Addressing of a memory level in which the access to the desired data or data block requires associative addressing means

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

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G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means

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Patents Grantslast 30 patents

Information Patent Grant
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Addressing of a memory level in which the access to the desired data or data block requires associative addressing means

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Programmable core integrated with hardware pipeline of network inte...

Data routing for efficient decompression of compressed data stored...

Systems, methods and devices for exploiting value similarity in com...

Method of managing access rights for software tasks executed by a m...

Systems and methods for joint de-interleaving and rate recovery in...

Signal development caching in a memory device

Workload-based cache compression in a distributed storage system

Semiconductor device with hypervisor-based cache management for mul...

Storage device, system including storage device and method operatin...

Efficient key-value cache management for large language models

Selection of victim entry in a data structure

Automated predictive caching of cloud-sourced data and methods of u...

Memory controller, storage device including the memory controller,...

Input/output (I/O) store protocol for pipelining coherent operations

Precomputed cache validation

Tracking memory modifications at cache line granularity

Methods and apparatus to facilitate atomic operations in victim cache

Systems and methods for a content-addressable peer-to-peer storage...

Techniques for runtime protocol conformance cache for third party

Implicit fence for write messages

Victim cache with write miss merging

Managing power loss recovery using a dirty section write policy for...

Modifying processing of commands in a command queue based on access...

Storage system and method providing cache area in memory included i...

Cache memory with per-sector cache residency controls

Technologies for memory and I/O efficient operations on homomorphic...

Memory system and operations of the same

Systems and methods for generating a graphical representation of a...

Method and apparatus for increasing memory level parallelism by red...

Apparatus and method with cache control

Patents Applicationslast 30 patents

STORAGE CONTROLLER, MEMORY MANAGEMENT METHOD AND STORAGE DEVICE

MEMORY DEVICE SUPPORTING METADATA MODE AND OPERATION METHOD OF MEMO...

Modifying Processing of Commands in a Command Queue Based on Access...

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

CACHING STRATEGY BASED ON MODEL EXECUTION TIME

REGISTER RENAMING CACHING

TRAFFIC AWARE SMART CACHING IN FABRIC SWITCHES

DATA PROCESSING METHOD, SYSTEM AND APPARATUS, AND ELECTRONIC DEVICE...

SYSTEMS AND METHODS FOR CACHING METADATA

STORAGE METHOD AND APPARATUS, AND ELECTRONIC DEVICE

APPARATUS AND METHOD FOR DATA MANIPULATION DETECTION OR REPLAY PROT...

CACHE AWARE SEARCHING

HIGH-FIDELITY EVENT DATA FOR MULTI-CLOUD SERVICES

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

TECHNOLOGIES FOR DYNAMIC ACCELERATOR SELECTION

METHOD FOR GENERATING TRAINING DATA FOR CACHE MEMORY DESIGN BASED O...

MEMORY MODULE WITH LOCAL SYNCHRONIZATION

SMART CACHING BASED ON REPUTATION INFORMATION

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

WRITE BROADCAST OPERATIONS ASSOCIATED WITH A MEMORY DEVICE

DATA REDUCTION METHOD, APPARATUS, AND SYSTEM

DATA CACHING METHOD AND APPARATUS, DEVICE, AND STORAGE MEDIUM

STORAGE DEVICE AND A METHOD OF CONTROLLING DATA STORING AREA

MANAGING A PROGRAMMABLE CACHE CONTROL MAPPING TABLE IN A SYSTEM LEV...

DATA INITIALIZATION TECHNIQUES

TRANSACTION INTERLOCKS FOR A DISTRIBUTED SYSTEM

DYNAMIC SINGLE-LEVEL CELL WRITE THROUGH IN MEMORY DEVICES

MEMORY VIRTUALIZATION FOR ACCESSING HETEROGENEOUS MEMORY COMPONENTS

SINGLE-PHASE COMMIT FOR REPLICATED CACHE DATA

Performant Data Caching