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Accessing, addressing or allocating within memory systems or architectures
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CPC
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Parent Industries
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PHYSICS
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Computing
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ELECTRICAL DIGITAL DATA PROCESSING
Current Industry
G06F12/00
Accessing, addressing or allocating within memory systems or architectures
Sub Industries
G06F12/02
Addressing or allocation Relocation
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with multidimensional access
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with look ahead addressing means
G06F12/0223
User address space allocation
G06F12/023
Free address space management
G06F12/0238
in non-volatile memory
G06F12/0246
in block erasable memory
G06F12/0253
Garbage collection
G06F12/0261
using reference counting
G06F12/0269
Incremental or concurrent garbage collection
G06F12/0276
Generational garbage collection
G06F12/0284
Multiple user address space allocation
G06F12/0292
using tables or multilevel address translation means
G06F12/04
Addressing variable-length words or parts of words
G06F12/06
Addressing a physical block of locations
G06F12/0607
Interleaved addressing
G06F12/0615
Address space extension
G06F12/0623
for memory modules
G06F12/063
for I/O modules
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Combination of memories
G06F12/0646
Configuration or reconfiguration
G06F12/0653
with centralised address assignment
G06F12/0661
and decentralised selection
G06F12/0669
with decentralised address assignment
G06F12/0676
the address being position dependent
G06F12/0684
with feedback
G06F12/0692
Multiconfiguration
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in hierarchically structured memory systems
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Addressing of a memory level in which the access to the desired data or data block requires associative addressing means
G06F12/0804
with main memory updating
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Multiuser, multiprocessor, multiprocessing cache systems
G06F12/0808
with cache invalidating means
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with multilevel cache hierarchies
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with a network or matrix configuration
G06F12/0815
Cache consistency protocols
G06F12/0817
using directory methods
G06F12/082
Associative directories
G06F12/0822
Copy directories
G06F12/0824
Distributed directories
G06F12/0826
Limited pointers directories; State-only directories without pointers
G06F12/0828
with concurrent directory accessing
G06F12/0831
using a bus scheme (
G06F12/0833
in combination with broadcast means (
G06F12/0835
for main memory peripheral accesses (
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with software control (
G06F12/084
with a shared cache
G06F12/0842
for multiprocessing or multitasking
G06F12/0844
Multiple simultaneous or quasi-simultaneous cache accessing
G06F12/0846
Cache with multiple tag or data arrays being simultaneously accessible
G06F12/0848
Partitioned cache
G06F12/0851
Cache with interleaved addressing
G06F12/0853
Cache with multiport tag or data arrays
G06F12/0855
Overlapped cache accessing
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by multiple requestors
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with reload from main memory
G06F12/0862
with prefetch
G06F12/0864
using pseudo-associative means
G06F12/0866
for peripheral storage systems
G06F12/0868
Data transfer between cache memory and other subsystems
G06F12/0871
Allocation and management of cache space
G06F12/0873
Mapping of cache memory to specific storage devices or parts of a storage device
G06F12/0875
with dedicated cache
G06F12/0877
Cache access modes
G06F12/0879
Burst mode
G06F12/0882
Page mode
G06F12/0884
Parallel mode
G06F12/0886
Variable-length word access
G06F12/0888
using selective caching
G06F12/0891
using clearing, invalidating or resetting means
G06F12/0893
Organization and technology of caches
G06F12/0895
of parts of caches
G06F12/0897
with a plurality of cache hierarchy levels
G06F12/10
Address translation
G06F12/1009
using page tables
G06F12/1018
involving hashing techniques
G06F12/1027
using associative or pseudo-associative address translation means
G06F12/1036
for multiple virtual address spaces
G06F12/1045
associated with a data cache
G06F12/1054
the data cache being concurrently physically addressed
G06F12/1063
the data cache being concurrently virtually addressed
G06F12/1072
Decentralised address translation
G06F12/1081
for peripheral access to main memory
G06F12/109
for multiple virtual address spaces
G06F12/12
Replacement control
G06F12/121
using a replacement algorithm
G06F12/122
of the least frequently used type
G06F12/123
with an age list
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being minimized
G06F12/125
being generated by decoding an array or storage
G06F12/126
with special data handling
G06F12/127
using an additional replacement algorithm
G06F12/128
adapted to multidimensional cache systems
G06F12/14
Protection against unauthorised use of memory or access to memory
G06F12/1408
by using cryptography
G06F12/1416
by checking the object accessibility
G06F12/1425
the protection being physical
G06F12/1433
for a module or a part of a module
G06F12/1441
for a range
G06F12/145
the protection being virtual
G06F12/1458
by checking the subject access rights
G06F12/1466
Key-lock mechanism
G06F12/1475
in a virtual system
G06F12/1483
using an access-table
G06F12/1491
in a hierarchical protection system
G06F12/16
Protection against loss of memory contents
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Patent Grant
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Issue date
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Patent number
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Issue date
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Issue date
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Patent number
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Issue date
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Information
Patent Grant
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Patent number
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Issue date
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Patent Grant
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Patent number
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Issue date
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Patent Grant
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Issue date
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Patent Grant
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Issue date
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Patent Grant
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Patent number
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Patent Grant
Method and apparatus for replacing data from near to far memory ove...
Patent number
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Patent Grant
Multi-mode indexed cache in a processor
Patent number
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Patent Grant
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Patent number
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Issue date
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Patent Grant
Memory access determination
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Patent Grant
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Patent number
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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Issue date
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G06 - COMPUTING CALCULATING COUNTING
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G06 - COMPUTING CALCULATING COUNTING