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Accessing, addressing or allocating within memory systems or architectures
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Industry
CPC
G06F12/00
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Parent Industries
G
PHYSICS
G06
Computing
G06F
ELECTRICAL DIGITAL DATA PROCESSING
Current Industry
G06F12/00
Accessing, addressing or allocating within memory systems or architectures
Sub Industries
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Addressing or allocation Relocation
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with multidimensional access
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with look ahead addressing means
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User address space allocation
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Free address space management
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in non-volatile memory
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in block erasable memory
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Garbage collection
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using reference counting
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Incremental or concurrent garbage collection
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Generational garbage collection
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Multiple user address space allocation
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using tables or multilevel address translation means
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Addressing variable-length words or parts of words
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Addressing a physical block of locations
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Interleaved addressing
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Address space extension
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for memory modules
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for I/O modules
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Combination of memories
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Configuration or reconfiguration
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with centralised address assignment
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and decentralised selection
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with decentralised address assignment
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the address being position dependent
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with feedback
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Multiconfiguration
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in hierarchically structured memory systems
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Addressing of a memory level in which the access to the desired data or data block requires associative addressing means
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with main memory updating
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Multiuser, multiprocessor, multiprocessing cache systems
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with cache invalidating means
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with multilevel cache hierarchies
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with a network or matrix configuration
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Cache consistency protocols
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using directory methods
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Associative directories
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Copy directories
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Distributed directories
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Limited pointers directories; State-only directories without pointers
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with concurrent directory accessing
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using a bus scheme (
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in combination with broadcast means (
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for main memory peripheral accesses (
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with software control (
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with a shared cache
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for multiprocessing or multitasking
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Multiple simultaneous or quasi-simultaneous cache accessing
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Cache with multiple tag or data arrays being simultaneously accessible
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Partitioned cache
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Cache with interleaved addressing
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Cache with multiport tag or data arrays
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Overlapped cache accessing
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by multiple requestors
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with reload from main memory
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with prefetch
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using pseudo-associative means
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for peripheral storage systems
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Data transfer between cache memory and other subsystems
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Allocation and management of cache space
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Mapping of cache memory to specific storage devices or parts of a storage device
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with dedicated cache
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Cache access modes
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Burst mode
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Page mode
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Parallel mode
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Variable-length word access
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using selective caching
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using clearing, invalidating or resetting means
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Organization and technology of caches
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of parts of caches
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with a plurality of cache hierarchy levels
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Address translation
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using page tables
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involving hashing techniques
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using associative or pseudo-associative address translation means
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for multiple virtual address spaces
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associated with a data cache
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the data cache being concurrently physically addressed
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the data cache being concurrently virtually addressed
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Decentralised address translation
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for peripheral access to main memory
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for multiple virtual address spaces
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Replacement control
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using a replacement algorithm
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of the least frequently used type
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with an age list
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being minimized
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being generated by decoding an array or storage
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with special data handling
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using an additional replacement algorithm
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adapted to multidimensional cache systems
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Protection against unauthorised use of memory or access to memory
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by using cryptography
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by checking the object accessibility
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the protection being physical
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for a module or a part of a module
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for a range
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the protection being virtual
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by checking the subject access rights
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Key-lock mechanism
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in a virtual system
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using an access-table
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in a hierarchical protection system
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Protection against loss of memory contents
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