Alternation of true and inverted stages

Industry

CPC
G06F2207/3876

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled

Current Industry

G06F2207/3876Alternation of true and inverted stages

Industries

Patents Grantslast 30 patents

Information Patent Grant
M-bit race delay adder and method of operation
- Patent number 8,473,541
- Issue date Jun 25, 2013
- STMicroelectronics, Inc.
- William E. Ballachino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
M-bit race delay adder and method of operation
- Patent number 7,571,204
- Issue date Aug 4, 2009
- STMicroelectronics, Inc.
- William E. Ballachino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuitry to provide fast carry
- Patent number 6,359,466
- Issue date Mar 19, 2002
- Vantis Corporation
- Bradley A. Sharpe-Geisler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable function block
- Patent number 6,188,240
- Issue date Feb 13, 2001
- NEC Corporation
- Shogo Nakaya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient use of inverting cells in multiplier converter
- Patent number 6,122,655
- Issue date Sep 19, 2000
- Lucent Technologies Inc.
- Alexander Goldovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder with even/odd 1-bit adder cells
- Patent number 5,978,826
- Issue date Nov 2, 1999
- Lucent Techologies Inc.
- Ravi Kumar Kolagotla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital adder circuit
- Patent number 5,951,630
- Issue date Sep 14, 1999
- ARM Limited
- Jianwei Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rectifying transfer gate circuit
- Patent number 5,935,203
- Issue date Aug 10, 1999
- SamSung Electronics Co., Ltd.
- Takashi Nakashima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rectifying transfer gate circuit
- Patent number 5,822,235
- Issue date Oct 13, 1998
- Samsung Electronics Co. Ltd.
- Takashi Nakashima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rectifying transfer gate device
- Patent number 5,682,054
- Issue date Oct 28, 1997
- Samsung Electronics Co., Ltd.
- Takashi Nakashima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logical operation circuit and device having the same
- Patent number 5,617,345
- Issue date Apr 1, 1997
- Fujitsu Limited
- Shunsuke Kamijo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rectifying transfer gate circuit
- Patent number 5,604,429
- Issue date Feb 18, 1997
- Samsung Electronics Co., Ltd.
- Takashi Nakashima
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CMOS multiplexor
- Patent number 5,473,554
- Issue date Dec 5, 1995
- National Semiconductor Corporation
- D. Kevin Covey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital logic circuit for implementing fuzzy logic operators
- Patent number 5,446,438
- Issue date Aug 29, 1995
- Siemens Aktiengesellschaft
- Herbert Eichfeld
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully static 32 bit alu with two stage carry bypass
- Patent number 5,444,646
- Issue date Aug 22, 1995
- National Semiconductor Corporation
- D. Kevin Covey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined multiplier and accumulator
- Patent number 5,442,579
- Issue date Aug 15, 1995
- National Semiconductor Corporation
- Thomas W. S. Thomson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High speed adder using a varied carry scheme and related method
- Patent number 5,375,081
- Issue date Dec 20, 1994
- Motorola, Inc.
- Donald C. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Signed overflow sticky bits
- Patent number 5,319,588
- Issue date Jun 7, 1994
- National Semiconductor Corporation
- Ralph W. Haines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CPU with integrated multiply/accumulate unit
- Patent number 5,311,458
- Issue date May 10, 1994
- National Semiconductor Corporation
- Ralph W. Haines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Layout efficient 32-bit shifter/register with 16-bit interface
- Patent number 5,218,564
- Issue date Jun 8, 1993
- National Semiconductor Corporation
- Ralph W. Haines
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallel multiplier using skip array and modified wallace tree
- Patent number 5,181,185
- Issue date Jan 19, 1993
- Samsumg Electronics Co., Ltd.
- Tack D. Han
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary carry circuitry
- Patent number 5,163,019
- Issue date Nov 10, 1992
- Brooktree Corporation
- Lanny L. Lewyn
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital signal inversion employing cross-over switch
- Patent number 5,162,796
- Issue date Nov 10, 1992
- Inmos Limited
- Martin J. P. Bolton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital adder having a high-speed low-capacitance carry bypass sign...
- Patent number 5,146,424
- Issue date Sep 8, 1992
- Unisys Corporation
- LuVerne R. Peterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Lookahead adder with universal logic gates
- Patent number 5,043,934
- Issue date Aug 27, 1991
- Hewlett-Packard Company
- Joel D. Lamb
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Carry-select adder
- Patent number 5,027,312
- Issue date Jun 25, 1991
- Siemens Aktiengellschaft
- Karl Knauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Carry select multiplexer
- Patent number 5,027,311
- Issue date Jun 25, 1991
- Intel Corporation
- Diane E. Zion
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast gate and adder for microprocessor ALU
- Patent number 4,989,174
- Issue date Jan 29, 1991
- Commodore Business Machines, Inc.
- William F. Gardei
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for a parallel carry generation adder
- Patent number 4,956,802
- Issue date Sep 11, 1990
- Sun Microsystems, Inc.
- Curtis Priem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-place ripple-carry adder
- Patent number 4,931,981
- Issue date Jun 5, 1990
- Siemens Aktiengesellschaft
- Karl Knauer
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
M-BIT RACE DELAY ADDER AND METHOD OF OPERATION
- Publication number 20100036902
- Publication date Feb 11, 2010
- William E. Ballachino
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Inversion of alternate instruction and/or data bits in a computer
- Publication number 20080177817
- Publication date Jul 24, 2008
- Charles H. Moore
- G06 - COMPUTING CALCULATING COUNTING

Alternation of true and inverted stages

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

M-bit race delay adder and method of operation

M-bit race delay adder and method of operation

Circuitry to provide fast carry

Programmable function block

Efficient use of inverting cells in multiplier converter

Adder with even/odd 1-bit adder cells

Digital adder circuit

Rectifying transfer gate circuit

Rectifying transfer gate circuit

Rectifying transfer gate device

Logical operation circuit and device having the same

Rectifying transfer gate circuit

CMOS multiplexor

Digital logic circuit for implementing fuzzy logic operators

Fully static 32 bit alu with two stage carry bypass

Combined multiplier and accumulator

High speed adder using a varied carry scheme and related method

Signed overflow sticky bits

CPU with integrated multiply/accumulate unit

Layout efficient 32-bit shifter/register with 16-bit interface

Parallel multiplier using skip array and modified wallace tree

Binary carry circuitry

Digital signal inversion employing cross-over switch

Digital adder having a high-speed low-capacitance carry bypass sign...

Lookahead adder with universal logic gates

Carry-select adder

Carry select multiplexer

Fast gate and adder for microprocessor ALU

Method and apparatus for a parallel carry generation adder

Multi-place ripple-carry adder

Patents Applicationslast 30 patents

M-BIT RACE DELAY ADDER AND METHOD OF OPERATION

Inversion of alternate instruction and/or data bits in a computer