Claims
- 1. A digital signal processor for receiving and selectively processing a plurality of digital data signals, comprising:
- multiplier/accumulator means for receiving signed multiplier data and signed multiplicand data and for selectively multiplying and accumulating said signed multiplier data and multiplicand data thereby providing signed output data, wherein said signed multiplier data includes a multiplier sign bit representing the polarity of said signed multiplier data, said signed multiplicand data includes a multiplicand sign bit representing the polarity of said signed multiplicand data, and said signed output data includes an output sign bit representing the polarity of said output data, and
- overflow indicator means for receiving said multiplier sign bit, said multiplicand sign bit and said output sign bit, and for indicating a signed arithmetic overflow of a multiply and accumulate operation, comprising a pair of sticky flag bits representing said signed arithmetic overflow, wherein said sticky flag bits have mutually exclusive true states.
- 2. A signed arithmetic overflow indicator utilizable with a multiply/accumulate unit that performs sequential multiply and accumulate operations, wherein the multiply/accumulate unit includes a multiplier register having a sign bit, a multiplicand register having a sign bit and an accumulator register having a sign bit, said accumulator register being used to store a signed result of a signed multiply and accumulate operation, comprising:
- an overflow register comprising a positive overflow bit and a negative overflow bit;
- first means for receiving and storing the values of the multiplier sign bit, the multiplicand sign bit, the accumulator sign bit, the positive overflow bit, and the negative overflow bit after a first sequential multiply and accumulate operation; and
- second means for logically combining the values stored in said first means with a value of the accumulator bit after a second sequential multiply and accumulate operation on clock cycle t+1, and for generating values to be stored in the positive overflow bit and in the negative overflow bit after the second clock cycle t+1;
- wherein the positive overflow bit and the negative overflow bit have mutually exclusive true states.
- 3. A signed arithmetic overflow indicator as recited in claim 2, wherein the positive overflow bit is set equal to the logical state of a current accumulator sign bit when the logical states of a previous positive overflow bit and a previous negative overflow bit are both false, and when the logical state of a previous accumulator sign bit is false, and when the logical states of the previous multiplier sign bit and a previous multiplicand sign bit are equal, and wherein the negative overflow bit is set equal to the inverse of the logical state of the current accumulator sign bit when the logical states of the previous positive overflow bit and the previous negative overflow bit are both false, and when the logical state of the previous accumulator sign bit is true, and when the logical states of the previous multiplier sign bit and the previous multiplicand sign bit are not signal.
- 4. A signed arithmetic overflow indicator as recited in claim 3, wherein the second means sets the signed overflow bits substantially in accordance with the following:
- P.sub.(t+1) =A.sub.(t) (O.sub.(t) M.sub.(t)) P.sub.(t) N.sub.(t) A.sub.(t+1) +P.sub.(t),
- N.sub.(t+1) =A.sub.(t) (O.sub.(t) .sym.M.sub.(t)) P.sub.(t) N.sub.(t) A.sub.(t+1) +N.sub.(t),
- where P.sub.(t) =the logical state of the positive overflow bit at a first time interval t, N.sub.(t) =the logical state of the negative overflow bit at the first time interval t, P.sub.(t+1) =the logical state of the positive overflow bit at a second time interval t+1, N.sub.(t+1) =the logical state of the negative overflow bit at the second time interval t+1, A.sub.(t) =the logical state of the accumulator sign bit at the first time interval t, A.sub.(t+1) =the logical state of the accumulator sign bit at the second time interval t+1, O.sub.(t) =the logical state of the multiplier sign bit at the first time interval t, M.sub.(t) =the logical state of the multiplicand sign bit at the first time interval t, =logical equivalence, and .sym.=logical exclusive or.
Parent Case Info
This application is a divisional of application Ser. No. 07/712,208, filed Jun. 7, 1991 now U.S. Pat. No. 5,218,564 issued Jun. 8, 1993.
US Referenced Citations (6)
Divisions (1)
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Number |
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712208 |
Jun 1991 |
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