Arrangements in static stores specially adapted for testing by means external to the store

Industry

CPC
G11C29/48

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GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/48Arrangements in static stores specially adapted for testing by means external to the store

Industries

Patents Grantslast 30 patents

Information Patent Grant
Memory view for non-volatile memory module
- Patent number 11,971,818
- Issue date Apr 30, 2024
- Cadence Design Systems, Inc.
- Steven L. Gregor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system including an in-package sequencer to perform erro...
- Patent number 11,869,618
- Issue date Jan 9, 2024
- Micron Technology, Inc.
- Samir Mittal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
JTAG based architecture allowing multi-core operation
- Patent number 11,830,563
- Issue date Nov 28, 2023
- Micron Technology, Inc.
- Antonino Mondello
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory and operating method thereof
- Patent number 11,798,624
- Issue date Oct 24, 2023
- SK hynix Inc.
- Dong Uk Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage devices and methods of operating storage devices
- Patent number 11,791,013
- Issue date Oct 17, 2023
- Samsung Electronics Co., Ltd.
- Seungjun Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controller to detect malfunctioning address of memory device
- Patent number 11,783,910
- Issue date Oct 10, 2023
- RAMBUS INC.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan synchronous-write-through testing architectures for a memory d...
- Patent number 11,734,142
- Issue date Aug 22, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ming-Hung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for direct access hybrid testing
- Patent number 11,581,056
- Issue date Feb 14, 2023
- Micron Technology, Inc.
- Chiaki Dono
- G11 - INFORMATION STORAGE
Information Patent Grant
Electrical device with test interface
- Patent number 11,568,953
- Issue date Jan 31, 2023
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system self-testing operations
- Patent number 11,514,995
- Issue date Nov 29, 2022
- Micron Technology, Inc.
- Nathan A. Eckel
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller to detect malfunctioning address of memory device
- Patent number 11,501,848
- Issue date Nov 15, 2022
- RAMBUS INC.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device testing, and associated methods, devices, and systems
- Patent number 11,456,049
- Issue date Sep 27, 2022
- Micron Technology, Inc.
- Jason M. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for monitoring data error status in a memory
- Patent number 11,403,170
- Issue date Aug 2, 2022
- Macronix International Co., Ltd.
- Kuen Long Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interconnected command/address resources
- Patent number 11,342,042
- Issue date May 24, 2022
- Micron Technology, Inc.
- Jason M. Johnson
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory loopback systems and methods
- Patent number 11,327,113
- Issue date May 10, 2022
- Micron Technology, Inc.
- David D. Wilmoth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
JTAG based architecture allowing multi-core operation
- Patent number 11,322,223
- Issue date May 3, 2022
- Micron Technology, Inc.
- Antonino Mondello
- G11 - INFORMATION STORAGE
Information Patent Grant
Test architecture for die to die interconnect for three dimensional...
- Patent number 11,257,560
- Issue date Feb 22, 2022
- Intel Corporation
- Sreejit Chakravarty
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan synchronous-write-through testing architectures for a memory d...
- Patent number 11,256,588
- Issue date Feb 22, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ming-Hung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 11,250,928
- Issue date Feb 15, 2022
- Micron Technology, Inc.
- Michael Richard Spica
- G01 - MEASURING TESTING
Information Patent Grant
Shared error detection and correction memory
- Patent number 11,222,708
- Issue date Jan 11, 2022
- Micron Technology, Inc.
- Tomoyuki Shibata
- G11 - INFORMATION STORAGE
Information Patent Grant
Anti-hacking mechanisms for flash memory device
- Patent number 11,188,237
- Issue date Nov 30, 2021
- Silicon Storage Technology, Inc.
- Hieu Van Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device
- Patent number 11,156,658
- Issue date Oct 26, 2021
- Micron Technology, Inc.
- Chiaki Dono
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for accessing configurable memory during hard...
- Patent number 11,086,788
- Issue date Aug 10, 2021
- Intel Corporation
- Jun Pin Tan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual tap architecture for enabling secure access for DDR memory tes...
- Patent number 11,037,651
- Issue date Jun 15, 2021
- QUALCOMM Incorporated
- Arvind Jain
- G11 - INFORMATION STORAGE
Information Patent Grant
Controller to detect malfunctioning address of memory device
- Patent number 11,037,652
- Issue date Jun 15, 2021
- Rambus, Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and method for testing three-dimensional memory device
- Patent number 10,998,079
- Issue date May 4, 2021
- Yangtze Memory Technologies Co., Ltd.
- Jong Jun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory sub-system including an in-package sequencer to perform erro...
- Patent number 10,991,445
- Issue date Apr 27, 2021
- Micron Technology, Inc.
- Samir Mittal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system self-testing operations
- Patent number 10,984,881
- Issue date Apr 20, 2021
- Micron Technology, Inc.
- Nathan A. Eckel
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage device with test interface
- Patent number 10,930,366
- Issue date Feb 23, 2021
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for direct access hybrid testing
- Patent number 10,896,738
- Issue date Jan 19, 2021
- Micron Technology, Inc.
- Chiaki Dono
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE
- Publication number 20240071559
- Publication date Feb 29, 2024
- Rambus Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY D...
- Publication number 20230342272
- Publication date Oct 26, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ming-Hung CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING SYSTEM ERROR MANAGEMENT, RELATED INTEGRATED CIRCUIT, APP...
- Publication number 20230065623
- Publication date Mar 2, 2023
- STMicroelectronics Application GmbH
- Vivek Mohan Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY AND OPERATING METHOD THEREOF
- Publication number 20220359013
- Publication date Nov 10, 2022
- SK HYNIX INC.
- Dong Uk LEE
- G11 - INFORMATION STORAGE
Information Patent Application
JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION
- Publication number 20220254438
- Publication date Aug 11, 2022
- Micron Technology, Inc.
- Antonino Mondello
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE
- Publication number 20220238177
- Publication date Jul 28, 2022
- Rambus Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY D...
- Publication number 20220171688
- Publication date Jun 2, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ming-Hung CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE TESTING, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS
- Publication number 20220005541
- Publication date Jan 6, 2022
- Micron Technology, Inc.
- Jason M. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE
- Publication number 20210407619
- Publication date Dec 30, 2021
- Rambus Inc.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Application
JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION
- Publication number 20210335444
- Publication date Oct 28, 2021
- Micron Technology, Inc.
- Antonino Mondello
- G11 - INFORMATION STORAGE
Information Patent Application
INTERCONNECTED COMMAND/ADDRESS RESOURCES
- Publication number 20210304838
- Publication date Sep 30, 2021
- Micron Technology, Inc.
- Jason M. Johnson
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SUB-SYSTEM INCLUDING AN IN-PACKAGE SEQUENCER TO PERFORM ERRO...
- Publication number 20210233601
- Publication date Jul 29, 2021
- Micron Technology, Inc.
- Samir Mittal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SUB-SYSTEM SELF-TESTING OPERATIONS
- Publication number 20210210155
- Publication date Jul 8, 2021
- Micron Technology, Inc.
- Nathan A. Eckel
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRICAL DEVICE WITH TEST INTERFACE
- Publication number 20210142861
- Publication date May 13, 2021
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUSES AND METHODS FOR DIRECT ACCESS HYBRID TESTING
- Publication number 20210104293
- Publication date Apr 8, 2021
- Micron Technology, Inc.
- Chiaki Dono
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICE WITH TEST INTERFACE
- Publication number 20210020259
- Publication date Jan 21, 2021
- Micron Technology, Inc.
- Stephen Hanna
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY D...
- Publication number 20200293417
- Publication date Sep 17, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ming-Hung CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE
- Publication number 20200273534
- Publication date Aug 27, 2020
- RAMBUS INC.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Application
STRUCTURE AND METHOD FOR TESTING THREE-DIMENSIONAL MEMORY DEVICE
- Publication number 20200265913
- Publication date Aug 20, 2020
- YANGTZE MEMORY TECHNOLOGIES CO., LTD.
- Jong Jun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL TAP ARCHITECTURE FOR ENABLING SECURE ACCESS FOR DDR MEMORY TES...
- Publication number 20200143902
- Publication date May 7, 2020
- QUALCOMM Incorporated
- Arvind JAIN
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE
- Publication number 20200111540
- Publication date Apr 9, 2020
- RAMBUS INC.
- Adrian E. Ong
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SUB-SYSTEM INCLUDING AN IN-PACKAGE SEQUENCER TO PERFORM ERRO...
- Publication number 20200082901
- Publication date Mar 12, 2020
- Micron Technology, Inc.
- Samir Mittal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR FAULT ANALYSIS DEVICE AND FAULT ANALYSIS METHOD THEREOF
- Publication number 20190385695
- Publication date Dec 19, 2019
- Samsung Electronics Co., Ltd.
- Changwook JEONG
- G01 - MEASURING TESTING
Information Patent Application
SHARED ERROR DETECTION AND CORRECTION MEMORY
- Publication number 20190362803
- Publication date Nov 28, 2019
- Micron Technology, Inc.
- Tomoyuki Shibata
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND DEVICE FOR MONITORING DATA ERROR STATUS IN A MEMORY
- Publication number 20190347159
- Publication date Nov 14, 2019
- MACRONIX INTERNATIONAL CO., LTD
- Kuen Long CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM AND METHOD OF DESIGNING THE SAME
- Publication number 20190318800
- Publication date Oct 17, 2019
- NANYA TECHNOLOGY CORPORATION
- Ting-Shuo HSU
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED ERROR DETECTION AND CORRECTION MEMORY
- Publication number 20190295679
- Publication date Sep 26, 2019
- Micron Technology, Inc.
- Chiaki Dono
- G11 - INFORMATION STORAGE
Information Patent Application
Use of wrapper cells to improve signal routing in integrated circuits
- Publication number 20190227124
- Publication date Jul 25, 2019
- MELLANOX TECHNOLOGIES, LTD.
- Ido Bourstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE FOR PERFORMING INTERNAL PROCESS AND OPERATING METHOD...
- Publication number 20190198061
- Publication date Jun 27, 2019
- Samsung Electronics Co., Ltd.
- REUM OH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, Apparatus and Electronic Device For Read/Write Speed Testing
- Publication number 20190189238
- Publication date Jun 20, 2019
- ZHUHAI JUNTIAN ELECTRONIC TECHNOLOGY CO., LTD.
- Zhenbei YU
- G11 - INFORMATION STORAGE

Arrangements in static stores specially adapted for testing by means external to the store

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory view for non-volatile memory module

Memory sub-system including an in-package sequencer to perform erro...

JTAG based architecture allowing multi-core operation

Semiconductor memory and operating method thereof

Storage devices and methods of operating storage devices

Controller to detect malfunctioning address of memory device

Scan synchronous-write-through testing architectures for a memory d...

Apparatuses and methods for direct access hybrid testing

Electrical device with test interface

Memory sub-system self-testing operations

Controller to detect malfunctioning address of memory device

Memory device testing, and associated methods, devices, and systems

Method and device for monitoring data error status in a memory

Interconnected command/address resources

Memory loopback systems and methods

JTAG based architecture allowing multi-core operation

Test architecture for die to die interconnect for three dimensional...

Scan synchronous-write-through testing architectures for a memory d...

Test access port architecture to facilitate multiple testing modes

Shared error detection and correction memory

Anti-hacking mechanisms for flash memory device

Semiconductor memory device

Methods and apparatus for accessing configurable memory during hard...

Dual tap architecture for enabling secure access for DDR memory tes...

Controller to detect malfunctioning address of memory device

Structure and method for testing three-dimensional memory device

Memory sub-system including an in-package sequencer to perform erro...

Memory sub-system self-testing operations

Storage device with test interface

Apparatuses and methods for direct access hybrid testing

Patents Applicationslast 30 patents

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY D...

PROCESSING SYSTEM ERROR MANAGEMENT, RELATED INTEGRATED CIRCUIT, APP...

SEMICONDUCTOR MEMORY AND OPERATING METHOD THEREOF

JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY D...

MEMORY DEVICE TESTING, AND ASSOCIATED METHODS, DEVICES, AND SYSTEMS

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

JTAG BASED ARCHITECTURE ALLOWING MULTI-CORE OPERATION

INTERCONNECTED COMMAND/ADDRESS RESOURCES

MEMORY SUB-SYSTEM INCLUDING AN IN-PACKAGE SEQUENCER TO PERFORM ERRO...

MEMORY SUB-SYSTEM SELF-TESTING OPERATIONS

ELECTRICAL DEVICE WITH TEST INTERFACE

APPARATUSES AND METHODS FOR DIRECT ACCESS HYBRID TESTING

STORAGE DEVICE WITH TEST INTERFACE

SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY D...

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

STRUCTURE AND METHOD FOR TESTING THREE-DIMENSIONAL MEMORY DEVICE

DUAL TAP ARCHITECTURE FOR ENABLING SECURE ACCESS FOR DDR MEMORY TES...

CONTROLLER TO DETECT MALFUNCTIONING ADDRESS OF MEMORY DEVICE

MEMORY SUB-SYSTEM INCLUDING AN IN-PACKAGE SEQUENCER TO PERFORM ERRO...

SEMICONDUCTOR FAULT ANALYSIS DEVICE AND FAULT ANALYSIS METHOD THEREOF

SHARED ERROR DETECTION AND CORRECTION MEMORY

METHOD AND DEVICE FOR MONITORING DATA ERROR STATUS IN A MEMORY

DRAM AND METHOD OF DESIGNING THE SAME

SHARED ERROR DETECTION AND CORRECTION MEMORY

Use of wrapper cells to improve signal routing in integrated circuits

MEMORY DEVICE FOR PERFORMING INTERNAL PROCESS AND OPERATING METHOD...

Method, Apparatus and Electronic Device For Read/Write Speed Testing