based on architectures providing a highly parallelized implementation

Industry

CPC
H03M13/3966

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Parent Industries

HELECTRICITY H03Electronic circuits H03MCODING DECODING CODE CONVERSION IN GENERAL H03M13/00Coding, decoding or code conversion, for error detection or error correction Coding theory basic assumptions Coding bounds Error probability evaluation methods Channel models Simulation or testing of codes

Current Industry

H03M13/3966based on architectures providing a highly parallelized implementation

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Patents Grantslast 30 patents

Information Patent Grant
Parallel implementation of maximum a posteriori probability decoder
- Patent number 9,348,798
- Issue date May 24, 2016
- The MathWorks, Inc.
- Brian J. Fanous
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel implementation of maximum a posteriori probability decoder
- Patent number 8,594,217
- Issue date Nov 26, 2013
- The MathWorks, Inc.
- Brian Fanous
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of and apparatus for implementing fast orthogonal transforms...
- Patent number 7,870,176
- Issue date Jan 11, 2011
- ASOCS Ltd.
- Doron Solomon
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method of switching from parallel to serial MAP detector
- Patent number 7,650,561
- Issue date Jan 19, 2010
- Seagate Technology LLC
- Bengt A. Ulriksson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for a multi-channel add-compare-select unit
- Patent number 7,613,990
- Issue date Nov 3, 2009
- Xilinx, Inc.
- William A. Wilkie
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Maximum likelihood detector and/or decoder
- Patent number 7,263,652
- Issue date Aug 28, 2007
- Arithmatica Limited
- Oleg Zaboronski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reduced-latency soft-in/soft-out module
- Patent number 7,197,691
- Issue date Mar 27, 2007
- University of Southern California
- Peter A. Beerel
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SCL PARALLEL DECODING METHOD AND APPARATUS AND DEVICE
- Publication number 20210184701
- Publication date Jun 17, 2021
- Huawei Technologies Co., Ltd
- Liang MA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PARALLEL IMPLEMENTATION OF MAXIMUM A POSTERIORI PROBABILITY DECODER
- Publication number 20140046995
- Publication date Feb 13, 2014
- The MathWorks, Inc.
- Brian J. FANOUS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARALLEL IMPLEMENTATION OF MAXIMUM A POSTERIORI PROBABILITY DECODER
- Publication number 20130142289
- Publication date Jun 6, 2013
- The MathWorks, Inc.
- Brian FANOUS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Methods and Apparatuses for Parallel Decoding and Data Processing o...
- Publication number 20090172495
- Publication date Jul 2, 2009
- VIA TELECOM, INC.
- Le Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW POWER VITERBI DECODER USING SCARCE STATE TRANSITION AND PATH PR...
- Publication number 20090089648
- Publication date Apr 2, 2009
- THE HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY
- Chi Ying Tsui
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method of and apparatus for implementing fast orthogonal transforms...
- Publication number 20060010188
- Publication date Jan 12, 2006
- Doron Solomon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Maximum likelihood detector and/or decoder
- Publication number 20050044474
- Publication date Feb 24, 2005
- Oleg Zaboronski
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reduced-latency soft-in/soft-out module
- Publication number 20040237025
- Publication date Nov 25, 2004
- University of Southern California
- Peter A. Beerel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Turbo-code decoder
- Publication number 20030149928
- Publication date Aug 7, 2003
- Yeun-Renn Ting
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Reduced-latency soft-in/soft-out module
- Publication number 20020021770
- Publication date Feb 21, 2002
- Peter A. Beerel
- H03 - BASIC ELECTRONIC CIRCUITRY

based on architectures providing a highly parallelized implementation

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Parallel implementation of maximum a posteriori probability decoder

Parallel implementation of maximum a posteriori probability decoder

Method of and apparatus for implementing fast orthogonal transforms...

Method of switching from parallel to serial MAP detector

Method and system for a multi-channel add-compare-select unit

Maximum likelihood detector and/or decoder

Reduced-latency soft-in/soft-out module

Patents Applicationslast 30 patents

SCL PARALLEL DECODING METHOD AND APPARATUS AND DEVICE

PARALLEL IMPLEMENTATION OF MAXIMUM A POSTERIORI PROBABILITY DECODER

PARALLEL IMPLEMENTATION OF MAXIMUM A POSTERIORI PROBABILITY DECODER

Methods and Apparatuses for Parallel Decoding and Data Processing o...

LOW POWER VITERBI DECODER USING SCARCE STATE TRANSITION AND PATH PR...

Method of and apparatus for implementing fast orthogonal transforms...

Maximum likelihood detector and/or decoder

Reduced-latency soft-in/soft-out module

Turbo-code decoder

Reduced-latency soft-in/soft-out module