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Coding, decoding or code conversion, for error detection or error correction Coding theory basic assumptions Coding bounds Error probability evaluation methods Channel models Simulation or testing of codes
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CPC
H03M13/00
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ELECTRICITY
H03
Electronic circuits
H03M
CODING DECODING CODE CONVERSION IN GENERAL
Current Industry
H03M13/00
Coding, decoding or code conversion, for error detection or error correction Coding theory basic assumptions Coding bounds Error probability evaluation methods Channel models Simulation or testing of codes
Sub Industries
H03M13/005
using punctured codes
H03M13/01
Coding theory basic assumptions Coding bounds Error probability evaluation methods Channel models Simulation or testing of codes
H03M13/015
Simulation or testing of codes
H03M13/03
Error detection or forward error correction by redundancy in data representation
H03M13/033
Theoretical methods to calculate these checking codes
H03M13/036
Heuristic code construction methods
H03M13/05
using block codes
H03M13/07
Arithmetic codes
H03M13/09
Error detection only
H03M13/091
Parallel or block-wise CRC computation
H03M13/093
CRC update after modification of the information word
H03M13/095
Error detection codes other than CRC and single parity bit codes
H03M13/096
Checksums
H03M13/098
using single parity bit
H03M13/11
using multiple parity bits
H03M13/1102
Codes on graphs and decoding on graphs
H03M13/1105
Decoding
H03M13/1108
Hard decision decoding
H03M13/1111
Soft-decision decoding
H03M13/1114
Merged schedule message passing algorithm with storage of sums of check-to-bit node messages or sums of bit-to-check node messages
H03M13/1117
using approximations for check node processing
H03M13/112
with correction functions for the min-sum rule
H03M13/1122
storing only the first and second minimum values per check node
H03M13/1125
using different domains for check node and bit node processing, wherein the different domains include probabilities, likelihood ratios, likelihood differences, log-likelihood ratios or log-likelihood difference pairs
H03M13/1128
Judging correct decoding and iterative stopping criteria other than syndrome check and upper limit for decoding iterations
H03M13/1131
Scheduling of bit node or check node processing
H03M13/1134
Full parallel processing
H03M13/1137
Partly parallel processing
H03M13/114
Shuffled, staggered, layered or turbo decoding schedules
H03M13/1142
using trapping sets
H03M13/1145
Pipelined decoding at code word level
H03M13/1148
Structural properties of the code parity-check or generator matrix
H03M13/1151
Algebraically constructed LDPC codes
H03M13/1154
Low-density parity-check convolutional codes [LDPC-CC]
H03M13/1157
Low-density generator matrices [LDGM]
H03M13/116
Quasi-cyclic LDPC [QC-LDPC] codes
H03M13/1162
Array based LDPC codes
H03M13/1165
QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications
H03M13/1168
wherein the sub-matrices have column and row weights greater than one
H03M13/1171
Parity-check or generator matrices with non-binary elements
H03M13/1174
Parity-check or generator matrices built from sub-matrices representing known block codes such as
H03M13/1177
Regular LDPC codes with parity-check matrices wherein all rows and columns have the same row weight and column weight, respectively
H03M13/118
Parity check matrix structured for simplifying encoding
H03M13/1182
wherein the structure of the parity-check matrix is obtained by reordering of a random parity-check matrix
H03M13/1185
wherein the parity-check matrix comprises a part with a double-diagonal
H03M13/1188
wherein in the part with the double-diagonal at least one column has an odd column weight equal or greater than three
H03M13/1191
Codes on graphs other than LDPC codes
H03M13/1194
Repeat-accumulate [RA] codes
H03M13/1197
Irregular repeat-accumulate [IRA] codes
H03M13/13
Linear codes
H03M13/132
Algebraic geometric codes
H03M13/134
Non-binary linear block codes not provided for otherwise
H03M13/136
Reed-Muller [RM] codes
H03M13/138
Codes linear in a ring
H03M13/15
Cyclic codes, i.e. cyclic shifts of codewords produce other codewords
H03M13/1505
Golay Codes
H03M13/151
using error location or error correction polynomials
H03M13/1515
Reed-Solomon codes
H03M13/152
Bose-Chaudhuri-Hocquenghem [BCH] codes
H03M13/1525
Determination and particular use of error location polynomials
H03M13/153
using the Berlekamp-Massey algorithm
H03M13/1535
using the Euclid algorithm
H03M13/154
Error and erasure correction
H03M13/1545
Determination of error locations
H03M13/155
Shortening or extension of codes
H03M13/1555
Pipelined decoder implementations
H03M13/156
Encoding or decoding using time-frequency transformations
H03M13/1565
Decoding beyond the bounded minimum distance [BMD]
H03M13/157
Polynomial evaluation
H03M13/1575
Direct decoding
H03M13/158
Finite field arithmetic processing
H03M13/1585
Determination of error values
H03M13/159
Remainder calculation
H03M13/1595
Parallel or block-wise remainder calculation
H03M13/17
Burst error correction
H03M13/175
Error trapping or Fire codes
H03M13/19
Single error correction without using particular properties of the cyclic codes
H03M13/21
Non-linear codes
H03M13/23
using convolutional codes
H03M13/235
Encoding of convolutional codes
H03M13/25
Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation
H03M13/251
with block coding
H03M13/253
with concatenated codes
H03M13/255
with Low Density Parity Check [LDPC] codes
H03M13/256
with trellis coding
H03M13/258
with turbo codes
H03M13/27
using interleaving techniques
H03M13/2703
the interleaver involving at least two directions
H03M13/2707
Simple row-column interleaver
H03M13/271
Row-column interleaver with permutations
H03M13/2714
Turbo interleaver for 3rd generation partnership project [3GPP] universal mobile telecommunications systems [UMTS]
H03M13/2717
the interleaver involves 3 or more directions
H03M13/2721
the interleaver involves a diagonal direction
H03M13/2725
Turbo interleaver for 3rd generation partnership project 2 [3GPP2] mobile telecommunication systems
H03M13/2728
Helical type interleaver
H03M13/2732
Convolutional interleaver; Interleavers using shift-registers or delay lines like
H03M13/2735
Interleaver using powers of a primitive element
H03M13/2739
Permutation polynomial interleaver
H03M13/2742
Irregular interleaver wherein the permutation pattern is not obtained by a computation rule
H03M13/2746
S-random interleaver
H03M13/275
Interleaver wherein the permutation pattern is obtained using a congruential operation of the type y=ax+b modulo c
H03M13/2753
Almost regular permutation [ARP] interleaver
H03M13/2757
Interleaver with an interleaving rule not provided for in the subgroups H03M13/2703 - H03M13/2753
H03M13/276
Interleaving address generation
H03M13/2764
Circuits therefore
H03M13/2767
Interleaver wherein the permutation pattern or a portion thereof is stored
H03M13/2771
Internal interleaver for turbo codes
H03M13/2775
Contention or collision free turbo code internal interleaver
H03M13/2778
Interleaver using block-wise interleaving
H03M13/2782
Interleaver implementations, which reduce the amount of required interleaving memory
H03M13/2785
Interleaver using in-place interleaving
H03M13/2789
Interleaver providing variable interleaving
H03M13/2792
Interleaver wherein interleaving is performed jointly with another technique such as puncturing, multiplexing or routing
H03M13/2796
Two or more interleaving operations are performed jointly
H03M13/29
combining two or more codes or code structures
H03M13/2903
Methods and arrangements specifically for encoding
H03M13/2906
using block codes
H03M13/2909
Product codes
H03M13/2912
omitting parity on parity
H03M13/2915
with an error detection code in one dimension
H03M13/2918
with error correction codes in three or more dimensions
H03M13/2921
wherein error correction coding involves a diagonal direction
H03M13/2924
Cross interleaved Reed-Solomon codes [CIRC]
H03M13/2927
Decoding strategies
H03M13/293
with erasure setting
H03M13/2933
using a block and a convolutional code
H03M13/2936
comprising an outer Reed-Solomon code and an inner convolutional code
H03M13/2939
using convolutional codes
H03M13/2942
wherein a block of parity bits is computed only from combined information bits or only from parity bits
H03M13/2945
using at least three error correction codes
H03M13/2948
Iterative decoding
H03M13/2951
using iteration stopping criteria
H03M13/2954
using Picket codes or other codes providing error burst detection capabilities
H03M13/2957
Turbo codes and decoding
H03M13/296
Particular turbo code structure
H03M13/2963
Turbo-block codes, i.e. turbo codes based on block codes
H03M13/2966
Turbo codes concatenated with another code
H03M13/2969
Non-binary turbo codes
H03M13/2972
Serial concatenation using convolutional component codes
H03M13/2975
Judging correct decoding
H03M13/2978
Particular arrangement of the component decoders
H03M13/2981
using as many component decoders as component codes
H03M13/2984
using less component decoders than component codes
H03M13/2987
using more component decoders than component codes
H03M13/299
Turbo codes with short blocks
H03M13/2993
Implementing the return to a predetermined state
H03M13/2996
Tail biting
H03M13/31
combining coding for error detection or correction and efficient use of the spectrum
H03M13/33
Synchronisation based on error coding or decoding
H03M13/333
Synchronisation on a multi-bit block basis
H03M13/336
Phase recovery
H03M13/35
Unequal or adaptive error protection
H03M13/353
Adaptation to the channel
H03M13/356
Unequal error protection [UEP]
H03M13/37
Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
H03M13/3707
Adaptive decoding and hybrid decoding
H03M13/3715
Adaptation to the number of estimated errors or to the channel state
H03M13/3723
using means or methods for the initialisation of the decoder
H03M13/373
with erasure correction and erasure determination
H03M13/3738
with judging correct decoding
H03M13/3746
with iterative decoding
H03M13/3753
using iteration stopping criteria
H03M13/3761
using code combining, i.e. using combining of codeword portions which may have been transmitted separately
H03M13/3769
using symbol combining
H03M13/3776
using a re-encoding step during the decoding process
H03M13/3784
for soft-output decoding of block codes
H03M13/3792
for decoding of real number codes
H03M13/39
Sequence estimation
H03M13/3905
Maximum a posteriori probability [MAP] decoding and approximations thereof based on trellis or lattice decoding
H03M13/3911
Correction factor
H03M13/3916
for block codes using a trellis or lattice
H03M13/3922
Add-Compare-Select [ACS] operation in forward or backward recursions
H03M13/3927
Log-Likelihood Ratio [LLR] computation by combination of forward and backward metrics into LLRs
H03M13/3933
Decoding in probability domain
H03M13/3938
Tail-biting
H03M13/3944
for block codes, especially trellis or lattice decoding thereof
H03M13/395
using a collapsed trellis
H03M13/3955
using a trellis with a reduced state space complexity
H03M13/3961
Arrangements of methods for branch or transition metric calculation
H03M13/3966
based on architectures providing a highly parallelized implementation
H03M13/3972
using sliding window techniques or parallel windows
H03M13/3977
using sequential decoding
H03M13/3983
for non-binary convolutional codes
H03M13/3988
for rate k/n convolutional codes, with k>1, obtained by convolutional encoders with k inputs and n outputs
H03M13/3994
using state pinning or decision forcing
H03M13/41
using the Viterbi algorithm or Viterbi processors
H03M13/4107
implementing add, compare, select [ACS] operations
H03M13/4115
list output Viterbi decoding
H03M13/4123
implementing the return to a predetermined state
H03M13/413
tail biting Viterbi decoding
H03M13/4138
soft-output Viterbi algorithm based decoding
H03M13/4146
soft-output Viterbi decoding according to Battail and Hagenauer in which the soft-output is determined using path metric differences along the maximum-likelihood path
H03M13/4153
two-step SOVA decoding
H03M13/4161
implementing path management
H03M13/4169
using traceback
H03M13/4176
using a plurality of RAMs
H03M13/4184
using register-exchange
H03M13/4192
using combined traceback and register-exchange
H03M13/42
MAP decoding or approximations thereof based on trellis or lattice decoding
H03M13/43
Majority logic or threshold decoding
H03M13/45
Soft decoding
H03M13/451
using a set of candidate code words
H03M13/453
wherein the candidate code words are obtained by an algebraic decoder
H03M13/455
using a set of erasure patterns or successive erasure decoding
H03M13/456
wherein all the code words of the code or its dual code are tested
H03M13/458
by updating bit probabilities or hard decisions in an iterative fashion for convergence to a final decoding result
H03M13/47
Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
H03M13/49
Unidirectional error detection or correction
H03M13/51
Constant weight codes n-out-of-m codes Berger codes
H03M13/53
Codes using Fibonacci numbers series
H03M13/61
Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
H03M13/611
Specific encoding aspects
H03M13/612
Aspects specific to channel or signal-to-noise ratio estimation
H03M13/613
Use of the dual code
H03M13/615
Use of computational or mathematical techniques
H03M13/616
Matrix operations, especially for generator matrices or check matrices
H03M13/617
Polynomial operations
H03M13/618
Shortening and extension of codes
H03M13/63
Joint error correction and other techniques
H03M13/6306
Error control coding in combination with Automatic Repeat reQuest [ARQ] and diversity transmission
H03M13/6312
Error control coding in combination with data compression
H03M13/6318
using variable length codes
H03M13/6325
Error control coding in combination with demodulation
H03M13/6331
Error control coding in combination with equalisation
H03M13/6337
Error control coding in combination with channel estimation
H03M13/6343
Error control coding in combination with techniques for partial response channels
H03M13/635
Error control coding in combination with rate matching
H03M13/6356
by repetition or insertion of dummy data
H03M13/6362
by puncturing
H03M13/6368
using rate compatible puncturing or complementary puncturing
H03M13/6375
Rate compatible punctured convolutional [RCPC] codes
H03M13/6381
Rate compatible punctured turbo [RCPT] codes
H03M13/6387
Complementary punctured convolutional [CPC] codes
H03M13/6393
Rate compatible low-density parity check [LDPC] codes
H03M13/65
Purpose and implementation aspects
H03M13/6502
Reduction of hardware complexity or efficient processing
H03M13/6505
Memory efficient implementations
H03M13/6508
Flexibility, adaptability, parametrability and configurability of the implementation
H03M13/6511
Support of multiple decoding rules
H03M13/6513
Support of multiple code types
H03M13/6516
Support of multiple code parameters
H03M13/6519
Support of multiple transmission or communication standards
H03M13/6522
Intended application
H03M13/6525
3GPP LTE including E-UTRA
H03M13/6527
IEEE 802.11 [WLAN]
H03M13/653
3GPP HSDPA
H03M13/6533
ITU 992.X [ADSL]
H03M13/6536
GSM GPRS
H03M13/6538
ATSC VBS systems
H03M13/6541
DVB-H and DVB-M
H03M13/6544
IEEE 802.16 (WIMAX and broadband wireless access)
H03M13/6547
TCP, UDP, IP and associated protocols
H03M13/655
UWB OFDM
H03M13/6552
DVB-T2
H03M13/6555
DVB-C2
H03M13/6558
3GPP2
H03M13/6561
Parallelized implementations
H03M13/6563
Implementations using multi-port memories
H03M13/6566
Implementations concerning memory access contentions
H03M13/6569
Implementation on processors
H03M13/6572
Implementations using a tree structure
H03M13/6575
Implementations based on combinatorial logic
H03M13/6577
Representation or format of variables, register sizes or word-lengths and quantization
H03M13/658
Scaling by multiplication or division
H03M13/6583
Normalization other than scaling
H03M13/6586
Modulo/modular normalization
H03M13/6588
Compression or short representation of variables
H03M13/6591
Truncation, saturation and clamping
H03M13/6594
Non-linear quantization
H03M13/6597
Implementations using analogue techniques for coding or decoding
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Patent number
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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Issue date
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H03 - BASIC ELECTRONIC CIRCUITRY
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Patent number
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Issue date
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Patent number
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Issue date
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Publication date
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Publication date
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Korea Advanced Institute of Science and Technology
Jeongseok HA
G06 - COMPUTING CALCULATING COUNTING
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Patent Application
CHANNEL CODING METHOD AND APPARATUS
Publication number
20250150097
Publication date
May 8, 2025
Huawei Technologies Co., Ltd
Weilin Qu
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
METHODS AND SYSTEMS FOR DATA TRANSMISSION
Publication number
20250150203
Publication date
May 8, 2025
Marvell Asia Pte Ltd.
Benjamin Smith
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
MEMORY SYSTEM AND NONVOLATILE MEMORY
Publication number
20250147842
Publication date
May 8, 2025
KIOXIA Corporation
Daisuke ARIZONO
G06 - COMPUTING CALCULATING COUNTING
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Patent Application
APPARATUS AND METHOD FOR POWER REDUCTION IN A BIT FLIPPING DECODER
Publication number
20250150095
Publication date
May 8, 2025
SK HYNIX INC.
Bi Woong CHUNG
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
COMMUNICATION DEVICE WITH INTERLEAVED ENCODING FOR FEC ENCODED DATA...
Publication number
20250150098
Publication date
May 8, 2025
Marvell Asia Pte Ltd.
Benjamin P. SMITH
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
ULTRA-WIDEBAND METHOD AND APPARATUS
Publication number
20250150116
Publication date
May 8, 2025
DecaWave, Ltd
Michael McLaughlin
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
HARQ FOR ADVANCED CHANNEL CODES
Publication number
20250141595
Publication date
May 1, 2025
INTERDIGITAL PATENT HOLDINGS, INC.
Chunxuan Ye
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
STAIRCASE MATRIX CODE AND HIGHLY PARALLEL LOW-LATENCY ORDERED STATI...
Publication number
20250141472
Publication date
May 1, 2025
SUN YAT-SEN UNIVERSITY
Xiao MA
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
SIGNALING WITH UNEQUAL AND FINER MCS
Publication number
20250141511
Publication date
May 1, 2025
Juan Fang
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
TECHNIQUES FOR GENERATING AND USING LONGER LOW-DENSITY PARITY CHECK...
Publication number
20250141596
Publication date
May 1, 2025
QUALCOMM Incorporated
Kanke Wu
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
FAIR-DENSITY PARITY-CHECK CODING AND DECODING
Publication number
20250141471
Publication date
May 1, 2025
Northeastern University
Hessam Mahdavifar
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
COMMUNICATION METHOD AND COMMUNICATION APPARATUS
Publication number
20250141473
Publication date
May 1, 2025
Huawei Technologies Co., Ltd
Jiajie TONG
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
METHOD FOR DETERMINING LENGTH OF LDPC CODE WORD IN UWB SYSTEM AND R...
Publication number
20250132862
Publication date
Apr 24, 2025
Huawei Technologies Co., Ltd
Wei LIN
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
BIT-FLIPPING DECODER AND DECODING METHOD BASED ON SUPER NODE
Publication number
20250132772
Publication date
Apr 24, 2025
SK HYNIX INC.
Fan ZHANG
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
ERROR CORRECTION DECODING DEVICE AND ERROR CORRECTION DECODING METHOD
Publication number
20250132774
Publication date
Apr 24, 2025
Mitsubishi Electric Corporation
Tsuyoshi YOSHIDA
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
Synchronization Log for Replicated Data in a Storage Network
Publication number
20250131013
Publication date
Apr 24, 2025
PURE STORAGE, INC.
Jason K. Resch
G06 - COMPUTING CALCULATING COUNTING
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Patent Application
PERFORMING CYCLIC REDUNDANCY CHECKS USING PARALLEL COMPUTING ARCHIT...
Publication number
20250132771
Publication date
Apr 24, 2025
NVIDIA Corporation
Andrea Miele
G06 - COMPUTING CALCULATING COUNTING
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Patent Application
Generalized Implicit Transmission
Publication number
20250132773
Publication date
Apr 24, 2025
Muhammad Ahsan Naim
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
BIT ERROR RATE ESTIMATION AND CLASSIFICATION IN NAND FLASH MEMORY
Publication number
20250124990
Publication date
Apr 17, 2025
KIOXIA Corporation
Eyal Nitzan
G11 - INFORMATION STORAGE
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Patent Application
WIRELESS COMMUNICATION DEVICE USING PLURALITY OF DEINTERLEAVING BUF...
Publication number
20250126626
Publication date
Apr 17, 2025
Samsung Electronics Co., Ltd.
Juhyuk IM
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
CONCATENATED POLAR CODE WITH ADAPTIVE ERROR DETECTION
Publication number
20250125823
Publication date
Apr 17, 2025
Telefonaktiebolaget LM Ericsson (publ)
Yufei Blankenship
H03 - BASIC ELECTRONIC CIRCUITRY
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Patent Application
ENCODING METHOD, DECODING METHOD, AND APPARATUS
Publication number
20250125821
Publication date
Apr 17, 2025
Huawei Technologies Co., Ltd
Wei LIN
H03 - BASIC ELECTRONIC CIRCUITRY