by changing characteristics of the loop filter

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H03L7/1075

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HELECTRICITY H03Electronic circuits H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES H03L7/00Automatic control of frequency or phase Synchronisation

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H03L7/1075by changing characteristics of the loop filter

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Patents Grantslast 30 patents

Information Patent Grant
Phase detectors with extrapolation of timing events
- Patent number 12,212,328
- Issue date Jan 28, 2025
- Analog Devices, Inc.
- Reuben P. Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock jitter and spurious tone cancellation system using optical delay
- Patent number 12,191,870
- Issue date Jan 7, 2025
- Cisco Technology, Inc.
- Abhishek Bhat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Modified control loop in a digital phase-locked loop
- Patent number 12,166,494
- Issue date Dec 10, 2024
- Kannanthodath V. Jayakumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dual digital phase lock loop with unmodulation coupling
- Patent number 12,015,414
- Issue date Jun 18, 2024
- RENESAS ELECTRONICS AMERICA INC.
- Menno Tjeerd Spijker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast frequency synthesizer switching
- Patent number 11,973,509
- Issue date Apr 30, 2024
- Silicon Laboratories Inc.
- Rangakrishnan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Synchronization between data and clock signals in high-speed interf...
- Patent number 11,962,310
- Issue date Apr 16, 2024
- Apple Inc.
- Nir Tishbi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Electronic apparatus and method for reducing coarse lock time of ph...
- Patent number 11,955,980
- Issue date Apr 9, 2024
- Samsung Electronics Co., Ltd.
- Venkatasuryam Setty Issa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and circuits for reducing clock jitter
- Patent number 11,831,323
- Issue date Nov 28, 2023
- Cadence Design Systems, Inc.
- Marcus Van Ierssel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reducing noise contribution in compensating for unequal successive...
- Patent number 11,711,087
- Issue date Jul 25, 2023
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase detectors with alignment to phase information lost in decimation
- Patent number 11,705,914
- Issue date Jul 18, 2023
- Analog Devices, Inc.
- Reuben P. Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduction of noise in output clock due to unequal successive time p...
- Patent number 11,658,667
- Issue date May 23, 2023
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital phase-locked loop
- Patent number 11,646,743
- Issue date May 9, 2023
- NXP USA, INC.
- Pawan Sabharwal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
PLL circuit using intermittent operation amplifier
- Patent number 11,606,097
- Issue date Mar 14, 2023
- Renesas Electronics Corporation
- Atsushi Motozawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Controlling synchronous I/O interface
- Patent number 11,575,385
- Issue date Feb 7, 2023
- U-BLOX AG
- Aneeb Sohail
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
First order memory-less dynamic element matching technique
- Patent number 11,417,371
- Issue date Aug 16, 2022
- STMICROELECTRONICS INTERNATIONAL N.V.
- Ankur Bal
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase-locked loop with phase noise cancellation
- Patent number 11,398,827
- Issue date Jul 26, 2022
- Cisco Technology, Inc.
- Abhishek Bhat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-tuning phase-locked loop (PLL) circuit
- Patent number 11,271,572
- Issue date Mar 8, 2022
- Analog Devices International Unlimited Company
- Wreeju Bhaumik
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Fast locking sequence for phase-locked loops
- Patent number 11,177,816
- Issue date Nov 16, 2021
- Analog Devices, Inc.
- Neil E. Weeks
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
First order memory-less dynamic element matching technique
- Patent number 11,094,354
- Issue date Aug 17, 2021
- STMICROELECTRONICS INTERNATIONAL N.V.
- Ankur Bal
- G11 - INFORMATION STORAGE
Information Patent Grant
Phase-locked loop with reduced frequency transients
- Patent number 11,038,513
- Issue date Jun 15, 2021
- Raytheon Company
- Gary I. Moore
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive timing synchronization for reception for bursty and contin...
- Patent number 10,965,437
- Issue date Mar 30, 2021
- Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
- Christian Rohde
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Adaptive timing synchronization for reception for bursty and contin...
- Patent number 10,958,410
- Issue date Mar 23, 2021
- Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
- Christian Rohde
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock data recovery circuit and apparatus including the same
- Patent number 10,924,119
- Issue date Feb 16, 2021
- Samsung Electronics Co., Ltd.
- Geumyoung Tak
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Spread spectrum clock generation apparatus and method, and display...
- Patent number 10,680,586
- Issue date Jun 9, 2020
- LG DISPLAY CO., LTD.
- Jaehun Jun
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit device, oscillator, electronic apparatus, and vehicle
- Patent number 10,613,234
- Issue date Apr 7, 2020
- Seiko Epson Corporation
- Katsuhito Nakajima
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for suppressing oscillator-induced spurs in fre...
- Patent number 10,566,982
- Issue date Feb 18, 2020
- Marvell International Ltd.
- Luca Vercesi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase adjusting circuit, inverter circuit, and power supply system
- Patent number 10,447,281
- Issue date Oct 15, 2019
- Sumida Corporation
- Hiroyuki Miyazaki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Radio signal processing device, semiconductor device, and oscillati...
- Patent number 10,419,009
- Issue date Sep 17, 2019
- Renesas Electronics Corporation
- Kenichi Shibata
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimum phase searching system and method thereof in ethernet physi...
- Patent number 10,382,047
- Issue date Aug 13, 2019
- ALi Corporation
- Rong-yun Li
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods of relocking for locked loops
- Patent number 10,374,651
- Issue date Aug 6, 2019
- QUALCOMM Incorporated
- Shyam Sundar Sivakumar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Patents Applicationslast 30 patents

Information Patent Application
PLL CIRCUIT
- Publication number 20240356557
- Publication date Oct 24, 2024
- ASAHI KASEI MICRODEVICES CORPORATION
- Takeji FUJIBAYASHI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE-LOCKED LOOP (PLL) WITH AUTOMATIC LOOP BANDWIDTH CONTROL
- Publication number 20240322830
- Publication date Sep 26, 2024
- QUALCOMM Incorporated
- Alessio SANTICCIOLI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK JITTER AND SPURIOUS TONE CANCELLATION SYSTEM USING OPTICAL DELAY
- Publication number 20240259025
- Publication date Aug 1, 2024
- Cisco Technology, Inc.
- Abhishek Bhat
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK AND DATA RECOVERY DEVICE
- Publication number 20240154616
- Publication date May 9, 2024
- Silicon Mitus, Inc.
- Young Jae Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DUAL DIGITAL PHASE LOCK LOOP WITH UNMODULATION COUPLING
- Publication number 20240120924
- Publication date Apr 11, 2024
- Renesas Electronics America Inc.
- Menno Tjeerd Spijker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE LOCKED LOOP USING ADAPTIVE FILTER TUNING FOR RADIATION HARDENING
- Publication number 20230403017
- Publication date Dec 14, 2023
- The Boeing Company
- Alfio Zanchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FAST FREQUENCY SYNTHESIZER SWITCHING
- Publication number 20230318609
- Publication date Oct 5, 2023
- Silicon Laboratories Inc.
- Rangakrishnan Srinivasan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE DETECTORS WITH EXTRAPOLATION OF TIMING EVENTS
- Publication number 20230308104
- Publication date Sep 28, 2023
- Analog Devices, Inc.
- Reuben P. Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ELECTRONIC APPARATUS AND METHOD FOR REDUCING COARSE LOCK TIME OF PH...
- Publication number 20230275588
- Publication date Aug 31, 2023
- Samsung Electronics Co., Ltd.
- Venkatasuryam Setty ISSA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE LOCK LOOP WITH AN ADAPTIVE LOOP FILTER
- Publication number 20230092886
- Publication date Mar 23, 2023
- Intel Corporation
- Kuan-Yueh Shen
- G08 - SIGNALLING
Information Patent Application
Reducing Noise Contribution in Compensating for Unequal Successive...
- Publication number 20230006682
- Publication date Jan 5, 2023
- Shaoxing Yuanfang Semiconductor Co., Ltd.
- Raja Prabhu J
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods and Circuits for Reducing Clock Jitter
- Publication number 20220329247
- Publication date Oct 13, 2022
- Rambus Inc.
- Marcus van Ierssel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE DETECTORS WITH ALIGNMENT TO PHASE INFORMATION LOST IN DECIMATION
- Publication number 20220173742
- Publication date Jun 2, 2022
- Analog Devices, Inc.
- Reuben P. Nelson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLING SYNCHRONOUS I/O INTERFACE
- Publication number 20220149850
- Publication date May 12, 2022
- u-blox AG.
- Aneeb Sohail
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELF-TUNING PHASE-LOCKED LOOP (PLL) CIRCUIT
- Publication number 20210344348
- Publication date Nov 4, 2021
- Analog Devices International Unlimited Company
- Wreeju BHAUMIK
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FIRST ORDER MEMORY-LESS DYNAMIC ELEMENT MATCHING TECHNIQUE
- Publication number 20210343319
- Publication date Nov 4, 2021
- STMicroelectronics International N.V.
- Ankur BAL
- G11 - INFORMATION STORAGE
Information Patent Application
FIRST ORDER MEMORY-LESS DYNAMIC ELEMENT MATCHING TECHNIQUE
- Publication number 20210110852
- Publication date Apr 15, 2021
- STMicroelectronics International N.V.
- Ankur BAL
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ADAPTIVE TIMING SYNCHRONIZATION FOR RECEPTION FOR BURSTY AND CONTIN...
- Publication number 20200274689
- Publication date Aug 27, 2020
- FRAUNHOFER-GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG e.V.
- Christian ROHDE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SPREAD SPECTRUM CLOCK GENERATION APPARATUS AND METHOD, AND DISPLAY...
- Publication number 20190173454
- Publication date Jun 6, 2019
- LG Display Co., Ltd.
- Jaehun JUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RADIO SIGNAL PROCESSING DEVICE, SEMICONDUCTOR DEVICE, AND OSCILLATI...
- Publication number 20180367152
- Publication date Dec 20, 2018
- RENESAS ELECTRONICS CORPORATION
- Kenichi SHIBATA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
BANDWIDTH ADJUSTMENT METHOD AND ASSOCIATED BANDWIDTH ADJUSTMENT CIR...
- Publication number 20180278260
- Publication date Sep 27, 2018
- Mstar Semiconductor, Inc.
- TING-NAN CHO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PHASE CONTROL OSCILLATOR
- Publication number 20180269883
- Publication date Sep 20, 2018
- NIHON DEMPA KOGYO CO., LTD.
- Ken MIYAHARA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SIMULTANEOUS CANCELLATION OF MULTIPLE SPURS FROM DIFFERENT SOURCES
- Publication number 20180241404
- Publication date Aug 23, 2018
- Avago Technologies General IP (Singapore) PTE. LTD.
- Long BU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DIGITAL SYNTHESIZER, COMMUNICATION UNIT AND METHOD THEREFOR
- Publication number 20180123537
- Publication date May 3, 2018
- NXP USA, Inc.
- Didier SALLE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ON-CHIP MEASUREMENT FOR PHASE-LOCKED LOOP
- Publication number 20180095119
- Publication date Apr 5, 2018
- ANALOG DEVICES GLOBAL
- Vamshi Krishna Chillara
- G01 - MEASURING TESTING
Information Patent Application
VIBRATION OPTIMIZING INTELLIGENT PHASE LOCKED LOOP
- Publication number 20170257105
- Publication date Sep 7, 2017
- Raytheon Company
- Michael R. Patrizi
- G01 - MEASURING TESTING
Information Patent Application
Oscillator Arrangement, Method, Computer Program And Communication...
- Publication number 20170026049
- Publication date Jan 26, 2017
- Telefonaktiebolaget LM Ericsson (publ)
- Lars Sundström
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHASE LOCKED LOOP CIRCUIT AND METHOD OF FREQUENCY ADJUSTMENT OF INJ...
- Publication number 20160336944
- Publication date Nov 17, 2016
- Mitsubishi Electric Corporation
- Takayuki NAKAI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK SYNCHRONIZER
- Publication number 20160294398
- Publication date Oct 6, 2016
- NXP B.V.
- Jos Verlinden
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Fast Settling Phase Locked Loop (PLL) with Optimum Spur Reduction
- Publication number 20150288371
- Publication date Oct 8, 2015
- Dialog Semiconductor B.V.
- Jan Prummel
- G06 - COMPUTING CALCULATING COUNTING

by changing characteristics of the loop filter

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Phase detectors with extrapolation of timing events

Clock jitter and spurious tone cancellation system using optical delay

Modified control loop in a digital phase-locked loop

Dual digital phase lock loop with unmodulation coupling

Fast frequency synthesizer switching

Synchronization between data and clock signals in high-speed interf...

Electronic apparatus and method for reducing coarse lock time of ph...

Methods and circuits for reducing clock jitter

Reducing noise contribution in compensating for unequal successive...

Phase detectors with alignment to phase information lost in decimation

Reduction of noise in output clock due to unequal successive time p...

Digital phase-locked loop

PLL circuit using intermittent operation amplifier

Controlling synchronous I/O interface

First order memory-less dynamic element matching technique

Phase-locked loop with phase noise cancellation

Self-tuning phase-locked loop (PLL) circuit

Fast locking sequence for phase-locked loops

First order memory-less dynamic element matching technique

Phase-locked loop with reduced frequency transients

Adaptive timing synchronization for reception for bursty and contin...

Adaptive timing synchronization for reception for bursty and contin...

Clock data recovery circuit and apparatus including the same

Spread spectrum clock generation apparatus and method, and display...

Circuit device, oscillator, electronic apparatus, and vehicle

Systems and methods for suppressing oscillator-induced spurs in fre...

Phase adjusting circuit, inverter circuit, and power supply system

Radio signal processing device, semiconductor device, and oscillati...

Optimum phase searching system and method thereof in ethernet physi...

Systems and methods of relocking for locked loops

Patents Applicationslast 30 patents

PLL CIRCUIT

PHASE-LOCKED LOOP (PLL) WITH AUTOMATIC LOOP BANDWIDTH CONTROL

CLOCK JITTER AND SPURIOUS TONE CANCELLATION SYSTEM USING OPTICAL DELAY

CLOCK AND DATA RECOVERY DEVICE

DUAL DIGITAL PHASE LOCK LOOP WITH UNMODULATION COUPLING

PHASE LOCKED LOOP USING ADAPTIVE FILTER TUNING FOR RADIATION HARDENING

FAST FREQUENCY SYNTHESIZER SWITCHING

PHASE DETECTORS WITH EXTRAPOLATION OF TIMING EVENTS

ELECTRONIC APPARATUS AND METHOD FOR REDUCING COARSE LOCK TIME OF PH...

PHASE LOCK LOOP WITH AN ADAPTIVE LOOP FILTER

Reducing Noise Contribution in Compensating for Unequal Successive...

Methods and Circuits for Reducing Clock Jitter

PHASE DETECTORS WITH ALIGNMENT TO PHASE INFORMATION LOST IN DECIMATION

CONTROLLING SYNCHRONOUS I/O INTERFACE

SELF-TUNING PHASE-LOCKED LOOP (PLL) CIRCUIT

FIRST ORDER MEMORY-LESS DYNAMIC ELEMENT MATCHING TECHNIQUE

FIRST ORDER MEMORY-LESS DYNAMIC ELEMENT MATCHING TECHNIQUE

ADAPTIVE TIMING SYNCHRONIZATION FOR RECEPTION FOR BURSTY AND CONTIN...

SPREAD SPECTRUM CLOCK GENERATION APPARATUS AND METHOD, AND DISPLAY...

RADIO SIGNAL PROCESSING DEVICE, SEMICONDUCTOR DEVICE, AND OSCILLATI...

BANDWIDTH ADJUSTMENT METHOD AND ASSOCIATED BANDWIDTH ADJUSTMENT CIR...

PHASE CONTROL OSCILLATOR

SIMULTANEOUS CANCELLATION OF MULTIPLE SPURS FROM DIFFERENT SOURCES

DIGITAL SYNTHESIZER, COMMUNICATION UNIT AND METHOD THEREFOR

ON-CHIP MEASUREMENT FOR PHASE-LOCKED LOOP

VIBRATION OPTIMIZING INTELLIGENT PHASE LOCKED LOOP

Oscillator Arrangement, Method, Computer Program And Communication...

PHASE LOCKED LOOP CIRCUIT AND METHOD OF FREQUENCY ADJUSTMENT OF INJ...

CLOCK SYNCHRONIZER

Fast Settling Phase Locked Loop (PLL) with Optimum Spur Reduction