Any and all applications for which a foreign or domestic priority claim is identified in the Application Data Sheet as filed with the present application are hereby incorporated by reference under 37 CFR 1.57.
This invention relates to generating clock signals for electronic devices and more particularly to generating clock signals using digital phase-locked loops.
A conventional digital phase-locked loop control system that includes a Proportional Integral (PI) controller has a lock time that is defined by the required loop bandwidth, quality of the input clock signal, peaking requirement, etc. The lock time of the conventional digital phase-locked loop is negligible for relatively high frequency input clock signals but becomes increasingly significant as the frequency of the input clock signal decreases. In applications that use an input clock signal having a relatively low frequency, such as a Global Positioning System (GPS) or distributed timing application that receives a Pulse Per Second (PPS) input clock signal (i.e., a 1 Hz input clock signal) or a Pulse Per Two Second (PP2S) input clock signal (i.e., an 0.5 Hz input clock signal), the conventional digital phase-locked loop takes a relatively long time (e.g., approximately an hour) to lock. The relatively long locking time can degrade further according to the quality of the input clock signal. However, a target application specification requires locking time to be less than one minute. The relatively long lock time for a low frequency input clock signal impacts performance in systems that relock the digital phase-locked loop when the input clock signal is lost and recovered or switched. Accordingly, improved digital phase-locked loop techniques are desired.
In at least one embodiment, a method for generating a clock signal using a digital phase-locked loop includes updating a gain of a variable gain digital filter of the digital phase-locked loop using an estimate error of a current estimate of a phase and a frequency of an input clock signal and a measurement error of a measurement of the phase and the frequency of the input clock signal. The gain may include a proportional gain component and an integral gain component. The method may include calculating the current estimate of the phase and the frequency of the input clock signal based on a previous estimate of the phase and the frequency of the input clock signal, the measurement of the phase and the frequency of the input clock signal, and the gain of the variable gain digital filter. The gain may be updated every cycle of the input clock signal.
In at least one embodiment, a digital phase-locked loop includes a time-to-digital converter configured to generate a digital signal based on an input clock signal. The digital phase-locked loop is configured to generate a phase-adjusted clock signal based on the digital signal. The digital phase-locked loop includes a variable gain digital filter configured to apply a time-varying gain to the digital signal. The digital phase-locked loop includes a variable gain generator configured to use the digital signal to update the time-varying gain based on an estimate error of a current estimate of a phase and a frequency of the input clock signal and a measurement error of a measurement of the phase and the frequency of the input clock signal. The variable gain digital filter may include a proportional signal path and an integral signal path and the time-varying gain may include a proportional gain component and an integral gain component.
In at least one embodiment, a method for generating a clock signal using a digital phase-locked loop includes filtering a state of a phase and a frequency of an input clock signal using a variable gain digital filter having a gain updated based on an estimate of the phase and the frequency of the input clock signal and a measurement of the phase and the frequency of the input clock signal. The gain may include a proportional gain component and an integral gain component. The gain may be updated every cycle of the input clock signal.
The present invention may be better understood, and its numerous objects, features, and advantages made apparent to those skilled in the art by referencing the accompanying drawings.
The use of the same reference symbols in different drawings indicates similar or identical items.
Digital phase-locked loop 105 is an outer digital phase-locked loop that includes time-to-digital converter 118, phase/frequency detector 120, digital loop filter 122, frequency divider 126 (e.g., a fractional divider), and uses digital phase-locked loop 104 as a digitally controlled oscillator for phase-locked loop 105. The digitally controlled oscillator is responsive to divider value MR, which may be a fractional divide value provided by digital loop filter 122. Phase/frequency detector 120 receives timestamps based on clock signal CLKIN1 and feedback timestamps provided by time-to-digital converter 124 based on a feedback clock signal generated by frequency divider 126. The feedback clock signal may be based on a frequency-divided version of clock signal CLKVCO. Digital phase/frequency detector 120 provides a digital phase error signal reflecting the difference between clock signal CLKIN1 and the digital feedback clock signal. The frequency of clock signal CLKVCO is determined by the frequency of clock signal CLKIN1 and the divider value MR provided by digital loop filter 122 and provided to feedback divider 114 (e.g., a fractional divider) in the feedback path of inner digital phase-locked loop 104. Digital phase-locked loop 105 adjusts divider value MR to match the frequency of clock signal CLKVCO to a multiple of the frequency of clock signal CLKIN1 implemented using frequency divider 126 and frequency divider 116 (e.g., frequency(CLKIN1)=frequency(CLKVCO)/MA NB). The frequency of CLKOUT1 provided by frequency divider 112 is based on the frequency of clock signal CLKVCO and divider value NA.
Digital phase-locked loop 107 receives a clock signal CLKIN2 and configures output interpolative divider 128 as a digitally controlled oscillator to generate clock signal CLKOUT2 using clock signal CLKVCO as a low-jitter reference clock signal. Time-to-digital converter 130 receives input clock signal CLKIN2, which has a low frequency, e.g., 1 PPS or 1 PP2S. Clock signal CLKOUT2 has a frequency determined by the frequency of clock signal CLKIN2 and the divider value MB provided to frequency divider 138. Time-to-digital converter 136 provides feedback timestamps to digital phase/frequency detector 132. Digital loop filter 134 provides a digital control signal to output interpolative divider 128 based on the digital phase error signal reflecting the difference between clock signal CLKIN2 and the feedback clock signal. The digital control signal causes output interpolative divider 128 to match the frequency of clock signal CLKOUT2 to a multiple of the frequency of clock signal CLKIN2.
In a signal path that is coupled in parallel with phase slope limiter 256, integrator gain 254 applies another gain factor (e.g., a power of two) to the gained phase difference signal received from forward gain 252. If the gained phase difference value is greater than a predetermined frequency slope limit, then frequency slope limiter 258 provides a predetermined frequency slope limit to accumulator 260. If the gained phase difference value is less than the predetermined frequency slope limit, then frequency slope limiter 258 provides the gained phase difference signal to accumulator 260. In closed-loop operation, accumulator 260 sums values of the gained phase difference signal over time to obtain a frequency shift value and provides the combination with the output of phase slope limiter 256 to infinite impulse response filter 262 in series with infinite impulse response filter 264, which low-pass filter the phase-change limited and frequency-change limited output signal to generate a corresponding digital control signal for output interpolative divider 128. The conventional control loop of
A technique for decreasing the lock or relock time of a digital phase-locked loop uses a modified control loop that has a variable control gain and thus, a variable locking time. The technique considers the quality of the input clock signal (e.g., uses a variance and covariance of a measurement of the input clock signal and process noise) to decrease the time to converge or lock to the target input clock signal. The technique maintains all the control loop characteristics like the acquiring and tracking modes of a conventional phase-locked loop. A dynamic model of a hardware-optimized structure includes a proportional-integral control loop having the same structure as a Kalman filter.
Referring to
where Z0k is the output of a phase detector or phase-frequency detector for the kth outputs of the corresponding time-to-digital converters, zi is the ith previous output of the phase detector for i=1 to P, Tk and Tk+1 are the previous and the current control loop updates at the kth and k+1th edges of the output of the phase-frequency detector. The technique implements a modified control loop using a linear unbiased estimator (e.g., gain generator 352 or gain generator 350 that generates the loop gain coefficients for variable gain digital filter 334 or variable gain digital filter 322, respectively). The linear unbiased estimator minimizes the least mean square error and is the optimal estimator if the noise sources are Gaussian noise sources. An iterative mathematical process uses a set of equations and consecutive data points and quickly converges an estimate to a true value (e.g., in the locked state) when the measured values contain unpredicted or random error/variation. The linear unbiased estimator uses relatively few samples to converge as compared to a conventional digital phase-locked loop by using variation of the input clock signal.
In general, gain generator 352 estimates a parameter (e.g., phase or frequency) to minimize uncertainty about that parameter after altering the belief about the parameter based on a prior belief Gain generator 352 measures the parameter and then combines phase and frequency errors and the variance of the phase and frequency to provide a new gain that minimizes the uncertainty. The technique is based on Gaussian probability density functions that are fully described by their variances and covariances (e.g., stored in covariance matrix Pk, described above). Terms along a main diagonal of covariance matrix Pk are the variances associated with the corresponding terms in the state vector. An appropriate mapping is used to move from one domain to another. Process noise and measurement noise are independent and thus, the covariance of the process noise and the measurement noise are ignored.
Referring to
The iterative process for gain generator 352 or gain generator 350 is further described as follows:
Gain generator 352 iteratively updates estimated (i.e., predicted) values Xkp and corrects measurements Zk to determine loop gain coefficients K:
If noise affecting frequency and phase is already captured by the covariance matrix and R vector observation noise, then
where
The variable loop gain K is a vector of weighting factors that are based on comparing the estimate error (i.e., the error in the estimate) to the measurement error (i.e., the error in the measurement). For example, if the measured value has relatively small error, then a weight applied to the measured value is greater than a weight applied to the estimated value and if the measured value has a relatively large error, then a weight applied to the estimated value is greater than a weight applied to the measured value. The gain and the prediction covariance matrix will reach a steady state value in some amount of time. In an embodiment, the proportional path is predominately relevant to phase and the integral path is predominately relevant to frequency. Based on the optimized or simplified (i.e., ignoring constant gains) the variable loop gain is as follows:
where K[1,1] applies to the proportional path and K[2,2] applies to the integral path.
This technique has two primary sources of error: initialization error and stochastic errors due to the process and measurement noise. In early stages of operation, initialization error dominates, and it takes some time for the estimated state to converge to the true state from an incorrect initial state. After initial error convergence, measurement noise remains, resulting in persistent errors. Stability analysis can be used to generate an initial error and noise disturbance. Below are few assumptions to analyze the convergence rate of the control loop. If the following assumptions hold, then:
The techniques described above can be used in tracking systems, artificial intelligence-related applications and systems requiring synchronization. The control loops described above can be used as an alternative to conventional PI controller control loop systems.
In at least one embodiment, the digital phase-locked loop implementing variable gain digital filter techniques described above is included in a network communication box that uses timing protocols to ensure time of day (ToD) counters in the network are synchronized. SYNC signals are used to update time of day counters at the same time in the network. Any delay/offset and process, voltage, temperature (PVT) variation between the SYNC lines being supplied to the ToD counters in each line card in the network box results in an error that is classified as Continuous Time Error (CTE). Network communications are used to communicate various status and information regarding the system.
The exact position of the SYNC edge is derived using a precision time protocol (PTP) servo loop that uses time information inside the incoming Synchronous Ethernet (SyncE) packet stream to slave line card 1101 on input DATA_IN 1116 of physical interface 1123. The timestamps exchange allows determination of one-way delay (OWD) and error offset between the upstream PHY and the downstream PHY. That time stamp exchange allows the slave line card to determine the correct time provided by the upstream PHY even with delays between the upstream PHY and the downstream PHY. Note that the high-level description of the PTP servo loop is provided as background information to provide context in which various embodiments of the digital phase-locked loop described herein can be utilized.
Slave line card 1101 and master timing card 1103 also have a closed loop PTP servo system in accordance with the IEEE 1588 protocol that corrects the position of the SYNC signal over process, voltage, and temperature (PVT) and aligns the SYNC signals distributed by the master timing card 1103 to the timing of the incoming packet stream to the slave line card. The servo loop ensures that the slave line card and the master timing card are synchronized. The slave line card 1101 and the master timing card 1103 exchange information in the closed loop system to adjust the CLK and SYNC pair on the master timing card such that the slave line card ToD is aligned with the network ToD of the chosen incoming data stream on DATA_IN 1116. The PTP servo loop adjusts the timing of SYNC by adjusting DPLL 1117 so that the slave line card ToD is aligned in frequency and phase to the upstream ToD received by the slave line card on input DATA_IN 1116. The distributed system clock signal SYSCLK is distributed and supplied as a reference clock to DPLL 1121 within each of the line cards and the line card digital phase-locked loops generate a local system clock signal SYSCLK and SYNC signal that is phase and frequency aligned with the distributed system clock signal SYSCLK and SYNC signal. The master line cards 1105 are duplicates (up to 64 copies) of the slave line card 1101 but without the closed loop PTP servo loop. In other words, the distribution of the CLK/SYNC pair to the master line cards 1105 is open loop (i.e., without the PTP closed loop adjustments). The timing card and various line cards communicate, at least in part, utilizing a serial communication bus (not shown in
Structures described herein may be implemented using software executing on a processor (which includes firmware) or by a combination of software and hardware. Software, as described herein, may be encoded in at least one tangible (i.e., non-transitory) computer readable medium. As referred to herein, a tangible computer-readable medium includes at least a disk, tape, or other magnetic, optical, or electronic storage medium.
Thus, techniques for reducing the lock time or relock time of a digital phase-locked loop are described. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the following claims. The terms “first,” “second,” “third,” and so forth, as used in the claims, unless otherwise clear by context, is to distinguish between different items in the claims and does not otherwise indicate or imply any order in time, location or quality. For example, “a first signal,” and “a second signal,” does not indicate or imply that the first signal occurs in time before the second signal. Variations and modifications of the embodiments disclosed herein may be made based on the description set forth herein, without departing from the scope of the invention as set forth in the following claims.
Number | Name | Date | Kind |
---|---|---|---|
6147561 | Rhee et al. | Nov 2000 | A |
6630868 | Perrott et al. | Oct 2003 | B2 |
6707342 | Zachan et al. | Mar 2004 | B1 |
6717475 | McCarthy | Apr 2004 | B2 |
6765445 | Perrott et al. | Jul 2004 | B2 |
6785346 | Birkett et al. | Aug 2004 | B1 |
6792282 | Domino et al. | Sep 2004 | B1 |
6801784 | Rozenblit et al. | Oct 2004 | B1 |
6867655 | McCarthy | Mar 2005 | B2 |
6920622 | Garlepp et al. | Jul 2005 | B1 |
6927637 | Koh et al. | Aug 2005 | B1 |
6961547 | Rozenblit et al. | Nov 2005 | B2 |
7064617 | Hein et al. | Jun 2006 | B2 |
7068110 | Frey et al. | Jun 2006 | B2 |
7079598 | Birkett et al. | Jul 2006 | B2 |
7091759 | Sowiati et al. | Aug 2006 | B2 |
7099636 | Rozenblit et al. | Aug 2006 | B2 |
7138839 | Zachan et al. | Nov 2006 | B2 |
7148753 | Garlepp et al. | Dec 2006 | B1 |
7187241 | Hein et al. | Mar 2007 | B2 |
7218951 | Rozenblit et al. | May 2007 | B2 |
7256629 | Zachan et al. | Aug 2007 | B2 |
7288998 | Thomsen et al. | Oct 2007 | B2 |
7295077 | Thomsen et al. | Nov 2007 | B2 |
7355463 | Sowiati et al. | Apr 2008 | B2 |
7375591 | Fu et al. | May 2008 | B2 |
7405628 | Hulfachor et al. | Jul 2008 | B2 |
7436227 | Thomsen et al. | Oct 2008 | B2 |
7443250 | Seethamraju et al. | Oct 2008 | B2 |
7576614 | Zachan et al. | Aug 2009 | B2 |
7612617 | Pullela et al. | Nov 2009 | B2 |
7613267 | Perrott et al. | Nov 2009 | B2 |
7706496 | Youssoufian | Apr 2010 | B2 |
7747237 | All et al. | Jun 2010 | B2 |
7825708 | Thomsen et al. | Nov 2010 | B2 |
7834706 | Frey et al. | Nov 2010 | B2 |
7869780 | Youssoufian et al. | Jan 2011 | B2 |
8135365 | Youssoufian et al. | Mar 2012 | B2 |
8154351 | Tadjpour | Apr 2012 | B2 |
8193867 | Fu et al. | Jun 2012 | B2 |
8456206 | Namdar-Mehdiabadi et al. | Jun 2013 | B2 |
8532243 | Seethamraju et al. | Sep 2013 | B2 |
8554156 | Tadjpour | Oct 2013 | B2 |
8791734 | Hara et al. | Jul 2014 | B1 |
8989332 | Katumba et al. | Mar 2015 | B2 |
8994420 | Eldredge et al. | Mar 2015 | B2 |
9036762 | Green | May 2015 | B2 |
9042854 | Wang et al. | May 2015 | B2 |
9054716 | Obkircher et al. | Jun 2015 | B2 |
9065457 | Namdar-Mehdiabadi et al. | Jun 2015 | B2 |
9236851 | Youssoufian et al. | Jan 2016 | B2 |
9246500 | Perrott | Jan 2016 | B2 |
9270288 | Perrott | Feb 2016 | B2 |
9350367 | All et al. | May 2016 | B2 |
9362925 | Namdar-Mehdiabadi et al. | Jun 2016 | B2 |
9461653 | Perrott | Oct 2016 | B2 |
9490818 | Perrott | Nov 2016 | B2 |
9490827 | Wang et al. | Nov 2016 | B2 |
9531392 | Katumba et al. | Dec 2016 | B2 |
9705521 | Monk et al. | Jul 2017 | B1 |
9762250 | Perroti | Sep 2017 | B2 |
9768790 | Namdar-mehdiabadi | Sep 2017 | B2 |
10075173 | Sarda | Sep 2018 | B2 |
10263626 | Wang et al. | Apr 2019 | B2 |
10608649 | Jayakumar et al. | Mar 2020 | B1 |
10651862 | Barette et al. | May 2020 | B1 |
10727844 | Gong et al. | Jul 2020 | B1 |
10819353 | Monk et al. | Oct 2020 | B1 |
10819354 | Jayakumar et al. | Oct 2020 | B2 |
10826507 | Gong et al. | Nov 2020 | B1 |
10833682 | Monk et al. | Nov 2020 | B1 |
10908635 | Ranganathan et al. | Feb 2021 | B1 |
11018679 | Jayakumar | May 2021 | B1 |
11088819 | Sarda | Aug 2021 | B1 |
11095295 | Monk et al. | Aug 2021 | B2 |
11228403 | Ranganathan et al. | Jan 2022 | B2 |
11283459 | Monk et al. | Mar 2022 | B1 |
11502764 | Sarda | Nov 2022 | B2 |
11563441 | Monk et al. | Jan 2023 | B2 |
11671238 | Sarda | Jun 2023 | B2 |
20070036253 | Seo | Feb 2007 | A1 |
20070132518 | Wang | Jun 2007 | A1 |
20070146083 | Hein et al. | Jun 2007 | A1 |
20140035641 | Lamanna | Feb 2014 | A1 |
20140062549 | Navid | Mar 2014 | A1 |
20220077863 | Monk et al. | Mar 2022 | A1 |
20220123877 | Ranganathan et al. | Apr 2022 | A1 |
20230094645 | Jayakumar | Mar 2023 | A1 |
20230188237 | Sarda | Jun 2023 | A1 |
20230198531 | Jayakumar | Jun 2023 | A1 |
20230231567 | Monk et al. | Jul 2023 | A1 |
20240056084 | Lee | Feb 2024 | A1 |
Number | Date | Country | |
---|---|---|---|
20230198531 A1 | Jun 2023 | US |
Number | Date | Country | |
---|---|---|---|
63292515 | Dec 2021 | US |