by using two redundant chains

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H03K19/0075

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Parent Industries

HELECTRICITY H03Electronic circuits H03KPULSE TECHNIQUE H03K19/00Logic circuits

Current Industry

H03K19/0075by using two redundant chains

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Buffer circuit, semiconductor integrated circuit device, oscillator...
- Patent number RE50208
- Issue date Nov 12, 2024
- Seiko Epson Corporation
- Kenji Hayashi
Information Patent Grant
Multi-bit scan chain with error-bit generator
- Patent number 12,068,745
- Issue date Aug 20, 2024
- ARM Limited
- Anil Kumar Baratam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device
- Patent number 11,949,413
- Issue date Apr 2, 2024
- NUVOTON TECHNOLOGY CORPORATION JAPAN
- Kazuyuki Nakanishi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Systems and methods for mitigating faults in combinatory logic
- Patent number 10,901,836
- Issue date Jan 26, 2021
- University of Southern California
- Michel Sika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fail redundancy circuits
- Patent number 10,778,226
- Issue date Sep 15, 2020
- SK hynix Inc.
- Geun Ho Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Radiation event protection circuit with double redundancy and latch
- Patent number 10,715,143
- Issue date Jul 14, 2020
- STMicroelectronics S.R.L.
- Agatino Antonino Alessandro
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Power distributor, and on-board electrical system having at least o...
- Patent number 10,676,052
- Issue date Jun 9, 2020
- Leoni-Bordnetz Systeme GmbH
- Sebastian Doernbach
- B60 - VEHICLES IN GENERAL
Information Patent Grant
Buffer circuit, semiconductor integrated circuit device, oscillator...
- Patent number 10,476,493
- Issue date Nov 12, 2019
- Seiko Epson Corporation
- Kenji Hayashi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Safety switching device for fail-safely disconnecting an electrical...
- Patent number 10,460,895
- Issue date Oct 29, 2019
- Pilz GmbH & Co. KG
- Jürgen Pullmann
- G05 - CONTROLLING REGULATING
Information Patent Grant
Reconfigurable circuit, storage device, and electronic device inclu...
- Patent number 10,418,995
- Issue date Sep 17, 2019
- Semiconductor Energy Laboratory Co., Ltd.
- Yoshiyuki Kurokawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuitry for implementing multi-mode redundancy and arithmetic fun...
- Patent number 9,813,061
- Issue date Nov 7, 2017
- Altera Corporation
- Herman Henry Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Industrial control system with integrated circuit elements partitio...
- Patent number 9,651,931
- Issue date May 16, 2017
- Rockwell Automation Technologies, Inc.
- Edward C. Hopsecger
- G05 - CONTROLLING REGULATING
Information Patent Grant
Reconfigurable circuit, storage device, and electronic device inclu...
- Patent number 9,515,656
- Issue date Dec 6, 2016
- Semiconductor Energy Laboratory Co., Ltd.
- Yoshiyuki Kurokawa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Radiation hardened digital circuit
- Patent number 9,467,144
- Issue date Oct 11, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Redundant electric circuit for cutting off the power supply to a pi...
- Patent number 9,459,640
- Issue date Oct 4, 2016
- Sagem Defense Securite
- Jean-Marie Courteille
- G05 - CONTROLLING REGULATING
Information Patent Grant
Circuitry for implementing multi-mode redundancy and arithmetic fun...
- Patent number 9,362,913
- Issue date Jun 7, 2016
- Altera Corporation
- Herman Henry Schmit
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable circuit device and configuration information restorati...
- Patent number 9,337,838
- Issue date May 10, 2016
- Hitachi, Ltd.
- Makoto Saen
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and circuit structure for suppressing single event transient...
- Patent number 8,975,913
- Issue date Mar 10, 2015
- Nelson Mandela Metropolitan University
- Farouk Smith
- G01 - MEASURING TESTING
Information Patent Grant
Electronic circuit arrangement for processing binary input values
- Patent number 8,884,643
- Issue date Nov 11, 2014
- Infineon Technologies AG
- Michael Augustin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device having a latch circuit
- Patent number 8,330,494
- Issue date Dec 11, 2012
- Fujitsu Semiconductor Limited
- Taiki Uemura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Protection circuit
- Patent number 8,259,425
- Issue date Sep 4, 2012
- Giga-Byte Technology Co., Ltd.
- Hui-Mou Wu
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Soft error and transient error detection device and methods therefor
- Patent number 8,255,748
- Issue date Aug 28, 2012
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- G01 - MEASURING TESTING
Information Patent Grant
Self restoring logic
- Patent number 8,081,010
- Issue date Dec 20, 2011
- ICS, LLC
- Sterling R. Whitaker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and circuitry for reconfigurable SEU/SET tolerance
- Patent number 7,859,292
- Issue date Dec 28, 2010
- United States of America as represented by the Administrator of the National...
- Robert L. Shuler, Jr.
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Single event upset mitigation
- Patent number 7,852,107
- Issue date Dec 14, 2010
- Xilinx, Inc.
- Prasanna Sundararajan
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit architecture for radiation resilience
- Patent number 7,804,354
- Issue date Sep 28, 2010
- Honeywell International Inc.
- David O. Erstad
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual redundant dynamic logic
- Patent number 7,679,403
- Issue date Mar 16, 2010
- Honeywell International Inc.
- David O. Erstad
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit and method of production of same
- Patent number 7,646,209
- Issue date Jan 12, 2010
- Sony Corporation
- Mitsuhiro Oomori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with redundancy
- Patent number 7,589,552
- Issue date Sep 15, 2009
- Altera Corporation
- Mario E. Guzman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Duplicated double checking production rule set for fault-tolerant e...
- Patent number 7,301,362
- Issue date Nov 27, 2007
- California Institute of Technology
- Wonjin Jang
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
Multi-Bit Scan Chain with Error-Bit Generator
- Publication number 20230063727
- Publication date Mar 2, 2023
- ARM Limited
- Anil Kumar Baratam
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20220209773
- Publication date Jun 30, 2022
- NUVOTON TECHNOLOGY CORPORATION JAPAN
- Kazuyuki NAKANISHI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20220200595
- Publication date Jun 23, 2022
- NUVOTON TECHNOLOGY CORPORATION JAPAN
- Kazuyuki NAKANISHI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FAIL REDUNDANCY CIRCUITS
- Publication number 20200287544
- Publication date Sep 10, 2020
- SK HYNIX INC.
- Geun Ho CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
Power Distributor, and On-Board Electrical System Having at Least O...
- Publication number 20200062200
- Publication date Feb 27, 2020
- LEONI BORDNETZ-SYSTEME GMBH
- Sebastian Doernbach
- B60 - VEHICLES IN GENERAL
Information Patent Application
SYSTEMS AND METHODS FOR MITIGATING FAULTS IN COMBINATORY LOGIC
- Publication number 20190220347
- Publication date Jul 18, 2019
- University of Southern California
- Michel Sika
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND CIRCUIT STRUCTURE FOR SUPPRESSING SINGLE EVENT TRANSIENT...
- Publication number 20190020341
- Publication date Jan 17, 2019
- NELSON MANDELA UNIVERSITY
- Farouk Smith
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
RADIATION HARDENED DIGITAL CIRCUIT
- Publication number 20160028397
- Publication date Jan 28, 2016
- Arizona Board of Regents on behalf of Arizona State University
- Lawrence T. Clark
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PROGRAMMABLE CIRCUIT DEVICE AND CONFIGURATION INFORMATION RESTORATI...
- Publication number 20150236696
- Publication date Aug 20, 2015
- Hitachi, Ltd.
- MAKOTO SAEN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND CIRCUIT STRUCTURE FOR SUPPRESSING SINGLE EVENT TRANSIENT...
- Publication number 20140247068
- Publication date Sep 4, 2014
- NELSON MANDELA METROPOLITAN UNIVERSITY
- Farouk Smith
- G01 - MEASURING TESTING
Information Patent Application
Electronic Circuit Arrangement for Processing Binary Input Values
- Publication number 20130002288
- Publication date Jan 3, 2013
- INFINEON TECHNOLOGIES AG
- Michael Augustin
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20110309861
- Publication date Dec 22, 2011
- FUJITSU SEMICONDUCTOR LIMITED
- Taiki Uemura
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Protection Circuit
- Publication number 20110058294
- Publication date Mar 10, 2011
- Hui-Mou WU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND CIRCUITRY FOR RECONFIGURABLE SEU/SET TOLERANCE
- Publication number 20110012638
- Publication date Jan 20, 2011
- Robert L. Shuler, JR.
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SOFT ERROR AND TRANSIENT ERROR DETECTION DEVICE AND METHODS THEREFOR
- Publication number 20100244918
- Publication date Sep 30, 2010
- FREESCALE SEMICONDUCTOR, INC.
- William C. Moyer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Self-protected solid-state electrical switching device
- Publication number 20090109590
- Publication date Apr 30, 2009
- CROUZET AUTOMATISMES
- Dominique Girot
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Circuit Architecture for Radiation Resilience
- Publication number 20090108912
- Publication date Apr 30, 2009
- Honeywell International Inc.
- David O. Erstad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor integrated circuit and method of production of same
- Publication number 20070234137
- Publication date Oct 4, 2007
- SONY CORPORATION
- Mutsuhiro Oomori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Dual redundant dynamic logic
- Publication number 20070103194
- Publication date May 10, 2007
- Honeywell International Inc.
- David O. Erstad
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Redundancy circuits hardened against single event upsets
- Publication number 20070052442
- Publication date Mar 8, 2007
- Honeywell International Inc.
- David E. Fulkerson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Duplicated double checking production rule set for fault-tolerant e...
- Publication number 20070016823
- Publication date Jan 18, 2007
- California Institute of Technology
- Wonjin Jang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Apparatus and method for automotive bus switching protection
- Publication number 20050184752
- Publication date Aug 25, 2005
- Alexandre Pierre Palus
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Protection circuit against voltage or current spikes, and clock cir...
- Publication number 20040252571
- Publication date Dec 16, 2004
- STMicroelectronics S.A.
- Jean-Francois Hugues
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Protection circuit against voltage or current spikes, and clock cir...
- Publication number 20030214772
- Publication date Nov 20, 2003
- STMicroelectronics S.A.
- Jean-Francois Hugues
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Electronic safety switching device and method
- Publication number 20030178961
- Publication date Sep 25, 2003
- Roland Rupp
- G05 - CONTROLLING REGULATING
Information Patent Application
Safety switching device and system of safety switching devices
- Publication number 20030011250
- Publication date Jan 16, 2003
- Jurgen Pullmann
- F16 - ENGINEERING ELEMENTS AND UNITS GENERAL MEASURES FOR PRODUCING AND MAINT...
Information Patent Application
Logic architecture for single event upset immunity
- Publication number 20020175713
- Publication date Nov 28, 2002
- BAE SYSTEMS Information and Electronic Systems Integration, Inc
- Kenneth R. Knowles
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Logic architecture for single event upset immunity
- Publication number 20020017924
- Publication date Feb 14, 2002
- Kenneth R. Knowles
- H03 - BASIC ELECTRONIC CIRCUITRY

by using two redundant chains

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Buffer circuit, semiconductor integrated circuit device, oscillator...

Multi-bit scan chain with error-bit generator

Semiconductor device

Systems and methods for mitigating faults in combinatory logic

Fail redundancy circuits

Radiation event protection circuit with double redundancy and latch

Power distributor, and on-board electrical system having at least o...

Buffer circuit, semiconductor integrated circuit device, oscillator...

Safety switching device for fail-safely disconnecting an electrical...

Reconfigurable circuit, storage device, and electronic device inclu...

Circuitry for implementing multi-mode redundancy and arithmetic fun...

Industrial control system with integrated circuit elements partitio...

Reconfigurable circuit, storage device, and electronic device inclu...

Radiation hardened digital circuit

Redundant electric circuit for cutting off the power supply to a pi...

Circuitry for implementing multi-mode redundancy and arithmetic fun...

Programmable circuit device and configuration information restorati...

Method and circuit structure for suppressing single event transient...

Electronic circuit arrangement for processing binary input values

Semiconductor device having a latch circuit

Protection circuit

Soft error and transient error detection device and methods therefor

Self restoring logic

Methods and circuitry for reconfigurable SEU/SET tolerance

Single event upset mitigation

Circuit architecture for radiation resilience

Dual redundant dynamic logic

Semiconductor integrated circuit and method of production of same

Integrated circuit with redundancy

Duplicated double checking production rule set for fault-tolerant e...

Patents Applicationslast 30 patents

Multi-Bit Scan Chain with Error-Bit Generator

SEMICONDUCTOR DEVICE

SEMICONDUCTOR DEVICE

FAIL REDUNDANCY CIRCUITS

Power Distributor, and On-Board Electrical System Having at Least O...

SYSTEMS AND METHODS FOR MITIGATING FAULTS IN COMBINATORY LOGIC

METHOD AND CIRCUIT STRUCTURE FOR SUPPRESSING SINGLE EVENT TRANSIENT...

RADIATION HARDENED DIGITAL CIRCUIT

PROGRAMMABLE CIRCUIT DEVICE AND CONFIGURATION INFORMATION RESTORATI...

METHOD AND CIRCUIT STRUCTURE FOR SUPPRESSING SINGLE EVENT TRANSIENT...

Electronic Circuit Arrangement for Processing Binary Input Values

SEMICONDUCTOR DEVICE

Protection Circuit

METHODS AND CIRCUITRY FOR RECONFIGURABLE SEU/SET TOLERANCE

SOFT ERROR AND TRANSIENT ERROR DETECTION DEVICE AND METHODS THEREFOR

Self-protected solid-state electrical switching device

Circuit Architecture for Radiation Resilience

Semiconductor integrated circuit and method of production of same

Dual redundant dynamic logic

Redundancy circuits hardened against single event upsets

Duplicated double checking production rule set for fault-tolerant e...

Apparatus and method for automotive bus switching protection

Protection circuit against voltage or current spikes, and clock cir...

Protection circuit against voltage or current spikes, and clock cir...

Electronic safety switching device and method

Safety switching device and system of safety switching devices

Logic architecture for single event upset immunity

Logic architecture for single event upset immunity