Logic circuits

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  • CPC
  • H03K19/00
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H03K19/0002Multistate logic H03K19/0005Modifications of input or output impedance H03K19/0008Arrangements for reducing power consumption H03K19/001in bipolar transistor circuits H03K19/0013in field effect transistor circuits H03K19/0016by using a control or a clock signal H03K19/0019by energy recovery or adiabatic operation H03K19/0021Modifications of threshold H03K19/0024in bipolar transistor circuits H03K19/0027in field effect transistor circuits H03K19/003Modifications for increasing the reliability for protection H03K19/00307in bipolar transistor circuits H03K19/00315in field-effect transistor circuits H03K19/00323Delay compensation H03K19/0033Radiation hardening H03K19/00338In field effect transistor circuits H03K19/00346Modifications for eliminating interference or parasitic voltages or currents H03K19/00353in bipolar transistor circuits H03K19/00361in field effect transistor circuits H03K19/00369Modifications for compensating variations of temperature, supply voltage or other physical parameters H03K19/00376in bipolar transistor circuits H03K19/00384in field effect transistor circuits H03K19/00392by circuit redundancy H03K19/007Fail-safe circuits H03K19/0075by using two redundant chains H03K19/01Modifications for accelerating switching H03K19/013in bipolar transistor circuits H03K19/0133by bootstrapping H03K19/0136by means of a pull-up or down element H03K19/017in field-effect transistor circuits H03K19/01707in asynchronous circuits H03K19/01714by bootstrapping H03K19/01721by means of a pull-up or down element H03K19/01728in synchronous circuits H03K19/01735by bootstrapping H03K19/01742by means of a pull-up or down element H03K19/0175Coupling arrangements Interface arrangements H03K19/017509Interface arrangements H03K19/017518using a combination of bipolar and field effect transistors [BIFET] H03K19/017527with at least one differential stage H03K19/017536using opto-electronic devices H03K19/017545Coupling arrangements; Impedance matching circuits H03K19/017554using a combination of bipolar and field effect transistors [BIFET] H03K19/017563with at least one differential stage H03K19/017572using opto-electronic devices H03K19/017581programmable H03K19/01759with a bidirectional operation H03K19/018using bipolar transistors only H03K19/01806Interface arrangements H03K19/01812with at least one differential stage H03K19/01818for integrated injection logic (I2L) H03K19/01825Coupling arrangements, impedance matching circuits H03K19/01831with at least one differential stage H03K19/01837programmable H03K19/01843with a bidirectional operation H03K19/0185using field effect transistors only H03K19/018507Interface arrangements H03K19/018514with at least one differential stage H03K19/018521of complementary type H03K19/018528with at least one differential stage H03K19/018535of Schottky barrier type [MESFET] H03K19/018542with at least one differential stage H03K19/01855synchronous H03K19/018557Coupling arrangements; Impedance matching circuits H03K19/018564with at least one differential stage H03K19/018571of complementary type H03K19/018578with at least one differential stage H03K19/018585programmable H03K19/018592with a bidirectional operation H03K19/02using specified components H03K19/04using gas-filled tubes H03K19/06using vacuum tubes H03K19/08using semiconductor devices H03K19/0806using charge transfer devices (DTC, CCD) H03K19/0813Threshold logic H03K19/082using bipolar transistors H03K19/0823Multistate logic H03K19/0826one of the states being the high impedance or floating state H03K19/084Diode-transistor logic H03K19/0843Complementary transistor logic [CTL] H03K19/0846Schottky transistor logic [STL] H03K19/086Emitter coupled logic H03K19/0863Emitter function logic [EFL]; Base coupled logic [BCL] H03K19/0866Stacked emitter coupled logic H03K19/088Transistor-transistor logic H03K19/09Resistor-transistor logic H03K19/091Integrated injection logic or merged transistor logic H03K19/0912Static induction logic [STIL] H03K19/0915Integrated schottky logic [ISL] H03K19/0917Multistate logic H03K19/094using field-effect transistors H03K19/09403using junction field-effect transistors H03K19/09407of the same canal type H03K19/0941of complementary type H03K19/09414with gate injection or static induction [STIL] H03K19/09418in combination with bipolar transistors [BIFET] H03K19/09421Diode field-effect transistor logic H03K19/09425Multistate logic H03K19/09429one of the states being the high impedance or floating state H03K19/09432with coupled sources or source coupled logic H03K19/09436Source coupled field-effect logic [SCFL] H03K19/0944using MOSFET or insulated gate field-effect transistors H03K19/09441of the same canal type H03K19/09443using a combination of enhancement and depletion transistors H03K19/09445with active depletion transistors H03K19/09446using only depletion transistors H03K19/09448in combination with bipolar transistors [BIMOS] H03K19/0948using CMOS or complementary insulated gate field-effect transistors H03K19/09482using a combination of enhancement and depletion transistors H03K19/09485with active depletion transistors H03K19/09487using only depletion transistors H03K19/0952using Schottky type FET MESFET H03K19/0956Schottky diode FET logic H03K19/096Synchronous circuits H03K19/0963using transistors of complementary type H03K19/0966Self-timed logic H03K19/098using thyristors H03K19/10using tunnel diodes H03K19/12using diode rectifiers H03K19/14using opto-electronic devices H03K19/16using saturable magnetic devices H03K19/162using parametrons H03K19/164using ferro-resonant devices H03K19/166using transfluxors H03K19/168using thin-film devices H03K19/17using twistors H03K19/173using elementary logic circuits as components H03K19/1731Optimisation thereof H03K19/1732by limitation or reduction of the pin/gate ratio H03K19/1733Controllable logic circuits H03K19/1735by wiring H03K19/1736in which the wiring can be modified H03K19/1737using multiplexers H03K19/1738using cascode switch logic [CSL] or cascode emitter coupled logic [CECL] H03K19/177arranged in matrix form H03K19/17704the logic functions being realised by the interconnection of rows and columns H03K19/17708using an AND matrix followed by an OR matrix H03K19/17712one of the matrices at least being reprogrammable H03K19/17716with synchronous operation, i.e. using clock signals H03K19/1772with synchronous operation of at least one of the logical matrixes H03K19/17724Structural details of logic blocks H03K19/17728Reconfigurable logic blocks H03K19/17732Macro blocks H03K19/17736Structural details of routing resources H03K19/1774for global signals H03K19/17744for input/output signals H03K19/17748Structural details of configuration resources H03K19/17752for hot reconfiguration H03K19/17756for partial configuration or reconfiguration H03K19/1776for memories H03K19/17764for reliability H03K19/17768for security H03K19/17772for powering on or off H03K19/17776for speeding up configuration or reconfiguration H03K19/1778Structural details for adapting physical parameters H03K19/17784for supply voltage H03K19/17788for I/O voltages H03K19/17792for operating speed H03K19/17796for physical disposition of blocks H03K19/18using galvano-magnetic devices H03K19/185using dielectric elements with variable dielectric constant H03K19/19using ferro-resonant devices H03K19/195using superconductive devices H03K19/1952with electro-magnetic coupling of the control current H03K19/1954with injection of the control current H03K19/1956using an inductorless circuit H03K19/1958Hybrid configuration H03K19/20characterised by logic function H03K19/21EXCLUSIVE-OR circuits H03K19/212using bipolar transistors H03K19/215using field-effect transistors H03K19/217using Schottky type FET [MESFET] H03K19/23Majority or minority circuits