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H03K19/00
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Parent Industries
H
ELECTRICITY
H03
Electronic circuits
H03K
PULSE TECHNIQUE
Current Industry
H03K19/00
Logic circuits
Sub Industries
H03K19/0002
Multistate logic
H03K19/0005
Modifications of input or output impedance
H03K19/0008
Arrangements for reducing power consumption
H03K19/001
in bipolar transistor circuits
H03K19/0013
in field effect transistor circuits
H03K19/0016
by using a control or a clock signal
H03K19/0019
by energy recovery or adiabatic operation
H03K19/0021
Modifications of threshold
H03K19/0024
in bipolar transistor circuits
H03K19/0027
in field effect transistor circuits
H03K19/003
Modifications for increasing the reliability for protection
H03K19/00307
in bipolar transistor circuits
H03K19/00315
in field-effect transistor circuits
H03K19/00323
Delay compensation
H03K19/0033
Radiation hardening
H03K19/00338
In field effect transistor circuits
H03K19/00346
Modifications for eliminating interference or parasitic voltages or currents
H03K19/00353
in bipolar transistor circuits
H03K19/00361
in field effect transistor circuits
H03K19/00369
Modifications for compensating variations of temperature, supply voltage or other physical parameters
H03K19/00376
in bipolar transistor circuits
H03K19/00384
in field effect transistor circuits
H03K19/00392
by circuit redundancy
H03K19/007
Fail-safe circuits
H03K19/0075
by using two redundant chains
H03K19/01
Modifications for accelerating switching
H03K19/013
in bipolar transistor circuits
H03K19/0133
by bootstrapping
H03K19/0136
by means of a pull-up or down element
H03K19/017
in field-effect transistor circuits
H03K19/01707
in asynchronous circuits
H03K19/01714
by bootstrapping
H03K19/01721
by means of a pull-up or down element
H03K19/01728
in synchronous circuits
H03K19/01735
by bootstrapping
H03K19/01742
by means of a pull-up or down element
H03K19/0175
Coupling arrangements Interface arrangements
H03K19/017509
Interface arrangements
H03K19/017518
using a combination of bipolar and field effect transistors [BIFET]
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with at least one differential stage
H03K19/017536
using opto-electronic devices
H03K19/017545
Coupling arrangements; Impedance matching circuits
H03K19/017554
using a combination of bipolar and field effect transistors [BIFET]
H03K19/017563
with at least one differential stage
H03K19/017572
using opto-electronic devices
H03K19/017581
programmable
H03K19/01759
with a bidirectional operation
H03K19/018
using bipolar transistors only
H03K19/01806
Interface arrangements
H03K19/01812
with at least one differential stage
H03K19/01818
for integrated injection logic (I2L)
H03K19/01825
Coupling arrangements, impedance matching circuits
H03K19/01831
with at least one differential stage
H03K19/01837
programmable
H03K19/01843
with a bidirectional operation
H03K19/0185
using field effect transistors only
H03K19/018507
Interface arrangements
H03K19/018514
with at least one differential stage
H03K19/018521
of complementary type
H03K19/018528
with at least one differential stage
H03K19/018535
of Schottky barrier type [MESFET]
H03K19/018542
with at least one differential stage
H03K19/01855
synchronous
H03K19/018557
Coupling arrangements; Impedance matching circuits
H03K19/018564
with at least one differential stage
H03K19/018571
of complementary type
H03K19/018578
with at least one differential stage
H03K19/018585
programmable
H03K19/018592
with a bidirectional operation
H03K19/02
using specified components
H03K19/04
using gas-filled tubes
H03K19/06
using vacuum tubes
H03K19/08
using semiconductor devices
H03K19/0806
using charge transfer devices (DTC, CCD)
H03K19/0813
Threshold logic
H03K19/082
using bipolar transistors
H03K19/0823
Multistate logic
H03K19/0826
one of the states being the high impedance or floating state
H03K19/084
Diode-transistor logic
H03K19/0843
Complementary transistor logic [CTL]
H03K19/0846
Schottky transistor logic [STL]
H03K19/086
Emitter coupled logic
H03K19/0863
Emitter function logic [EFL]; Base coupled logic [BCL]
H03K19/0866
Stacked emitter coupled logic
H03K19/088
Transistor-transistor logic
H03K19/09
Resistor-transistor logic
H03K19/091
Integrated injection logic or merged transistor logic
H03K19/0912
Static induction logic [STIL]
H03K19/0915
Integrated schottky logic [ISL]
H03K19/0917
Multistate logic
H03K19/094
using field-effect transistors
H03K19/09403
using junction field-effect transistors
H03K19/09407
of the same canal type
H03K19/0941
of complementary type
H03K19/09414
with gate injection or static induction [STIL]
H03K19/09418
in combination with bipolar transistors [BIFET]
H03K19/09421
Diode field-effect transistor logic
H03K19/09425
Multistate logic
H03K19/09429
one of the states being the high impedance or floating state
H03K19/09432
with coupled sources or source coupled logic
H03K19/09436
Source coupled field-effect logic [SCFL]
H03K19/0944
using MOSFET or insulated gate field-effect transistors
H03K19/09441
of the same canal type
H03K19/09443
using a combination of enhancement and depletion transistors
H03K19/09445
with active depletion transistors
H03K19/09446
using only depletion transistors
H03K19/09448
in combination with bipolar transistors [BIMOS]
H03K19/0948
using CMOS or complementary insulated gate field-effect transistors
H03K19/09482
using a combination of enhancement and depletion transistors
H03K19/09485
with active depletion transistors
H03K19/09487
using only depletion transistors
H03K19/0952
using Schottky type FET MESFET
H03K19/0956
Schottky diode FET logic
H03K19/096
Synchronous circuits
H03K19/0963
using transistors of complementary type
H03K19/0966
Self-timed logic
H03K19/098
using thyristors
H03K19/10
using tunnel diodes
H03K19/12
using diode rectifiers
H03K19/14
using opto-electronic devices
H03K19/16
using saturable magnetic devices
H03K19/162
using parametrons
H03K19/164
using ferro-resonant devices
H03K19/166
using transfluxors
H03K19/168
using thin-film devices
H03K19/17
using twistors
H03K19/173
using elementary logic circuits as components
H03K19/1731
Optimisation thereof
H03K19/1732
by limitation or reduction of the pin/gate ratio
H03K19/1733
Controllable logic circuits
H03K19/1735
by wiring
H03K19/1736
in which the wiring can be modified
H03K19/1737
using multiplexers
H03K19/1738
using cascode switch logic [CSL] or cascode emitter coupled logic [CECL]
H03K19/177
arranged in matrix form
H03K19/17704
the logic functions being realised by the interconnection of rows and columns
H03K19/17708
using an AND matrix followed by an OR matrix
H03K19/17712
one of the matrices at least being reprogrammable
H03K19/17716
with synchronous operation, i.e. using clock signals
H03K19/1772
with synchronous operation of at least one of the logical matrixes
H03K19/17724
Structural details of logic blocks
H03K19/17728
Reconfigurable logic blocks
H03K19/17732
Macro blocks
H03K19/17736
Structural details of routing resources
H03K19/1774
for global signals
H03K19/17744
for input/output signals
H03K19/17748
Structural details of configuration resources
H03K19/17752
for hot reconfiguration
H03K19/17756
for partial configuration or reconfiguration
H03K19/1776
for memories
H03K19/17764
for reliability
H03K19/17768
for security
H03K19/17772
for powering on or off
H03K19/17776
for speeding up configuration or reconfiguration
H03K19/1778
Structural details for adapting physical parameters
H03K19/17784
for supply voltage
H03K19/17788
for I/O voltages
H03K19/17792
for operating speed
H03K19/17796
for physical disposition of blocks
H03K19/18
using galvano-magnetic devices
H03K19/185
using dielectric elements with variable dielectric constant
H03K19/19
using ferro-resonant devices
H03K19/195
using superconductive devices
H03K19/1952
with electro-magnetic coupling of the control current
H03K19/1954
with injection of the control current
H03K19/1956
using an inductorless circuit
H03K19/1958
Hybrid configuration
H03K19/20
characterised by logic function
H03K19/21
EXCLUSIVE-OR circuits
H03K19/212
using bipolar transistors
H03K19/215
using field-effect transistors
H03K19/217
using Schottky type FET [MESFET]
H03K19/23
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