Cache consistency protocols

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G06F12/0815

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0815Cache consistency protocols

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Patents Grantslast 30 patents

Information Patent Grant
Reconfigurable cache architecture and methods for cache coherency
- Patent number 12,360,902
- Issue date Jul 15, 2025
- Next Silicon Ltd
- Elad Raz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory performance during program suspend protocol
- Patent number 12,360,901
- Issue date Jul 15, 2025
- Micron Technology, Inc.
- Sundararajan N. Sankaranarayanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 12,360,843
- Issue date Jul 15, 2025
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Credit aware central arbitration for multi-endpoint, multi-core system
- Patent number 12,360,844
- Issue date Jul 15, 2025
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast synchronization mechanism for heterogeneous computing
- Patent number 12,360,904
- Issue date Jul 15, 2025
- Mediatek Inc.
- Hsing-Chuang Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Executing memory requests out of order
- Patent number 12,353,883
- Issue date Jul 8, 2025
- Imagination Technologies Limited
- Mark Landers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-performance computing system
- Patent number 12,346,254
- Issue date Jul 1, 2025
- SIPEARL
- Romain Dolbeau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Controlling operating voltage of a processor
- Patent number 12,339,723
- Issue date Jun 24, 2025
- Daedalus Prime LLC
- Ryan D. Wells
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable cache coherency protocol
- Patent number 12,332,792
- Issue date Jun 17, 2025
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coherency management using distributed snoop
- Patent number 12,332,791
- Issue date Jun 17, 2025
- Akeana, Inc.
- Sanjay Patel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Unforwardable load instruction re-execution eligibility based on ca...
- Patent number 12,332,793
- Issue date Jun 17, 2025
- Ventana Micro Systems Inc.
- John G. Favor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Speculative request indicator in request message
- Patent number 12,332,799
- Issue date Jun 17, 2025
- SiFive, Inc.
- Wesley Waylon Terpstra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fault tolerant systems and methods using shared memory configurations
- Patent number 12,326,811
- Issue date Jun 10, 2025
- STRATUS TECHNOLOGIES IRELAND LTD.
- Andrew Alden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Heterogeneous architecture, delivered by cxl based cached switch SO...
- Patent number 12,326,813
- Issue date Jun 10, 2025
- Avago Technologies International Sales Pte. Limited
- Shreyas Shah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate atomic operations in victim cache
- Patent number 12,321,284
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo out-of-order store commit
- Patent number 12,321,272
- Issue date Jun 3, 2025
- Advanced Micro Devices, Inc.
- John M. King
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence for memory controller
- Patent number 12,321,270
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,321,285
- Issue date Jun 3, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Updating related data in multi-cache systems
- Patent number 12,314,182
- Issue date May 27, 2025
- ARM Limited
- Olof Henrik Uhrenholt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data storage device with memory services for storage access queues
- Patent number 12,314,181
- Issue date May 27, 2025
- Micron Technology, Inc.
- Luca Bert
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Recording a cache coherency protocol trace for use with a separate...
- Patent number 12,306,757
- Issue date May 20, 2025
- Microsoft Technology Licensing, LLC
- Jordi Mola
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache synchronization for chiplet accelerators
- Patent number 12,292,836
- Issue date May 6, 2025
- Preyesh Dalmia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information processing apparatus and control method
- Patent number 12,292,837
- Issue date May 6, 2025
- Fujitsu Limited
- Yuji Shirahige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for migrating CPU state from an inoperable core to a spare core
- Patent number 12,277,041
- Issue date Apr 15, 2025
- Oracle International Corporation
- James Lewis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache size change
- Patent number 12,271,314
- Issue date Apr 8, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bypassing cache directory lookups for processing-in-memory instruct...
- Patent number 12,265,470
- Issue date Apr 1, 2025
- Advanced Micro Devices, Inc.
- Travis Henry Boraten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for managing data bias in a graphics processin...
- Patent number 12,260,470
- Issue date Mar 25, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
USING DIRECTORY DELEGATION FOR CLIENT SIDE CACHE OPERATIONS
- Publication number 20250231879
- Publication date Jul 17, 2025
- DELL PRODUCTS, L.P.
- G. Paul Koning
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE SIZE CHANGE
- Publication number 20250231878
- Publication date Jul 17, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VIRTUAL NETWORK PRE-ARBITRATION
- Publication number 20250231684
- Publication date Jul 17, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20250225083
- Publication date Jul 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH PERFORMANCE INTERCONNECT
- Publication number 20250225090
- Publication date Jul 10, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH MULTI DIMENSIONAL CIRCULAR ADDRESSING SELECTA...
- Publication number 20250217301
- Publication date Jul 3, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive System Probe Action to Minimize Input/Output Dirty Data Tr...
- Publication number 20250217292
- Publication date Jul 3, 2025
- ADVANCED MICRO DEVICES, INC.
- Li Ou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGEMENT OF MULTIPLE CACHE LINE INVALIDATIONS
- Publication number 20250209002
- Publication date Jun 26, 2025
- Kalray
- Vincent RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRAINING NODES OF A NEURAL NETWORK TO BE DECISIVE
- Publication number 20250209333
- Publication date Jun 26, 2025
- D5AI LLC
- James K. Baker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH
- Publication number 20250190368
- Publication date Jun 12, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER
- Publication number 20250181238
- Publication date Jun 5, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Matthew David PIERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEPARATING HASHING FROM PROOF-OF-WORK IN BLOCKCHAIN ENVIRONMENTS
- Publication number 20250184117
- Publication date Jun 5, 2025
- Inveniam Capital Partners, Inc.
- Paul Snow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR STORAGE VIRTUALIZATION
- Publication number 20250173266
- Publication date May 29, 2025
- Dynavisor, Inc.
- Sreekumar Nair
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VECTOR PROCESSOR STORAGE
- Publication number 20250156335
- Publication date May 15, 2025
- Daedalus Cloud LLC
- Xavier Aldren SIMMONS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE COHERENCE SIGNALING PROTOCOL
- Publication number 20250147888
- Publication date May 8, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERSISTENT STORAGE DEVICE MANAGEMENT
- Publication number 20250139014
- Publication date May 1, 2025
- Daedalus Cloud LLC
- Stuart John INGLIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE WRITE FILTER HARDWARE
- Publication number 20250123955
- Publication date Apr 17, 2025
- Intel Corporation
- Frank T. Hady
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESS REMAPPING OF DISCARDED SURFACES
- Publication number 20250117330
- Publication date Apr 10, 2025
- ADVANCED MICRO DEVICES, INC.
- Dana Schaa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING SPARSE COMPUTATION MECHANISM
- Publication number 20250117873
- Publication date Apr 10, 2025
- Intel Corporation
- Eriko Nurvitadhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Bypassing Cache Directory Lookups for Processing-in-Memory Instruct...
- Publication number 20250110878
- Publication date Apr 3, 2025
- ADVANCED MICRO DEVICES, INC.
- Travis Henry Boraten
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Controller Reservation of Resources for Cache Hit
- Publication number 20250103477
- Publication date Mar 27, 2025
- Apple Inc.
- Ilya Granovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT SWAP CACHING WITH ZERO LINE OPTIMIZATIONS
- Publication number 20250103339
- Publication date Mar 27, 2025
- Microsoft Technology Licensing, LLC
- Ishwar AGARWAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ZERO LATENCY PREFETCHING IN CACHES
- Publication number 20250103503
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Oluleye Olorode
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POWER SAVING MODE CONTROL FOR A MEMORY INSTANCE
- Publication number 20250103129
- Publication date Mar 27, 2025
- ARM Limited
- Andy Wangkun Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY STORAGE FOR MULTI-CHANNEL MEMORY SYSTEM
- Publication number 20250094061
- Publication date Mar 20, 2025
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20250094044
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Cache consistency protocols

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Reconfigurable cache architecture and methods for cache coherency

Memory performance during program suspend protocol

Multicore shared cache operation engine

Credit aware central arbitration for multi-endpoint, multi-core system

Fast synchronization mechanism for heterogeneous computing

Executing memory requests out of order

High-performance computing system

Controlling operating voltage of a processor

Scalable cache coherency protocol

Coherency management using distributed snoop

Unforwardable load instruction re-execution eligibility based on ca...

Speculative request indicator in request message

Fault tolerant systems and methods using shared memory configurations

Heterogeneous architecture, delivered by cxl based cached switch SO...

Methods and apparatus to facilitate atomic operations in victim cache

Pseudo out-of-order store commit

Hardware coherence for memory controller

Victim cache with write miss merging

Updating related data in multi-cache systems

Data storage device with memory services for storage access queues

Recording a cache coherency protocol trace for use with a separate...

Cache synchronization for chiplet accelerators

Write merging on stores with different privilege levels

Information processing apparatus and control method

Method for migrating CPU state from an inoperable core to a spare core

Cache size change

Bypassing cache directory lookups for processing-in-memory instruct...

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for multi-banked victim cache with dual datapath

Apparatus and method for managing data bias in a graphics processin...

Patents Applicationslast 30 patents

USING DIRECTORY DELEGATION FOR CLIENT SIDE CACHE OPERATIONS

CACHE SIZE CHANGE

VIRTUAL NETWORK PRE-ARBITRATION

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION

HIGH PERFORMANCE INTERCONNECT

STREAMING ENGINE WITH MULTI DIMENSIONAL CIRCULAR ADDRESSING SELECTA...

Adaptive System Probe Action to Minimize Input/Output Dirty Data Tr...

MANAGEMENT OF MULTIPLE CACHE LINE INVALIDATIONS

TRAINING NODES OF A NEURAL NETWORK TO BE DECISIVE

METHODS AND APPARATUS FOR MULTI-BANKED VICTIM CACHE WITH DUAL DATAPATH

MULTICORE, MULTIBANK, FULLY CONCURRENT COHERENCE CONTROLLER

SEPARATING HASHING FROM PROOF-OF-WORK IN BLOCKCHAIN ENVIRONMENTS

METHOD AND SYSTEM FOR STORAGE VIRTUALIZATION

VECTOR PROCESSOR STORAGE

HARDWARE COHERENCE SIGNALING PROTOCOL

PERSISTENT STORAGE DEVICE MANAGEMENT

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

PROGRAMMABLE WRITE FILTER HARDWARE

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

ADDRESS REMAPPING OF DISCARDED SURFACES

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

MACHINE LEARNING SPARSE COMPUTATION MECHANISM

Bypassing Cache Directory Lookups for Processing-in-Memory Instruct...

Memory Controller Reservation of Resources for Cache Hit

DIRECT SWAP CACHING WITH ZERO LINE OPTIMIZATIONS

ZERO LATENCY PREFETCHING IN CACHES

POWER SAVING MODE CONTROL FOR A MEMORY INSTANCE

NON-VOLATILE MEMORY STORAGE FOR MULTI-CHANNEL MEMORY SYSTEM

MULTICORE SHARED CACHE OPERATION ENGINE

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT