Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification

Industry

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G11C16/345

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C16/00Erasable programmable read-only memories

Current Industry

G11C16/345Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Memory device performing program operation and method of operating...
- Patent number 12,362,024
- Issue date Jul 15, 2025
- SK HYNIX INC.
- Dong Hun Kwak
- G11 - INFORMATION STORAGE
Information Patent Grant
Mixed bitline lockout for QLC/TLC die
- Patent number 12,362,012
- Issue date Jul 15, 2025
- SanDisk Technologies, Inc.
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with loop dependant ramp-up rate
- Patent number 12,354,664
- Issue date Jul 8, 2025
- SanDisk Technologies, Inc.
- Abu Naser Zainuddin
- G11 - INFORMATION STORAGE
Information Patent Grant
Channel pre-charge process in a memory device
- Patent number 12,354,681
- Issue date Jul 8, 2025
- SanDisk Technologies, Inc.
- Jiacen Guo
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device and programming method capable of programming...
- Patent number 12,354,667
- Issue date Jul 8, 2025
- Winbond Electronics Corp.
- Masaru Yano
- G11 - INFORMATION STORAGE
Information Patent Grant
High performance verify techniques in a memory device
- Patent number 12,354,680
- Issue date Jul 8, 2025
- SanDisk Technologies, Inc.
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with erase depth detection and adaptive adjustm...
- Patent number 12,354,683
- Issue date Jul 8, 2025
- SanDisk Technologies, Inc.
- Huiwen Xu
- G11 - INFORMATION STORAGE
Information Patent Grant
Intermediate re-verify for achieving tighter threshold voltage dist...
- Patent number 12,354,682
- Issue date Jul 8, 2025
- SanDisk Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with efficient testing
- Patent number 12,354,678
- Issue date Jul 8, 2025
- SanDisk Technologies, Inc.
- Jayavel Pachamuthu
- G11 - INFORMATION STORAGE
Information Patent Grant
Establishing bitline, wordline and boost voltages to manage a maxim...
- Patent number 12,347,485
- Issue date Jul 1, 2025
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of programming multi-plane memory device
- Patent number 12,347,501
- Issue date Jul 1, 2025
- Yangtze Memory Technologies Co., Ltd.
- Jialiang Deng
- G11 - INFORMATION STORAGE
Information Patent Grant
Page buffer, memory device including page buffer and memory system...
- Patent number 12,347,502
- Issue date Jul 1, 2025
- SK hynix Inc.
- Kang Woo Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device
- Patent number 12,347,495
- Issue date Jul 1, 2025
- SK hynix Inc.
- Hyun Seob Shin
- G11 - INFORMATION STORAGE
Information Patent Grant
Source bias temperature compensation for read and program verify op...
- Patent number 12,340,850
- Issue date Jun 24, 2025
- Micron Technology, Inc.
- Ronit Roneel Prakash
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for detecting fail cell and operation method thereof
- Patent number 12,340,849
- Issue date Jun 24, 2025
- Samsung Electronics Co., Ltd.
- Jooyong Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, memory system, and method for multi-pass programming...
- Patent number 12,340,852
- Issue date Jun 24, 2025
- Yangtze Memory Technologies Co., Ltd.
- Zhipeng Dong
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device performing program operation and operating met...
- Patent number 12,340,853
- Issue date Jun 24, 2025
- SK hynix Inc.
- Hyung Jin Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memories for performing successive programming operations
- Patent number 12,340,851
- Issue date Jun 24, 2025
- Micron Technology, Inc.
- Umberto Siciliani
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital Verify Failbit Count (VFC) circuit
- Patent number 12,334,162
- Issue date Jun 17, 2025
- Yangtze Memory Technologies Co., Ltd.
- Teng Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Simultaneous programming of multiple sub-blocks in NAND memory stru...
- Patent number 12,334,152
- Issue date Jun 17, 2025
- SK Hynix NAND Product Solutions Corp.
- Ali Khakifirooz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and method of operating the same
- Patent number 12,334,161
- Issue date Jun 17, 2025
- SK hynix Inc.
- Jong Hoon Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Single-level cell program-verify, latch-limited data recovery
- Patent number 12,334,163
- Issue date Jun 17, 2025
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of operating the memory device
- Patent number 12,334,156
- Issue date Jun 17, 2025
- SK hynix Inc.
- Jae Hyeon Shin
- G11 - INFORMATION STORAGE
Information Patent Grant
Shortened single-level cell memory programming
- Patent number 12,327,595
- Issue date Jun 10, 2025
- Micron Technology, Inc.
- Leo Raimondo
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory devices, operating methods thereof and memory sy...
- Patent number 12,322,457
- Issue date Jun 3, 2025
- Samsung Electronics Co., Ltd.
- Sun-Il Shim
- G11 - INFORMATION STORAGE
Information Patent Grant
Program verify process having placement aware pre-program verify (P...
- Patent number 12,322,455
- Issue date Jun 3, 2025
- INTEL NDTM US LLC
- Shantanu R. Rajwade
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of operating the same
- Patent number 12,322,458
- Issue date Jun 3, 2025
- SK hynix Inc.
- June Young Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, programming method of memory device, and memory system
- Patent number 12,322,449
- Issue date Jun 3, 2025
- Yangtze Memory Technologies Co., Ltd.
- Jing Wei
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital verify failbit count (VFC) circuit
- Patent number 12,322,456
- Issue date Jun 3, 2025
- Yangtze Memory Technologies Co., Ltd.
- Teng Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and program operation thereof to reduce capacitive co...
- Patent number 12,315,577
- Issue date May 27, 2025
- Yangtze Memory Technologies Co., Ltd.
- Yu Wang
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
NON-VOLATILE MEMORY DEVICE, STORAGE DEVICE, AND OPERATION METHOD TH...
- Publication number 20250232815
- Publication date Jul 17, 2025
- Samsung Electronics Co., Ltd.
- Hyungseok YU
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY DEVICE REDUCING A NUMBER OF PROGRAM BIT LINES AN...
- Publication number 20250232813
- Publication date Jul 17, 2025
- Samsung Electronics Co., Ltd.
- Sangwon Kim
- G11 - INFORMATION STORAGE
Information Patent Application
HIDDEN MAJORITY VOTE PROGRAM VERIFY SCHEME FOR A MEMORY DEVICE
- Publication number 20250232823
- Publication date Jul 17, 2025
- Micro Technology, Inc.
- Yu-Chung LIEN
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
- Publication number 20250226034
- Publication date Jul 10, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
NAND DATA PLACEMENT SCHEMA
- Publication number 20250226041
- Publication date Jul 10, 2025
- Micron Technology, Inc.
- Carminantonio Manganelli
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND OPERATION METHOD THEREOF
- Publication number 20250226032
- Publication date Jul 10, 2025
- Samsung Electronics Co., Ltd.
- Sang-Won Park
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20250226031
- Publication date Jul 10, 2025
- KIOXIA Corporation
- Yosuke MURAKAMI
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS...
- Publication number 20250226040
- Publication date Jul 10, 2025
- Micron Technology, Inc.
- Robert W. Mason
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY WITH ENHANCED EARLY PROGRAM TERMINATION MODE FO...
- Publication number 20250226044
- Publication date Jul 10, 2025
- Western Digital Technologies, Inc.
- Xuan Tian
- G11 - INFORMATION STORAGE
Information Patent Application
3D NAND FLASH AND OPERATION METHOD THEREOF
- Publication number 20250226033
- Publication date Jul 10, 2025
- Yangtze Memory Technologies Co., Ltd.
- Hongtao Liu
- G11 - INFORMATION STORAGE
Information Patent Application
COMPACT SENSE AMPLIFIER DATA LATCH DESIGN WITH VERY LOW VOLTAGE TRA...
- Publication number 20250226038
- Publication date Jul 10, 2025
- Western Digital Technologies, Inc.
- Anirudh Amarnath
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTIVE SLOW PROGRAMMING CONVERGENCE PROGRAM OPERATION WITH PROGR...
- Publication number 20250226039
- Publication date Jul 10, 2025
- Micron Technology, Inc.
- Yu-Chung Lien
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METH...
- Publication number 20250218516
- Publication date Jul 3, 2025
- Samsung Electronics Co., Ltd.
- Heechan Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND PROGRAM OPERATION THEREOF
- Publication number 20250218520
- Publication date Jul 3, 2025
- Yangtze Memory Technologies Co., Ltd.
- Ying Huang
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20250210112
- Publication date Jun 26, 2025
- KIOXIA Corporation
- Koji HOSONO
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC BIT LINE VOLTAGE DURING PROGRAM VERIFY TO PROVIDE MORE THRE...
- Publication number 20250210118
- Publication date Jun 26, 2025
- Western Digital Technologies, Inc.
- Ming Wang
- G11 - INFORMATION STORAGE
Information Patent Application
SMART REDUCED-VERIFY ALGORITHM FOR NON-VOLATILE MEMORY APPARATUSES
- Publication number 20250210105
- Publication date Jun 26, 2025
- Western Digital Technologies, Inc.
- Chengqing Hu
- G11 - INFORMATION STORAGE
Information Patent Application
BITSCAN TECHNIQUES IN A MEMORY DEVICE
- Publication number 20250210117
- Publication date Jun 26, 2025
- Western Digital Technologies, Inc.
- Yuki Fujita
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE
- Publication number 20250201318
- Publication date Jun 19, 2025
- SK HYNIX INC.
- Hyun Seob SHIN
- G11 - INFORMATION STORAGE
Information Patent Application
OPERATING METHOD OF MEMORY DEVICE
- Publication number 20250201319
- Publication date Jun 19, 2025
- SK HYNIX INC.
- Jung Shik JANG
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY DEVICES WITH MULTIPLE OPERATION MODES
- Publication number 20250201320
- Publication date Jun 19, 2025
- Samsung Electronics Co., Ltd.
- Taeyun Lee
- G11 - INFORMATION STORAGE
Information Patent Application
PAGE BUFFER RELATED TO PERFORMING A PROGRAM OPERATION, MEMORY DEVIC...
- Publication number 20250191658
- Publication date Jun 12, 2025
- SK HYNIX INC.
- Chang Hyun HAN
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
- Publication number 20250191665
- Publication date Jun 12, 2025
- SK HYNIX INC.
- Hee Youl LEE
- G11 - INFORMATION STORAGE
Information Patent Application
SOURCE SIDE SELECT GATE ELECTRICAL ISOLATION IN NAND MEMORY USING I...
- Publication number 20250194091
- Publication date Jun 12, 2025
- SANDISK TECHNOLOGIES, INC.
- Kazuki Isozumi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTROL METHOD AND CONTROLLER OF 3D NAND FLASH
- Publication number 20250191655
- Publication date Jun 12, 2025
- Yangtze Memory Technologies Co., Ltd.
- Ying Huang
- G11 - INFORMATION STORAGE
Information Patent Application
LEVEL SHIFTING IN ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A ME...
- Publication number 20250191659
- Publication date Jun 12, 2025
- Micron Technology, Inc.
- Sheyang Ning
- G11 - INFORMATION STORAGE
Information Patent Application
OPERATION METHOD OF MEMORY, MEMORY, AND MEMORY SYSTEM
- Publication number 20250191664
- Publication date Jun 12, 2025
- Yangtze Memory Technologies Co., Ltd.
- Xiangnan ZHAO
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH FAST WRITE MODE TO MITIGATE POWER LOSS
- Publication number 20250182827
- Publication date Jun 5, 2025
- Micron Technology, Inc.
- Yu-Chung LIEN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND PROGRAM OPERATION THEREOF
- Publication number 20250182833
- Publication date Jun 5, 2025
- Yangtze Memory Technologies Co., Ltd.
- Weijun WAN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORIES, OPERATION METHODS OF MEMORIES, AND MEMORY SYSTEMS
- Publication number 20250174287
- Publication date May 29, 2025
- Yangtze Memory Technologies Co., Ltd.
- Yang ZHANG
- G06 - COMPUTING CALCULATING COUNTING

Circuits or methods to detect overerased nonvolatile memory cells, usually during erasure verification

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory device performing program operation and method of operating...

Mixed bitline lockout for QLC/TLC die

Non-volatile memory with loop dependant ramp-up rate

Channel pre-charge process in a memory device

Semiconductor device and programming method capable of programming...

High performance verify techniques in a memory device

Non-volatile memory with erase depth detection and adaptive adjustm...

Intermediate re-verify for achieving tighter threshold voltage dist...

Non-volatile memory with efficient testing

Establishing bitline, wordline and boost voltages to manage a maxim...

Method of programming multi-plane memory device

Page buffer, memory device including page buffer and memory system...

Memory device

Source bias temperature compensation for read and program verify op...

Memory device for detecting fail cell and operation method thereof

Memory device, memory system, and method for multi-pass programming...

Semiconductor device performing program operation and operating met...

Memories for performing successive programming operations

Digital Verify Failbit Count (VFC) circuit

Simultaneous programming of multiple sub-blocks in NAND memory stru...

Memory device and method of operating the same

Single-level cell program-verify, latch-limited data recovery

Memory device and method of operating the memory device

Shortened single-level cell memory programming

Nonvolatile memory devices, operating methods thereof and memory sy...

Program verify process having placement aware pre-program verify (P...

Memory device and method of operating the same

Memory device, programming method of memory device, and memory system

Digital verify failbit count (VFC) circuit

Memory device and program operation thereof to reduce capacitive co...

Patents Applicationslast 30 patents

NON-VOLATILE MEMORY DEVICE, STORAGE DEVICE, AND OPERATION METHOD TH...

NONVOLATILE MEMORY DEVICE REDUCING A NUMBER OF PROGRAM BIT LINES AN...

HIDDEN MAJORITY VOTE PROGRAM VERIFY SCHEME FOR A MEMORY DEVICE

PROGRAMMING MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING

NAND DATA PLACEMENT SCHEMA

MEMORY DEVICE AND OPERATION METHOD THEREOF

SEMICONDUCTOR MEMORY DEVICE

MANAGING DEFECTIVE BLOCKS DURING MULTI-PLANE PROGRAMMING OPERATIONS...

NON-VOLATILE MEMORY WITH ENHANCED EARLY PROGRAM TERMINATION MODE FO...

3D NAND FLASH AND OPERATION METHOD THEREOF

COMPACT SENSE AMPLIFIER DATA LATCH DESIGN WITH VERY LOW VOLTAGE TRA...

SELECTIVE SLOW PROGRAMMING CONVERGENCE PROGRAM OPERATION WITH PROGR...

MEMORY DEVICE, MEMORY SYSTEM INCLUDING THE SAME, AND OPERATING METH...

MEMORY DEVICE AND PROGRAM OPERATION THEREOF

SEMICONDUCTOR MEMORY DEVICE

DYNAMIC BIT LINE VOLTAGE DURING PROGRAM VERIFY TO PROVIDE MORE THRE...

SMART REDUCED-VERIFY ALGORITHM FOR NON-VOLATILE MEMORY APPARATUSES

BITSCAN TECHNIQUES IN A MEMORY DEVICE

SEMICONDUCTOR DEVICE AND OPERATING METHOD OF SEMICONDUCTOR DEVICE

OPERATING METHOD OF MEMORY DEVICE

NONVOLATILE MEMORY DEVICES WITH MULTIPLE OPERATION MODES

PAGE BUFFER RELATED TO PERFORMING A PROGRAM OPERATION, MEMORY DEVIC...

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

SOURCE SIDE SELECT GATE ELECTRICAL ISOLATION IN NAND MEMORY USING I...

CONTROL METHOD AND CONTROLLER OF 3D NAND FLASH

LEVEL SHIFTING IN ALL LEVELS PROGRAMMING OF A MEMORY DEVICE IN A ME...

OPERATION METHOD OF MEMORY, MEMORY, AND MEMORY SYSTEM

MEMORY DEVICE WITH FAST WRITE MODE TO MITIGATE POWER LOSS

MEMORY DEVICE AND PROGRAM OPERATION THEREOF

MEMORIES, OPERATION METHODS OF MEMORIES, AND MEMORY SYSTEMS