comprising cells containing a single floating gate transistor and one or more separate select transistors

Industry

CPC
G11C16/0433

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C16/00Erasable programmable read-only memories

Current Industry

G11C16/0433comprising cells containing a single floating gate transistor and one or more separate select transistors

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Memory circuits and devices, and methods thereof
- Patent number 12,183,397
- Issue date Dec 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, operating method thereof, system, and storage medium
- Patent number 12,176,033
- Issue date Dec 24, 2024
- Yangtze Memory Technologies Co., Ltd.
- Zhipeng Dong
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of operating the memory device
- Patent number 12,176,041
- Issue date Dec 24, 2024
- SK hynix Inc.
- Hye Lyoung Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Operating a chalcogenide memory with vertical word and vertical wor...
- Patent number 12,176,042
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Computing-in-memory architecture
- Patent number 12,176,063
- Issue date Dec 24, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yi-Chun Shih
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line dependent pass voltage ramp rate to improve performance o...
- Patent number 12,176,032
- Issue date Dec 24, 2024
- SANDISK TECHNOLOGIES LLC
- Abu Naser Zainuddin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Setting levels for a programming operation in a neural network array
- Patent number 12,176,039
- Issue date Dec 24, 2024
- Silicon Storage Technology, Inc.
- Hieu Van Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device and method of operating the same
- Patent number 12,165,718
- Issue date Dec 10, 2024
- SK hynix Inc.
- Hyun Seob Shin
- G11 - INFORMATION STORAGE
Information Patent Grant
Static random access memory apparatus that maintains stable write p...
- Patent number 12,165,719
- Issue date Dec 10, 2024
- Kwangwoon University Industry-Academic Collaboration Foundation
- Hanwool Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 12,160,999
- Issue date Dec 3, 2024
- Semiconductor Energy Laboratory Co., Ltd.
- Kiyoshi Kato
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-time programmable non-volatile memory cell and memory with lo...
- Patent number 12,154,629
- Issue date Nov 26, 2024
- CHENGDU ANALOG CIRCUIT TECHNOLOGY INC.
- Dan Ning
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of operating the same
- Patent number 12,142,320
- Issue date Nov 12, 2024
- SK hynix Inc.
- Jong Kyung Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device including active regions for reducing d...
- Patent number 12,137,557
- Issue date Nov 5, 2024
- SK hynix Inc.
- Sung Kun Park
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory device readable only a predetermined number of...
- Patent number 12,125,533
- Issue date Oct 22, 2024
- STMicroelectronics (Rousset) SAS
- Francesco La Rosa
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory architecture for serial EEPROMs
- Patent number 12,125,532
- Issue date Oct 22, 2024
- STMicroelectronics (Rousset) SAS
- Laurent Murillo
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, the operation method thereof and memory system
- Patent number 12,112,802
- Issue date Oct 8, 2024
- Yangtze Memory Technologies Co., Ltd.
- Zhihong Li
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device storing logical page data and operating method of the...
- Patent number 12,106,806
- Issue date Oct 1, 2024
- SK hynix Inc.
- Jung Shik Jang
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory device
- Patent number 12,100,452
- Issue date Sep 24, 2024
- Samsung Electronics Co., Ltd.
- Kuihan Ko
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 12,099,920
- Issue date Sep 24, 2024
- Renesas Electronics Corporation
- Junichi Suzuki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resistive memory device including reference cell to compensate for...
- Patent number RE50133
- Issue date Sep 17, 2024
- Samsung Electronics Co., Ltd.
- Artur Antonyan
Information Patent Grant
Using non-segregated cells as drain-side select gates for sub-block...
- Patent number 12,080,351
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Aaron S. Yip
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory device
- Patent number 12,073,888
- Issue date Aug 27, 2024
- Samsung Electronics Co., Ltd.
- Youn-Yeol Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and method of operating the memory device including d...
- Patent number 12,068,033
- Issue date Aug 20, 2024
- SK hynix Inc.
- Jae Woong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device and operating method thereof
- Patent number 12,068,045
- Issue date Aug 20, 2024
- SK hynix Inc.
- Hyung Jin Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory, programming method therefor and memory system
- Patent number 12,068,035
- Issue date Aug 20, 2024
- Yangtze Memory Technologies Co., Ltd.
- Zhipeng Dong
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory device for performing precharge to cell string...
- Patent number 12,062,402
- Issue date Aug 13, 2024
- Samsung Electronics Co., Ltd.
- Byungsoo Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Neural network array comprising one or more coarse cells and one or...
- Patent number 12,057,170
- Issue date Aug 6, 2024
- Silicon Storage Technology, Inc.
- Hieu Van Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of programming a select transistor of a semiconductor memory...
- Patent number 12,057,165
- Issue date Aug 6, 2024
- SK hynix Inc.
- Hee Youl Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Transistor and method for manufacturing the same
- Patent number 12,051,755
- Issue date Jul 30, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Yu-Chu Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compact EEPROM memory cell with a gate dielectric layer having two...
- Patent number 12,052,861
- Issue date Jul 30, 2024
- STMicroelectronics (Rousset) SAS
- François Tailliet
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE, THE OPERATION METHOD THEREOF AND MEMORY SYSTEM
- Publication number 20240428855
- Publication date Dec 26, 2024
- Yangtze Memory Technologies Co., Ltd.
- Zhihong Li
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND OPERATING METHOD OF MEMORY DEVICE
- Publication number 20240428861
- Publication date Dec 26, 2024
- SK HYNIX INC.
- Suk Hwan CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE
- Publication number 20240420763
- Publication date Dec 19, 2024
- SK HYNIX INC.
- Jung Shik JANG
- G11 - INFORMATION STORAGE
Information Patent Application
READ POWER SAVINGS BY TEMPORARILY DISABLING BITLINE VOLTAGE
- Publication number 20240420773
- Publication date Dec 19, 2024
- Western Digital Technologies, Inc.
- Xiang Yang
- G11 - INFORMATION STORAGE
Information Patent Application
OPEN BLOCK DETECTION METHOD USING FOR FIRST AND SECOND TIME PERIOD...
- Publication number 20240420775
- Publication date Dec 19, 2024
- Western Digital Technologies, Inc.
- Albert Chen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD OF OPERATING MEMORY DEVICE
- Publication number 20240420777
- Publication date Dec 19, 2024
- SK HYNIX INC.
- Byoung Young KIM
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR INPUTTING AND OUTPUTTING DATA AND A MEMORY SYSTEM...
- Publication number 20240420776
- Publication date Dec 19, 2024
- SK HYNIX INC.
- Byoung Young KIM
- G11 - INFORMATION STORAGE
Information Patent Application
ALTERNATING BITLINE PAGE MAPPING WITH LINEAR WORDLINE RAMPING DURIN...
- Publication number 20240404601
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Tomoharu Tanaka
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC BITSCAN FOR NON-VOLATILE MEMORY
- Publication number 20240404607
- Publication date Dec 5, 2024
- Western Digital Technologies, Inc.
- Yidan Liu
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH SUB-BLOCK ERASE
- Publication number 20240395332
- Publication date Nov 28, 2024
- Western Digital Technologies, Inc.
- Ming Wang
- G11 - INFORMATION STORAGE
Information Patent Application
USING NON-SEGREGATED CELLS AS DRAIN-SIDE SELECT GATES FOR SUB-BLOCK...
- Publication number 20240386965
- Publication date Nov 21, 2024
- Micron Technology, Inc.
- Aaron S. Yip
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE
- Publication number 20240379168
- Publication date Nov 14, 2024
- SK HYNIX INC.
- Hyung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
MULTI-STEP READ PASS VOLTAGE DISCHARGE FOR ICC REDUCTION
- Publication number 20240379170
- Publication date Nov 14, 2024
- Western Digital Technologies, Inc.
- Albert Bor Kai Chen
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF
- Publication number 20240371451
- Publication date Nov 7, 2024
- SK HYNIX INC.
- Hyung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
FULL SEQUENCE PROGRAM FOR EDGE WORD LINE QUAD-LEVEL MEMORY CELLS
- Publication number 20240363167
- Publication date Oct 31, 2024
- Western Digital Technologies, Inc.
- Sisi Yang
- G11 - INFORMATION STORAGE
Information Patent Application
SEPARATE PEAK CURRENT CHECKPOINTS FOR CLOSED AND OPEN BLOCK READ IC...
- Publication number 20240355400
- Publication date Oct 24, 2024
- SANDISK TECHNOLOGIES LLC
- Abu Naser Zainuddin
- G11 - INFORMATION STORAGE
Information Patent Application
NEGATIVE WORD LINE ENABLED PRE-BOOSTING STRATEGY TO IMPROVE NAND PR...
- Publication number 20240355401
- Publication date Oct 24, 2024
- SANDISK TECHNOLOGIES LLC
- Wei Cao
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
- Publication number 20240347645
- Publication date Oct 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Chu LIN
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND OPERATION METHOD THEREOF
- Publication number 20240331775
- Publication date Oct 3, 2024
- Yangtze Memory Technologies Co., Ltd.
- Li Xiang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND METHOD
- Publication number 20240321362
- Publication date Sep 26, 2024
- KIOXIA Corporation
- Hideki IGARASHI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE
- Publication number 20240321374
- Publication date Sep 26, 2024
- KIOXIA Corporation
- Manabu SATO
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION
- Publication number 20240312524
- Publication date Sep 19, 2024
- SK HYNIX INC.
- Hyung Jin CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
RE-DRIVING DATA TO A SUB-BLOCK DURING PROGRAMMING OF MULTIPLE SUB-B...
- Publication number 20240312525
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
CORRECTIVE READ WITH PARTIAL BLOCK OFFSET IN A MEMORY DEVICE
- Publication number 20240312529
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Karan Banerjee
- G11 - INFORMATION STORAGE
Information Patent Application
EXECUTION OF A PROGRAM BIAS DISTURB MITIGATION OPERATION ASSOCIATED...
- Publication number 20240312537
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR PARALLEL MEMORY CELL ACCESS
- Publication number 20240304244
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Paolo Fantini
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR SUMMATION OF OUTPUTS OF SIGNED MULTIPLICATIONS
- Publication number 20240304253
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Hernan Castro
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS WITH DIFFERENT...
- Publication number 20240304255
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Hernan Castro
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR SIGNED MULTI-BIT TO MULTI-BIT MULTIPLICATIONS
- Publication number 20240304254
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Hernan Castro
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POST-PROGRAM ERASE IN 3D NAND
- Publication number 20240296891
- Publication date Sep 5, 2024
- Western Digital Technologies, Inc.
- Ming Wang
- G11 - INFORMATION STORAGE

comprising cells containing a single floating gate transistor and one or more separate select transistors

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory circuits and devices, and methods thereof

Memory device, operating method thereof, system, and storage medium

Memory device and method of operating the memory device

Operating a chalcogenide memory with vertical word and vertical wor...

Computing-in-memory architecture

Word line dependent pass voltage ramp rate to improve performance o...

Setting levels for a programming operation in a neural network array

Memory device and method of operating the same

Static random access memory apparatus that maintains stable write p...

Semiconductor device

Multi-time programmable non-volatile memory cell and memory with lo...

Memory device and method of operating the same

Semiconductor memory device including active regions for reducing d...

Non-volatile memory device readable only a predetermined number of...

Memory architecture for serial EEPROMs

Memory device, the operation method thereof and memory system

Memory device storing logical page data and operating method of the...

Non-volatile memory device

Semiconductor device

Resistive memory device including reference cell to compensate for...

Using non-segregated cells as drain-side select gates for sub-block...

Non-volatile memory device

Memory device and method of operating the memory device including d...

Semiconductor memory device and operating method thereof

Memory, programming method therefor and memory system

Non-volatile memory device for performing precharge to cell string...

Neural network array comprising one or more coarse cells and one or...

Method of programming a select transistor of a semiconductor memory...

Transistor and method for manufacturing the same

Compact EEPROM memory cell with a gate dielectric layer having two...

Patents Applicationslast 30 patents

MEMORY DEVICE, THE OPERATION METHOD THEREOF AND MEMORY SYSTEM

MEMORY DEVICE AND OPERATING METHOD OF MEMORY DEVICE

MEMORY DEVICE AND OPERATING METHOD OF THE MEMORY DEVICE

READ POWER SAVINGS BY TEMPORARILY DISABLING BITLINE VOLTAGE

OPEN BLOCK DETECTION METHOD USING FOR FIRST AND SECOND TIME PERIOD...

MEMORY DEVICE AND METHOD OF OPERATING MEMORY DEVICE

MEMORY DEVICE FOR INPUTTING AND OUTPUTTING DATA AND A MEMORY SYSTEM...

ALTERNATING BITLINE PAGE MAPPING WITH LINEAR WORDLINE RAMPING DURIN...

DYNAMIC BITSCAN FOR NON-VOLATILE MEMORY

NON-VOLATILE MEMORY WITH SUB-BLOCK ERASE

USING NON-SEGREGATED CELLS AS DRAIN-SIDE SELECT GATES FOR SUB-BLOCK...

MEMORY DEVICE

MULTI-STEP READ PASS VOLTAGE DISCHARGE FOR ICC REDUCTION

SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

FULL SEQUENCE PROGRAM FOR EDGE WORD LINE QUAD-LEVEL MEMORY CELLS

SEPARATE PEAK CURRENT CHECKPOINTS FOR CLOSED AND OPEN BLOCK READ IC...

NEGATIVE WORD LINE ENABLED PRE-BOOSTING STRATEGY TO IMPROVE NAND PR...

TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME

MEMORY DEVICE AND OPERATION METHOD THEREOF

MEMORY DEVICE AND METHOD

MEMORY DEVICE

SEMICONDUCTOR MEMORY DEVICE FOR PERFORMING PROGRAM OPERATION

RE-DRIVING DATA TO A SUB-BLOCK DURING PROGRAMMING OF MULTIPLE SUB-B...

CORRECTIVE READ WITH PARTIAL BLOCK OFFSET IN A MEMORY DEVICE

EXECUTION OF A PROGRAM BIAS DISTURB MITIGATION OPERATION ASSOCIATED...

TECHNIQUES FOR PARALLEL MEMORY CELL ACCESS

MEMORY DEVICE FOR SUMMATION OF OUTPUTS OF SIGNED MULTIPLICATIONS

MEMORY DEVICE FOR MULTIPLICATION USING MEMORY CELLS WITH DIFFERENT...

MEMORY DEVICE FOR SIGNED MULTI-BIT TO MULTI-BIT MULTIPLICATIONS

POST-PROGRAM ERASE IN 3D NAND