Data generation devices

Industry

CPC
G11C29/36

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/36Data generation devices

Industries

Patents Grantslast 30 patents

Information Patent Grant
Memory interface circuitry and built-in self-testing method
- Patent number 12,183,411
- Issue date Dec 31, 2024
- Integrated Silicon Solution Inc.
- Hyeon Jae Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Test method for testing decision feedback equalization of memory de...
- Patent number 12,176,051
- Issue date Dec 24, 2024
- NANYA TECHNOLOGY CORPORATION
- Yi-Hsuan Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in self test circuit for segmented static random access memor...
- Patent number 12,170,120
- Issue date Dec 17, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Hitesh Chawla
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device including command log register and comm...
- Patent number 12,170,121
- Issue date Dec 17, 2024
- Samsung Electronics Co., Ltd.
- Youngsan Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Granular voltage tuning
- Patent number 12,158,814
- Issue date Dec 3, 2024
- PURE STORAGE, INC.
- Hari Kannan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storing memory array operational information in non-volatile subarrays
- Patent number 12,158,826
- Issue date Dec 3, 2024
- Micron Technology, Inc.
- Christopher John Kawamura
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Intelligent memory device test rack
- Patent number 12,142,336
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Gary D. Hamor
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for correcting an error in data transmission o...
- Patent number 12,125,549
- Issue date Oct 22, 2024
- MIMIRIP LLC
- In Jong Jang
- G11 - INFORMATION STORAGE
Information Patent Grant
Test method, computer apparatus, and computer-readable storage medium
- Patent number 12,112,817
- Issue date Oct 8, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Biao Song
- G11 - INFORMATION STORAGE
Information Patent Grant
Capacity-expanding memory control component
- Patent number 12,095,480
- Issue date Sep 17, 2024
- Astera Labs, Inc.
- Enrique Musoll
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor system for performing an active operation using an ac...
- Patent number 12,080,333
- Issue date Sep 3, 2024
- SK hynix Inc.
- Choung Ki Song
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic contact management systems and methods
- Patent number 12,079,819
- Issue date Sep 3, 2024
- LeadAssign Corporation
- Desmond Von Teichman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing system error management, related integrated circuit, app...
- Patent number 12,068,048
- Issue date Aug 20, 2024
- TMicroelectronics Application GMBH
- Vivek Mohan Sharma
- G11 - INFORMATION STORAGE
Information Patent Grant
Test access port architecture to facilitate multiple testing modes
- Patent number 12,057,183
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Michael Richard Spica
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing disruptive memories
- Patent number 12,051,476
- Issue date Jul 30, 2024
- NXP USA, INC.
- Timothy Strauss
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit protections against removal and oracle-guided at...
- Patent number 12,039,091
- Issue date Jul 16, 2024
- Duke University
- Jonti Talukdar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory with autonomous cycling
- Patent number 12,040,031
- Issue date Jul 16, 2024
- Western Digital Technologies, Inc.
- Liang Li
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for conducting built-in self-test of memory macro
- Patent number 12,033,710
- Issue date Jul 9, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ted Wong
- G11 - INFORMATION STORAGE
Information Patent Grant
ATPG testing method for latch based memories, for area reduction
- Patent number 12,020,760
- Issue date Jun 25, 2024
- STMICROELECTRONICS INTERNATIONAL N.V.
- Venkata Narayanan Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Correcting memory data using an error code and a memory test result
- Patent number 11,996,859
- Issue date May 28, 2024
- Amazon Technologies, Inc.
- Itai Avron
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing register with non-volatile-logic data storage
- Patent number 11,990,196
- Issue date May 21, 2024
- Texas Instruments Incorporated
- Adolf Baumann
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and devices for flexible RAM loading
- Patent number 11,984,178
- Issue date May 14, 2024
- STMicroelectronics S.r.l.
- Gabriele Solcia
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for testing multicore SSD firmware based on preco...
- Patent number 11,967,391
- Issue date Apr 23, 2024
- SK Hynix Inc.
- Yahor Zaitsau
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for processing memory repair information
- Patent number 11,961,576
- Issue date Apr 16, 2024
- Benoit Nadeau-Dostie
- G11 - INFORMATION STORAGE
Information Patent Grant
Testing circuit, testing device and testing method thereof
- Patent number 11,948,650
- Issue date Apr 2, 2024
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Liang Zhang
- G11 - INFORMATION STORAGE
Information Patent Grant
Distributed phased SRAM repair for systems on a chip
- Patent number 11,948,654
- Issue date Apr 2, 2024
- Meta Platforms Technologies, LLC
- Shrirang Madhav Yardi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and device for processing data stored in a memory unit
- Patent number 11,947,807
- Issue date Apr 2, 2024
- Robert Bosch GmbH
- Manuel Jauss
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory apparatus and semiconductor system including the same
- Patent number 11,942,173
- Issue date Mar 26, 2024
- SK hynix Inc.
- Heeeun Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Path based controls for ATE mode testing of multicell memory circuit
- Patent number 11,933,844
- Issue date Mar 19, 2024
- Texas Instruments Incorporated
- Wilson Pradeep
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
EVOLVING BAD BLOCK DETECTION IN NON-VOLATILE MEMORY
- Publication number 20250006285
- Publication date Jan 2, 2025
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
RECONFIGURABLE MBIST METHOD BASED ON ADAPTIVE MARCH ALGORITHM
- Publication number 20250006289
- Publication date Jan 2, 2025
- Nanjing University Of Posts And Telecommunications
- Zhikuang CAI
- G11 - INFORMATION STORAGE
Information Patent Application
HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING
- Publication number 20250006290
- Publication date Jan 2, 2025
- ADVANCED MICRO DEVICES, INC.
- Nehal Patel
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR WRITE DATA PRECONDITIONING USING A NEUR...
- Publication number 20240412796
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Fa-Long Luo
- G11 - INFORMATION STORAGE
Information Patent Application
Circuits And Methods For Memory Built-In-Self-Tests
- Publication number 20240412799
- Publication date Dec 12, 2024
- Altera Corporation
- Kok Wah Khor
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR SYSTEM FOR PERFORMING AN ACTIVE OPERATION USING AN AC...
- Publication number 20240395306
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Choung Ki SONG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR SYSTEM FOR PERFORMING AN ACTIVE OPERATION USING AN AC...
- Publication number 20240395307
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Choung Ki SONG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR SYSTEM FOR PERFORMING AN ACTIVE OPERATION USING AN AC...
- Publication number 20240395305
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Choung Ki SONG
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR READ DATA PRECONDITIONING USING A NEURA...
- Publication number 20240379181
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Fa-Long Luo
- G11 - INFORMATION STORAGE
Information Patent Application
TEST METHOD FOR TESTING DECISION FEEDBACK EQUALIZATION OF MEMORY DE...
- Publication number 20240331791
- Publication date Oct 3, 2024
- NANYA TECHNOLOGY CORPORATION
- Yi-Hsuan Chu
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD FOR CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO
- Publication number 20240321377
- Publication date Sep 26, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ted Wong
- G11 - INFORMATION STORAGE
Information Patent Application
Content addressable memory apparatus, content addressable memory ci...
- Publication number 20240312548
- Publication date Sep 19, 2024
- REALTEK SEMICONDUCTOR CORPORATION
- I-HAO CHIANG
- G11 - INFORMATION STORAGE
Information Patent Application
ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION
- Publication number 20240296899
- Publication date Sep 5, 2024
- STMicroelectronics International N.V.
- Venkata Narayanan SRINIVASAN
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE FOR DETECTING DEFECT IN WORD LINE DRIVER
- Publication number 20240290415
- Publication date Aug 29, 2024
- SK HYNIX INC.
- Byeong Cheol LEE
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY INTERFACE CIRCUITRY AND BUILT-IN SELF-TESTING METHOD
- Publication number 20240274214
- Publication date Aug 15, 2024
- Integrated Silicon Solution Inc.
- Hyeon Jae LEE
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20240249791
- Publication date Jul 25, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Repair Device
- Publication number 20240233853
- Publication date Jul 11, 2024
- Magnachip Semiconductor, Ltd.
- Jun Soo KWACK
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNOLOGIES FOR DYNAMIC ACCELERATOR SELECTION
- Publication number 20240195605
- Publication date Jun 13, 2024
- Intel Corporation
- Francesc Guim Bernat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME
- Publication number 20240194285
- Publication date Jun 13, 2024
- SK HYNIX INC.
- HEEEUN CHOI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY TESTING SYSTEM AND MEMORY TESTING METHOD
- Publication number 20240161857
- Publication date May 16, 2024
- NANYA TECHNOLOGY CORPORATION
- Chien Yu CHEN
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD, DEVICE, AND CIRCUIT FOR HIGH-SPEED MEMORIES
- Publication number 20240153573
- Publication date May 9, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jaspal Singh SHAH
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF TESTING STORAGE CONTROLLER INCLUDED IN STORAGE DEVICE
- Publication number 20240153575
- Publication date May 9, 2024
- Samsung Electronics Co., Ltd.
- Jongyeong JUNG
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Repair Device
- Publication number 20240136007
- Publication date Apr 25, 2024
- Magnachip Semiconductor, Ltd.
- Jun Soo KWACK
- G11 - INFORMATION STORAGE
Information Patent Application
AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
- Publication number 20240120016
- Publication date Apr 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY QUEUE OPERATIONS TO INCREASE THROUGHPUT IN AN ATE SYSTEM
- Publication number 20240096432
- Publication date Mar 21, 2024
- Advantest Corporation
- Edmundo de la Puente
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF-TEST CIRCUITRY
- Publication number 20240087663
- Publication date Mar 14, 2024
- Micron Technology, Inc.
- William Yu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY TEST CIRCUIT, MEMORY CHIP, AND TESTING METHOD OF MEMORY CHIP
- Publication number 20240079075
- Publication date Mar 7, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Jen Wu
- G11 - INFORMATION STORAGE
Information Patent Application
BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...
- Publication number 20240071546
- Publication date Feb 29, 2024
- STMicroelectronics International N.V.
- Hitesh CHAWLA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY AND METHOD WITH IN-MEMORY COMPUTING DEFECT DETECTION
- Publication number 20240071548
- Publication date Feb 29, 2024
- Samsung Electronics Co., Ltd.
- Sungmeen MYUNG
- G11 - INFORMATION STORAGE
Information Patent Application
CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO
- Publication number 20240055066
- Publication date Feb 15, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Ted Wong
- G11 - INFORMATION STORAGE

Data generation devices

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory interface circuitry and built-in self-testing method

Test method for testing decision feedback equalization of memory de...

Built-in self test circuit for segmented static random access memor...

Semiconductor memory device including command log register and comm...

Granular voltage tuning

Storing memory array operational information in non-volatile subarrays

Intelligent memory device test rack

Apparatus and method for correcting an error in data transmission o...

Test method, computer apparatus, and computer-readable storage medium

Capacity-expanding memory control component

Semiconductor system for performing an active operation using an ac...

Dynamic contact management systems and methods

Processing system error management, related integrated circuit, app...

Test access port architecture to facilitate multiple testing modes

Testing disruptive memories

Integrated circuit protections against removal and oracle-guided at...

Non-volatile memory with autonomous cycling

System and method for conducting built-in self-test of memory macro

ATPG testing method for latch based memories, for area reduction

Correcting memory data using an error code and a memory test result

Computing register with non-volatile-logic data storage

Methods and devices for flexible RAM loading

System and method for testing multicore SSD firmware based on preco...

Single “A” latch with an array of “B” latches

Method and apparatus for processing memory repair information

Testing circuit, testing device and testing method thereof

Distributed phased SRAM repair for systems on a chip

Method and device for processing data stored in a memory unit

Memory apparatus and semiconductor system including the same

Path based controls for ATE mode testing of multicell memory circuit

Patents Applicationslast 30 patents

EVOLVING BAD BLOCK DETECTION IN NON-VOLATILE MEMORY

RECONFIGURABLE MBIST METHOD BASED ON ADAPTIVE MARCH ALGORITHM

HOST-TO-DEVICE INTERFACE CIRCUITRY TESTING

APPARATUSES AND METHODS FOR WRITE DATA PRECONDITIONING USING A NEUR...

Circuits And Methods For Memory Built-In-Self-Tests

SEMICONDUCTOR SYSTEM FOR PERFORMING AN ACTIVE OPERATION USING AN AC...

SEMICONDUCTOR SYSTEM FOR PERFORMING AN ACTIVE OPERATION USING AN AC...

SEMICONDUCTOR SYSTEM FOR PERFORMING AN ACTIVE OPERATION USING AN AC...

APPARATUSES AND METHODS FOR READ DATA PRECONDITIONING USING A NEURA...

TEST METHOD FOR TESTING DECISION FEEDBACK EQUALIZATION OF MEMORY DE...

SYSTEM AND METHOD FOR CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO

Content addressable memory apparatus, content addressable memory ci...

ATPG TESTING METHOD FOR LATCH BASED MEMORIES, FOR AREA REDUCTION

SEMICONDUCTOR DEVICE FOR DETECTING DEFECT IN WORD LINE DRIVER

MEMORY INTERFACE CIRCUITRY AND BUILT-IN SELF-TESTING METHOD

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

Memory Repair Device

TECHNOLOGIES FOR DYNAMIC ACCELERATOR SELECTION

MEMORY APPARATUS AND SEMICONDUCTOR SYSTEM INCLUDING THE SAME

MEMORY TESTING SYSTEM AND MEMORY TESTING METHOD

METHOD, DEVICE, AND CIRCUIT FOR HIGH-SPEED MEMORIES

METHOD OF TESTING STORAGE CONTROLLER INCLUDED IN STORAGE DEVICE

Memory Repair Device

AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES

MEMORY QUEUE OPERATIONS TO INCREASE THROUGHPUT IN AN ATE SYSTEM

BUILT-IN SELF-TEST CIRCUITRY

MEMORY TEST CIRCUIT, MEMORY CHIP, AND TESTING METHOD OF MEMORY CHIP

BUILT-IN SELF TEST CIRCUIT FOR SEGMENTED STATIC RANDOM ACCESS MEMOR...

MEMORY AND METHOD WITH IN-MEMORY COMPUTING DEFECT DETECTION

CONDUCTING BUILT-IN SELF-TEST OF MEMORY MACRO