Decoding the operand specifier

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G06F9/3016

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/3016Decoding the operand specifier

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Patents Grantslast 30 patents

Information Patent Grant
Streaming engine with stream metadata saving for context switching
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- Issue date May 13, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
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Information Patent Grant
Employing sampled register values to infer memory accesses by an ap...
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- Issue date May 13, 2025
- Microsoft Technology Licensing, LLC
- Danny Chen
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Information Patent Grant
Systems and methods of instructions to accelerate multiplication of...
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- Issue date Apr 29, 2025
- Intel Corporation
- Dan Baum
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stream data unit with multiple head registers
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- Issue date Apr 29, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Program counter zero-cycle loads
- Patent number 12,288,070
- Issue date Apr 29, 2025
- Apple Inc.
- Muawya M. Al-Otoom
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Information Patent Grant
Register addressing information for data transfer instruction
- Patent number 12,288,071
- Issue date Apr 29, 2025
- ARM Limited
- Nigel John Stephens
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Information Patent Grant
Systems, methods, and apparatus for tile configuration
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- Issue date Apr 22, 2025
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- Menachem Adelman
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Information Patent Grant
Configuration of a deep vector engine using an opcode table, contro...
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- Issue date Apr 8, 2025
- Amazon Technologies, Inc.
- Paul Gilbert Meyer
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Information Patent Grant
Forming constant extensions in the same execute packet in a VLIW pr...
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Information Patent Grant
Systems, methods, and apparatuses for matrix add, subtract, and mul...
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Information Patent Grant
Processing apparatus, method and system for executing data processi...
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Information Patent Grant
Configurable vector compute engine
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Information Patent Grant
Look-up table initialize
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Information Patent Grant
Two address translations from a single table look-aside buffer read
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Information Patent Grant
Systems and methods for data placement for in-memory-compute
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Information Patent Grant
Synchronizing scheduling tasks with atomic ALU
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Information Patent Grant
In-core parallelization in a data processing apparatus and method
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- Issue date Feb 18, 2025
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Information Patent Grant
Systems and methods for programmed branch predictors
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- Issue date Feb 4, 2025
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- Alexander Toufic Freij
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Information Patent Grant
System and method for model-agnostic meta-learner for noisy data wi...
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- Issue date Jan 28, 2025
- YAHOO ASSETS LLC
- Eliyar Asgarieh
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Information Patent Grant
Implicit global pointer relative addressing for global memory access
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- Issue date Jan 28, 2025
- MIPS Tech, LLC
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Information Patent Grant
Inserting predefined pad values into a stream of vectors
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- Issue date Jan 21, 2025
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- Asheesh Bhardwaj
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Processing instructions selected from a first instruction set in a...
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Information Patent Grant
Accelerating eight-way parallel Keccak execution
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Information Patent Grant
Systems, methods, and apparatuses for tile load, multiplication and...
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Information Patent Grant
Systems and methods for computing dot products of nibbles in two ti...
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- Intel Corporation
- Raanan Sade
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Information Patent Grant
Concurrent multi-datatype execution within a processing resource
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- Issue date Dec 24, 2024
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- Elmoustapha Ould-Ahmed-Vall
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Information Patent Grant
Re-use of speculative load instruction results from wrong path
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- Issue date Dec 24, 2024
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- Yuan C. Chou
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Information Patent Grant
Load-with-substitution instruction
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- Issue date Dec 24, 2024
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- Eric Ola Harald Liljedahl
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Information Patent Grant
Tracking streaming engine vector predicates to control processor ex...
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- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Duc Quang Bui
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS
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SUB-VECTOR-SUPPORTING INSTRUCTION FOR SCALABLE VECTOR INSTRUCTION S...
- Publication number 20250156184
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- ARM Limited
- Alejandro Martinez Vicente
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Information Patent Application
SYNCHRONIZING SCHEDULING TASKS WITH ATOMIC ALU
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- Publication date May 8, 2025
- Imagination Technologies Limited
- Ollie Mower
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATING EIGHT-WAY PARALLEL KECCAK EXECUTION
- Publication number 20250138829
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- Santosh Ghosh
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Processor, Instruction Fetching Method, and Computer System
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METHODS AND APPARATUS FOR PROCESSING INSTRUCTIONS
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- ARM Limited
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Implicit Global Pointer Relative Addressing for Global Memory Access
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SYSTEMS, METHODS, AND APPARATUSES FOR TILE TRANSPOSE
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- Robert VALENTINE
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SYSTEMS, METHODS, AND APPARATUSES FOR TILE MATRIX MULTIPLICATION AN...
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PROCESSOR, METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING
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SUPPORTING 8-BIT FLOATING POINT FORMAT FOR PARALLEL COMPUTING AND S...
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TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...
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- TEXAS INSTRUMENTS INCORPORATED
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APPARATUS AND METHOD FOR PARTITIONED SHUFFLES
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SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA FOR MONITORING THIRD...
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SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND I...
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METHOD AND APPARATUS FOR DATA/INSTRUCTION ACCESS BASED ON PERFORMAN...
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INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...
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SCALAR CORE INTEGRATION
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Parallel decoding method, processor, chip and electronic device
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VECTOR SHUFFLING METHOD, PROCESSOR AND ELECTRONIC DEVICE
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PADDING IN A STREAM OF MATRIX ELEMENTS
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TECHNIQUES FOR CONTROLLING VECTOR PROCESSING OPERATIONS
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SYSTEM AND METHOD FOR MODEL-AGNOSTIC META-LEARNER FOR NOISY DATA WI...
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METHODS AND SYSTEMS FOR INTER-PIPELINE DATA HAZARD AVOIDANCE
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STREAMING ADDRESS GENERATION
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SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD
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CONDITIONAL BRANCH INSTRUCTIONS FOR AGGREGATING CONDITIONAL BRANCH...
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- TEXAS INSTRUMENTS INCORPORATED
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- G06 - COMPUTING CALCULATING COUNTING

Decoding the operand specifier

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Streaming engine with stream metadata saving for context switching

Employing sampled register values to infer memory accesses by an ap...

Systems and methods of instructions to accelerate multiplication of...

Stream data unit with multiple head registers

Program counter zero-cycle loads

Register addressing information for data transfer instruction

Systems, methods, and apparatus for tile configuration

Configuration of a deep vector engine using an opcode table, contro...

Forming constant extensions in the same execute packet in a VLIW pr...

Systems, methods, and apparatuses for matrix add, subtract, and mul...

Processing apparatus, method and system for executing data processi...

Processor micro-architecture for compute, save or restore multiple...

Configurable vector compute engine

Look-up table initialize

Two address translations from a single table look-aside buffer read

Systems and methods for data placement for in-memory-compute

Synchronizing scheduling tasks with atomic ALU

In-core parallelization in a data processing apparatus and method

Systems and methods for programmed branch predictors

System and method for model-agnostic meta-learner for noisy data wi...

Implicit global pointer relative addressing for global memory access

Inserting predefined pad values into a stream of vectors

Processing instructions selected from a first instruction set in a...

Accelerating eight-way parallel Keccak execution

Systems, methods, and apparatuses for tile load, multiplication and...

Systems and methods for computing dot products of nibbles in two ti...

Concurrent multi-datatype execution within a processing resource

Re-use of speculative load instruction results from wrong path

Load-with-substitution instruction

Tracking streaming engine vector predicates to control processor ex...

Patents Applicationslast 30 patents

INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS

Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...

SUB-VECTOR-SUPPORTING INSTRUCTION FOR SCALABLE VECTOR INSTRUCTION S...

SYNCHRONIZING SCHEDULING TASKS WITH ATOMIC ALU

ACCELERATING EIGHT-WAY PARALLEL KECCAK EXECUTION

Processor, Instruction Fetching Method, and Computer System

METHODS AND APPARATUS FOR PROCESSING INSTRUCTIONS

Implicit Global Pointer Relative Addressing for Global Memory Access

SYSTEMS, METHODS, AND APPARATUSES FOR TILE TRANSPOSE

SYSTEMS, METHODS, AND APPARATUSES FOR TILE MATRIX MULTIPLICATION AN...

PROCESSOR, METHOD, DEVICE AND STORAGE MEDIUM FOR DATA PROCESSING

SUPPORTING 8-BIT FLOATING POINT FORMAT FOR PARALLEL COMPUTING AND S...

TRACKING STREAMING ENGINE VECTOR PREDICATES TO CONTROL PROCESSOR EX...

APPARATUS AND METHOD FOR PARTITIONED SHUFFLES

SYSTEMS, METHODS, AND COMPUTER-READABLE MEDIA FOR MONITORING THIRD...

SM3 HASH ALGORITHM ACCELERATION PROCESSORS, METHODS, SYSTEMS, AND I...

METHOD AND APPARATUS FOR DATA/INSTRUCTION ACCESS BASED ON PERFORMAN...

INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...

SCALAR CORE INTEGRATION

Parallel decoding method, processor, chip and electronic device

VECTOR SHUFFLING METHOD, PROCESSOR AND ELECTRONIC DEVICE

PADDING IN A STREAM OF MATRIX ELEMENTS

TECHNIQUES FOR CONTROLLING VECTOR PROCESSING OPERATIONS

SYSTEM AND METHOD FOR MODEL-AGNOSTIC META-LEARNER FOR NOISY DATA WI...

METHODS AND SYSTEMS FOR INTER-PIPELINE DATA HAZARD AVOIDANCE

STREAMING ADDRESS GENERATION

METHOD AND APPARATUS FOR DECOMPRESSION HARDWARE COPY ENGINE WITH EF...

SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD

CONDITIONAL BRANCH INSTRUCTIONS FOR AGGREGATING CONDITIONAL BRANCH...

METHOD AND APPARATUS FOR VECTOR PERMUTATION