Decoding the operand specifier

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/3016Decoding the operand specifier

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Patents Grantslast 30 patents

Information Patent Grant
Two address translations from a single table look-aside buffer read
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- Issue date Feb 25, 2025
- Texas Instruments Incorporated
- Joseph Zbiciak
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Information Patent Grant
Systems and methods for data placement for in-memory-compute
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Information Patent Grant
Synchronizing scheduling tasks with atomic ALU
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- Issue date Feb 18, 2025
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- Ollie Mower
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Information Patent Grant
In-core parallelization in a data processing apparatus and method
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Information Patent Grant
Systems and methods for programmed branch predictors
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Information Patent Grant
System and method for model-agnostic meta-learner for noisy data wi...
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- Issue date Jan 28, 2025
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- Eliyar Asgarieh
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Information Patent Grant
Implicit global pointer relative addressing for global memory access
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- Issue date Jan 28, 2025
- MIPS Tech, LLC
- James Hippisley Robinson
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Information Patent Grant
Inserting predefined pad values into a stream of vectors
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- Issue date Jan 21, 2025
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- Asheesh Bhardwaj
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Information Patent Grant
Processing instructions selected from a first instruction set in a...
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- Nigel John Stephens
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Information Patent Grant
Accelerating eight-way parallel Keccak execution
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Information Patent Grant
Systems, methods, and apparatuses for tile load, multiplication and...
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Information Patent Grant
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- Raanan Sade
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Information Patent Grant
Concurrent multi-datatype execution within a processing resource
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Information Patent Grant
Re-use of speculative load instruction results from wrong path
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Information Patent Grant
Load-with-substitution instruction
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Tracking streaming engine vector predicates to control processor ex...
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Processor that executes instruction that specifies instruction conc...
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Information Patent Grant
Method for processing multiple transactions converted from single t...
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- Kwang Sun Lee
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Systems, methods, and apparatuses for tile matrix multiplication an...
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SM3 hash algorithm acceleration processors, methods, systems, and i...
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- Issue date Oct 29, 2024
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Systems, methods, and apparatuses for tile transpose
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Scalar core integration
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One-dimensional zero padding in a stream of matrix elements
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- Son Hung Tran
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Central processing unit with asynchronous registers
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Memory interface
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Data processing method and apparatus, and related product for incre...
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- Shaoli Liu
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Information Patent Grant
Method and apparatus for vector permutation
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- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Timothy David Anderson
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Information Patent Grant
Systems, methods, and apparatuses for matrix operations
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- Issue date Oct 1, 2024
- Intel Corporation
- Robert Valentine
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Information Patent Grant
Memory device with internal processing interface
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- Issue date Sep 24, 2024
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- Hak-soo Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Streaming address generation
- Patent number 12,099,843
- Issue date Sep 24, 2024
- Texas Instruments Incorporated
- Timothy David Anderson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR DATA/INSTRUCTION ACCESS BASED ON PERFORMAN...
- Publication number 20250068424
- Publication date Feb 27, 2025
- Duane GALBI
- G06 - COMPUTING CALCULATING COUNTING
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INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...
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SCALAR CORE INTEGRATION
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Parallel decoding method, processor, chip and electronic device
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- HYGON INFORMATION TECHNOLOGY CO., LTD.
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VECTOR SHUFFLING METHOD, PROCESSOR AND ELECTRONIC DEVICE
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PADDING IN A STREAM OF MATRIX ELEMENTS
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- TEXAS INSTRUMENTS INCORPORATED
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TECHNIQUES FOR CONTROLLING VECTOR PROCESSING OPERATIONS
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- Mbou Eyole
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SYSTEM AND METHOD FOR MODEL-AGNOSTIC META-LEARNER FOR NOISY DATA WI...
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METHODS AND SYSTEMS FOR INTER-PIPELINE DATA HAZARD AVOIDANCE
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- Luca Iuliano
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STREAMING ADDRESS GENERATION
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METHOD AND APPARATUS FOR DECOMPRESSION HARDWARE COPY ENGINE WITH EF...
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SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD
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CONDITIONAL BRANCH INSTRUCTIONS FOR AGGREGATING CONDITIONAL BRANCH...
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- TEXAS INSTRUMENTS INCORPORATED
- Alexander Tessarolo
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METHOD AND APPARATUS FOR VECTOR PERMUTATION
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- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Timothy David Anderson
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MEMORY DEVICE WITH INTERNAL PROCESSING INTERFACE
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CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS
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PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT
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VARIABLE LATENCY INSTRUCTIONS
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LOOK-UP TABLE READ
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DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS
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Processor having Switch Instruction Circuit
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- Publication date Nov 28, 2024
- Microchip Technology Inc.
- Christopher I. W. NORRIE
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MEMORY INTERFACE
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- Publication date Nov 21, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hiroki NOGUCHI
- G06 - COMPUTING CALCULATING COUNTING
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CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE
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METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS
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- TEXAS INSTRUMENTS INCORPORATED
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STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME T...
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- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
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TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS
- Publication number 20240378058
- Publication date Nov 14, 2024
- TEXAS INSTRUMENTS INCORPORATED
- William Franklin Leven
- G06 - COMPUTING CALCULATING COUNTING
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Systems and Methods Providing Pause for Interrupts and Shared Memor...
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- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Alexander Tessarolo
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A DATA PROCESSING APPARATUS AND METHOD FOR TRANSMITTING TRIGGERED I...
- Publication number 20240370263
- Publication date Nov 7, 2024
- ARM Limited
- Balaji Venu
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Information Patent Application
STORAGE ORGANIZATION FOR TRANSPOSING A MATRIX USING A STREAMING ENGINE
- Publication number 20240370264
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Jonathan (Son) Hung Tran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO ALIGN DATA TO AD...
- Publication number 20240362023
- Publication date Oct 31, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Saya Goud Langadi
- G06 - COMPUTING CALCULATING COUNTING

Decoding the operand specifier

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Two address translations from a single table look-aside buffer read

Systems and methods for data placement for in-memory-compute

Synchronizing scheduling tasks with atomic ALU

In-core parallelization in a data processing apparatus and method

Systems and methods for programmed branch predictors

System and method for model-agnostic meta-learner for noisy data wi...

Implicit global pointer relative addressing for global memory access

Inserting predefined pad values into a stream of vectors

Processing instructions selected from a first instruction set in a...

Accelerating eight-way parallel Keccak execution

Systems, methods, and apparatuses for tile load, multiplication and...

Systems and methods for computing dot products of nibbles in two ti...

Concurrent multi-datatype execution within a processing resource

Re-use of speculative load instruction results from wrong path

Load-with-substitution instruction

Tracking streaming engine vector predicates to control processor ex...

Processor that executes instruction that specifies instruction conc...

Method for processing multiple transactions converted from single t...

Systems, methods, and apparatuses for tile matrix multiplication an...

SM3 hash algorithm acceleration processors, methods, systems, and i...

Systems, methods, and apparatuses for tile transpose

Scalar core integration

One-dimensional zero padding in a stream of matrix elements

Central processing unit with asynchronous registers

Memory interface

Data processing method and apparatus, and related product for incre...

Method and apparatus for vector permutation

Systems, methods, and apparatuses for matrix operations

Memory device with internal processing interface

Streaming address generation

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR DATA/INSTRUCTION ACCESS BASED ON PERFORMAN...

INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...

SCALAR CORE INTEGRATION

Parallel decoding method, processor, chip and electronic device

VECTOR SHUFFLING METHOD, PROCESSOR AND ELECTRONIC DEVICE

PADDING IN A STREAM OF MATRIX ELEMENTS

TECHNIQUES FOR CONTROLLING VECTOR PROCESSING OPERATIONS

SYSTEM AND METHOD FOR MODEL-AGNOSTIC META-LEARNER FOR NOISY DATA WI...

METHODS AND SYSTEMS FOR INTER-PIPELINE DATA HAZARD AVOIDANCE

STREAMING ADDRESS GENERATION

METHOD AND APPARATUS FOR DECOMPRESSION HARDWARE COPY ENGINE WITH EF...

SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD

CONDITIONAL BRANCH INSTRUCTIONS FOR AGGREGATING CONDITIONAL BRANCH...

METHOD AND APPARATUS FOR VECTOR PERMUTATION

MEMORY DEVICE WITH INTERNAL PROCESSING INTERFACE

CACHE CONTROL CIRCUIT WITH FETCH HYSTERESIS

PROCESSOR ARCHITECTURE WITH MEMORY ACCESS CIRCUIT

VARIABLE LATENCY INSTRUCTIONS

LOOK-UP TABLE READ

DUAL DATA STREAMS SHARING DUAL CACHE ACCESS PORTS

Processor having Switch Instruction Circuit

MEMORY INTERFACE

CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE

METHOD AND APPARATUS FOR PERMUTING STREAMED DATA ELEMENTS

STREAMING ENGINE WITH CACHE-LIKE STREAM DATA STORAGE AND LIFETIME T...

TWO-DIMENSIONAL ZERO PADDING IN A STREAM OF MATRIX ELEMENTS

Systems and Methods Providing Pause for Interrupts and Shared Memor...

A DATA PROCESSING APPARATUS AND METHOD FOR TRANSMITTING TRIGGERED I...

STORAGE ORGANIZATION FOR TRANSPOSING A MATRIX USING A STREAMING ENGINE

METHODS, APPARATUS, AND ARTICLES OF MANUFACTURE TO ALIGN DATA TO AD...