Patent Application
20250068424
Large workloads involve substantial data movement challenges. The ability of a computer processor to effectively control how the data is stored, preprocessed, and prefetched into its cache hierarchy is important in solving these data movement challenges. One typical way of assigning characteristics to data is to add special tags to the page table of the page where the data is stored. This allows data types to be characterized at a page level granularity. The usefulness of this approach is limited by the difficulty in updating the page table, the coarseness of characterizing data in this manner (especially with the use of huge pages), and the overall lack of flexibility.
Alternatively, a program may be allowed to specify special performance related characteristics of the data as the data is being loaded or stored by the processor. The more flexible and portable approach may be achieved by adding new instructions for each, or for each combination, of the special characteristics that the program wants to associate with the handling of the data. Yet it is expensive to add additional instructions to the instruction set of the processor's instruction set (often referred to as Instruction Set Architecture (ISA)) due to the limited number of available instruction bits, and the addition of new instructions can touch a significant portion of the processor's decode logic, require assembler and other software for the new instructions, increase the processor hardware validation requirements, and create significant ongoing support requirements. In the fast-changing world of compute requirements, the complexity of the adding instructions to a processor limits the ability of the processor to be rapidly innovated to address new requirements.
The disclosure may best be understood by referring to the following description and accompanying drawings that are used to show embodiments of the disclosure.
In the following description, numerous specific details are set forth. However, it is understood that embodiments of the disclosure may be practiced without these specific details. In other instances, well-known circuits, structures, and techniques have not been shown in detail in order not to obscure the understanding of this description.
Bracketed text and blocks with dashed borders (such as large dashes, small dashes, dot-dash, and dots) may be used to illustrate optional operations that add additional features to the embodiments of the disclosure. Such notation, however, should not be taken to mean that these are the only options or optional operations, and/or that blocks with solid borders are not optional in some embodiments of the disclosure.
References in the specification to “one embodiment,” “an embodiment,” “an example embodiment,” etc. indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.
The term “connected” means a direct electrical or magnetic connection between the things that are connected, without any intermediary devices, while the term of “coupled” means either a direct electrical or magnetic connection between the things that are connected or an indirect connection through one or more passive or active intermediary devices. The term “circuit” means one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function. The terms “computing system,” “compute system,” “computer system,” and “computer” are used interchangeably herein. The term “set” means any positive whole number of items including one item.
Embodiments herein provide ways to portably add new instruction level software-controlled performance hints to a computer processor with a minimum impact on the processor's instruction decode pipeline. These performance hints can be easily and quickly targeted at new emerging compute data movement challenges without requiring a new revision of the overall processor hardware implementation.
One set of embodiments adds an immediate field to instructions to provide extra information relating to performance. The instructions include ones for data and instruction access, such as load, store, or prefetch. In some embodiments, the immediate field would not be part of the formal instruction mnemonic of an instruction. Instead, these bits would enable extra information relating to performance to be associated with the instruction. An intermediate field of 8 to 16 bits (or another bit width) would provide sufficient flexibility to allow prefetch, load, and store instructions to include extra performance-based information. These immediate bits could be partially unassigned during the processor core design and could be further specified later in the development cycle. This first set of embodiments may be referred to as an immediate-bit-based approach.
Another set of embodiments provides for associating performance-based configuration bits with the individual registers of the processor. One simple way would be to architect the processor to assume these bits are static and not directly associated with the processor pipeline. Instead, the bits would just be presented with the instruction to the unit that consumes or sources the associated register value. A more advanced architecture would sample the bits at instruction decode time and pipe the bits forward along with the other characteristics of the instruction. For instructions that utilize multiple registers, the number of performance bits grows linearly with the number of registers specified, and the added bits allow greater flexibility to add more performance information. This second set of embodiments may be referred to as a register-based approach. This approach may also allow supplying the 8 to 16 bits (or another bit width) as previously discussed with the immediate-bit-based approach, that offers sufficient flexibility to provide extra performance-based information to prefetch, load, and store instruction. That is, the two sets of embodiments may be used together to provide ample flexibility to provide better performance to the processor pipeline. The registers that may be used in this approach are discussed in further detail relating to
The extra information and/or configuration bits relating to performance (collectively referred to as performance information) is configurable to a specific instruction, and it may include a variety of information about one or more of the following: which cache level is appropriate to store or load the data into, the level of sharing of the data, how the data should be shared among cores, weak or strong data ordering, how the data should interact with the hardware prefetchers, the prefetch priority, where to store the data in the cache, the amount of data to prefetch, and any required data transformations. The performance information may relate to the priority of the data, including the replacement priority/eviction treatment, the level of cache, temporal/spatial locality, data/instruction criticality. For example, the eviction treatment (also referred to as eviction or replacement policy) specifies which data should be replaced from a cache when the cache becomes full to make room for new data, and the performance information corresponding to an instruction per some embodiments may indicate configured eviction treatment. The performance information may indicate prohibition of certain behaviors, including that ordering is not enforced, data item or instructions (or code) not to be placed in a certain level of cache (e.g., L1 instruction cache or data cache). The performance information may be referred to as metadata associated with corresponding data load, store, or prefetch.
Note that the performance information is discussed herein using performance hints as examples, where “hint” designates that a processor is not bound by the performance information but may use the information to optimize the processor's performance. The performance information may also be referred to as performance indication, directive, annotation, signal, request, recommendation, cue, tip, or similar terms for processors produced by different manufacturers.
When a user wants to update the processor to allow software to control how certain data/instruction is loaded into a cache or stored from the cache to memory, a new instruction format could be defined and implemented in the processor hardware. Support for this instruction would be added to the user software compiler tool chain. After this, the user could change their code to utilize this instruction when they want to load data in the prescribed manner. Performance based bits make this much simpler. Using either or both of the two approaches disclosed herein, one may define and use the performance-based register configuration bits and/or performance-based intermediate, and the definition may be revised in the production cycle from the initial processor design to later maintenance and updates. Additionally, new values of these bits may be defined and used later to further control how the data/instruction is to be accessed. The abstract of the instruction format definition to later realization with specificity of instruction, with the mapping immediate bits and/or registers, allow embodiments disclosed herein provide flexibility and scalability not practicable in earlier approaches, e.g., tagging the page tables and adding new instructions for performance hints.
For the immediate-bit-based approach, the user could just set one or more immediate bits in the appropriate instruction. For the register-based approach, the user would just set the bits for a particular register and then use this specific register as the destination for the data load, or the source of the data store. The configuration bits associated with the registers would indicate that the data load or store should proceed with the configured characteristics. These approaches do not require any extra state to be kept in the core or the caches to remember the hint bits supplied.
Additionally or alternatively, implementing the register-based approach is illustrated in
The performance hints obtained based on the immediate bits or registers may be propagated through the execution pipeline and used after the decoding. For example, the performance hints may be used in the execution engine unit 750 (e.g., in its interaction with memory unit 770) of a processor, as shown in
The processor that decodes the performance hints may be one of a variety of processors, including xPUs, matrix math units, accelerators, or other processing units. The xPUs may be central processing units (CPUs), graphics processing units (GPUs), tensor processing units (TPUs), infrastructure processing units (IPUs), edge processing units (EPUs), or data processing units (DPUs), or other processing units. The performance hints may be decoded by any of the processors, and the performance information obtained may be passed along from a processor to be used outside of the processor that decodes the performance hints.
For example, the performance hints decoded by a CPU may be passed from the CPU to an accelerator or another xPU. The performance hints may be passed using any interconnect between different stages of an execution pipeline or different processors, including PCI (Peripheral Component Interconnect) based protocols (e.g., PCI-Express), or any other bus or point-to-point communication interfaces and/or protocol(s), such as the NVLink high-speed interconnect, Compute Express Link™ (CXL™) (e.g., CXL.mem), Infinity Fabric (IF), Ethernet (IEEE 802.3), remote direct memory access (RDMA), InfiniBand, Internet Wide Area RDMA Protocol (iWARP), Transmission Control Protocol (TCP), User Datagram Protocol (UDP), quick UDP Internet Connections (QUIC), RDMA over Converged Ethernet (RoCE), Intel QuickPath Interconnect (QPI), Intel Ultra Path Interconnect (UPI), Intel On-Chip System Fabric (IOSF), Universal Chiplet Interconnect Express (UCIe), Omnipath, HyperTransport, Advanced Microcontroller Bus Architecture (AMBA) interconnect, OpenCAPI, Gen-Z, Cache Coherent Interconnect for Accelerators (CCIX), 3GPP Long Term Evolution (LTE) (4G), 3GPP 5G, and variations thereof, or wired or wireless interconnect protocols known in the art.
The performance hints provided through decoding an instruction with a set of configurable performance hints allow a processor to process large workloads much more efficiently. The large workloads are prevalent in applications such as artificial intelligence (AI) and machine learning (ML). The AI/ML workloads include (1) training workloads such as model training (e.g., large language models (LLMs) or retrieval-augmented generation (RAG)), hyperparameter tuning, transfer learning, and distributed training; (2) inference workloads such as real-time inference, batch inference, edge inference; (3) data processing workloads such as data preprocessing, data labeling, Extract, Transform, Load (ETL), and other data analytics; (4) model evaluation and validation workloads including model testing, cross-validation, A/B testing; (5) deployment workloads including model serving using machine learning algorithms, continuous integration and deployment (CI/CD) pipelines tailored for machine learning, and model monitoring including models using neural networks, Bayesian networks, and decision trees; (6) optimization workloads including model compression, quantization, pruning.
Additionally, the performance hints may be biased through a model. For example, an inference engine in a ML model may use hints passed along a neural network to configure/optimize inference.
Adding the register-based performance hints does not directly affect the instruction set architecture (ISA) of the processor as would happen when adding the immediate-bit-based performance hints. The ISA can be modified to move the performance hints from register-based to immediate-bit-based. Due to software compatibility constraints, it is typically more difficult to shrink the ISA than to grow it, but in certain cases it might be appropriate to move configuration and performance hints from immediate-bit-based to register-based.
For each full implementation of the processor, extra register-based hint bits could be implemented and reserved for future use. This would allow features to be added to the processor with minimal changes to an existing processor implementation.
The use of register-based hint bits reduces the impact (often referred to as the “blast radius”) of the hardware changes needed to add certain types of performance or configuration features to the processor hardware. However, it does potentially have a larger required software impact than expanding the processor ISA. Expanding the ISA has no impact to the user of the processor who does not use these expanded ISA features. However, the added register-based hint bits add to the state for the processor, so these hint bits, even when not being used, need to be saved and restored on a context switch. Context switch is a process in a processor where a core switches from executing one thread to another so that the threads may share resources of the processor effectively. Context switch is also referred to as context switching, thread swap, thread swap event, thread context swap, state swap, or similar terms. Context switch includes save and restore operations, where (1) the current state of the running thread on a core is saved, (2) the saved state of the next thread to be executed is then loaded on the core, and (3) the core executes the next thread from the saved state.
The added context overhead of the register-based hint bits is small compared to the overall size of the context state. Extra register-base hint bit state space could pre-emptively be added to the processor context state to allow the register-base hint bit state to be modified without changing the defined overall processor content state. Different types of encoding can be utilized for the register-based hint bits. Not every register needs to be allowed to have every hint bit associated with it. The hint bit encoding could limit certain hint bits to certain register subsets or could even be encoded to allow only a certain number of registers to have a certain hint associated with them by encoding both the register-id and the hint in the hint-bit context state.
In some embodiments, a partial virtualization is implemented, where the state of the added register-based hint bits is not saved or saved with delay during a context switch. The delayed state save would save the state of the added register-based hint bits a time later than the context switch. The delayed state save allows the core of the processor and the operating system/application implementing the performance hints to only virtualize the registers including the performance hint bits during a thread swap when the thread swapping in (“destination thread”), rather than the thread swapping out (“source thread”), needs to use the registers.
In the register-based approach, the one or more registers that include the performance hints may be identified in a variety of ways. A register with performance hints may be one that is already indicated in a data access instruction, e.g., the destination register for the data load, or the source register of the data store. The register with performance hints may be indicated by one or more immediate bits. The immediate bits may directly indicate the performance hints, and additionally/alternatively they may also indicate from which registers the performance hints are to be obtained. In some embodiments, the immediate bits may be separated into two subsets, one for the former, the direct indication of performance hints, and the other for the latter, identifying the registers with performance hints. The register with performance hints may be mapped for a specific operation implicitly, e.g., the register being not specifically defined to be a specific one or more registers for a set of data/instruction access instructions. The register with performance hints may be specified with opcode, e.g., register specifiers in fields such as (1) field to specify the addressing mode, the register involved, and whether the operand is in memory or a register (referred to as Mod-Register-Memory (ModRM)), (2) field to identify address calculation using scale-index-base (SIB) bytes when the addressing mode requires additional flexibility for addressing memory, allowing for complex addressing calculations, and (3) vector extension in the encoding of SIMD processing to extend the instruction set to support additional registers (VEX.vvv). Further details of these fields are discussed relating to
The pre-allocation may occur at the processor core design, and the instruction meaning may be defined and/or further expanded by specifying different immediate bits later in the development cycle. Such multi-phases design of the instruction format reduces software/hardware effort of introducing new types of instructions by allocating and implementing the needed space for the full immediate field at once, and then define/refine the meaning of the immediate values later.
These different performance hints can be configured to the same instruction to cause different data/instruction access behavior of a processor thus making the processor operate more efficiently.
At reference 602, an instruction is decoded to access data or code by a core of a computer processor, the instruction to provide one or more hints on how the data or code is to be processed through a cache hierarchy of the computer processor based on the instruction, the one or more hints indicating which level of the cache hierarchy or which cache in a level of the cache hierarchy to load or store the data or code, a priority of the data or code in a cache, or how the data or code is to be shared among multiple cores of the computer processor. At reference 604, the data or code is processed based on the one or more hints responsive to the decoded instruction.
In some embodiments, the one or more hints are selected from a plurality of hints configurable for the instruction. An example of the hint selection is shown in
In some embodiments, the one or more hints is indicated by one or more immediate bits of the instruction. In some embodiments, the one or more immediate bits of the instruction indicates one or more registers from which the one or more hints is to be obtained.
In some embodiments, the one more hints are indicated by one or more bits of one or more registers accessible by the core upon decoding the instruction.
In some embodiments, the one or more bits of the one or more registers is read during decoding the instruction and the one or more bits are passed along in a processor pipeline for executing the instruction to provide further hint on how the data or code is to be processed through the cache hierarchy.
In some embodiments, the one or more registers comprises a source register from which the data or code is stored, or a destination register to which the data or code is loaded, wherein a source or destination register is indicated in the instruction, and wherein the one or more bits in the source register or destination register indicates the one or more hints on how the data or code is to be stored or loaded, respectively.
In some embodiments, upon context switching, a state of the one or more registers is to be stored as a part of state of a thread switching out of the core.
In some embodiments, the instruction is to load the data or code to the core, store the data or code from the core, or prefetch the data or code to the core.
In some embodiments, the one or more hints further indicate one or more of the following: how the data or code is to be ordered, how the data or code is to be transformed upon accessing, an eviction treatment to specify how the data or code is to be replaced, or how the data or code is to interact with a prefetcher of the computer processor, how the data or code is to be prefetched, or a priority of the data or code in prefetching.
In some embodiments, the core of the computer processor comprises a core of a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit, a tensor processing unit, or a matrix math unit.
Embodiments of the instruction(s) described herein may be embodied in different formats. Additionally, exemplary systems, architectures, and pipelines are detailed below. Embodiments of the instruction(s) may be executed on such systems, architectures, and pipelines, but are not limited to those detailed.
A vector friendly instruction format is an instruction format that is suited for vector instructions (e.g., there are certain fields specific to vector operations). While embodiments are described in which both vector and scalar operations are supported through the vector friendly instruction format, alternative embodiments use only vector operations the vector friendly instruction format.
While embodiments will be described in which the vector friendly instruction format supports the following: a 64 byte vector operand length (or size) with 32 bit (4 byte) or 64 bit (8 byte) data element widths (or sizes) (and thus, a 64 byte vector consists of either 16 doubleword-size elements or alternatively, 8 quadword-size elements); a 64 byte vector operand length (or size) with 16 bit (2 byte) or 8 bit (1 byte) data element widths (or sizes); a 32 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); and a 16 byte vector operand length (or size) with 32 bit (4 byte), 64 bit (8 byte), 16 bit (2 byte), or 8 bit (1 byte) data element widths (or sizes); alternative embodiments may support more, less and/or different vector operand sizes (e.g., 256 byte vector operands) with more, less, or different data element widths (e.g., 128 bit (16 byte) data element widths).
The class A instruction templates in
The generic vector friendly instruction format 800 includes the following fields listed below in the order shown in
Format field 840—a specific value (an instruction format identifier value) in this field uniquely identifies the vector friendly instruction format, and thus occurrences of instructions in the vector friendly instruction format in instruction streams. As such, this field is optional in the sense that it is not needed for an instruction set that has only the generic vector friendly instruction format.
Base operation field 842—its content distinguishes different base operations.
Register index field 844—its content, directly or through address generation, specifies the locations of the source and destination operands, be they in registers or in memory. These include a sufficient number of bits to select N registers from a P×Q (e.g. 32×512, 16×128, 32×1024, 64×1024) register file. While in one embodiment N may be up to three sources and one destination register, alternative embodiments may support more or less sources and destination registers (e.g., may support up to two sources where one of these sources also acts as the destination, may support up to three sources where one of these sources also acts as the destination, may support up to two sources and one destination).
Modifier field 846—its content distinguishes occurrences of instructions in the generic vector instruction format that specify memory access from those that do not; that is, between no memory access 805 instruction templates and memory access 820 instruction templates. Memory access operations read and/or write to the memory hierarchy (in some cases specifying the source and/or destination addresses using values in registers), while non-memory access operations do not (e.g., the source and destinations are registers). While in one embodiment this field also selects between three different ways to perform memory address calculations, alternative embodiments may support more, less, or different ways to perform memory address calculations.
Augmentation operation field 850—its content distinguishes which one of a variety of different operations to be performed in addition to the base operation. This field is context specific. In one embodiment, this field is divided into a class field 868, an alpha field 852, and a beta field 854. The augmentation operation field 850 allows common groups of operations to be performed in a single instruction rather than 2, 3, or 4 instructions.
Scale field 860—its content allows for the scaling of the index field's content for memory address generation (e.g., for address generation that uses 2scale*index+base).
Displacement Field 862A—its content is used as part of memory address generation (e.g., for address generation that uses 2scale*index+base+displacement).
Displacement Factor Field 862B (note that the juxtaposition of displacement field 862A directly over displacement factor field 862B indicates one or the other is used)—its content is used as part of address generation; it specifies a displacement factor that is to be scaled by the size of a memory access (N)—where N is the number of bytes in the memory access (e.g., for address generation that uses 2scale*index+base+scaled displacement). Redundant low-order bits are ignored and hence, the displacement factor field's content is multiplied by the memory operands total size (N) in order to generate the final displacement to be used in calculating an effective address. The value of N is determined by the processor hardware at runtime based on the full opcode field 874 (described herein) and the data manipulation field 854C. The displacement field 862A and the displacement factor field 862B are optional in the sense that they are not used for the no memory access 805 instruction templates and/or different embodiments may implement only one or none of the two.
Data element width field 864—its content distinguishes which one of a number of data element widths is to be used (in some embodiments for all instructions; in other embodiments for only some of the instructions). This field is optional in the sense that it is not needed if only one data element width is supported and/or data element widths are supported using some aspect of the opcodes.
Write mask field 870—its content controls, on a per data element position basis, whether that data element position in the destination vector operand reflects the result of the base operation and augmentation operation. Class A instruction templates support merging-writemasking, while class B instruction templates support both merging- and zeroing-writemasking. When merging, vector masks allow any set of elements in the destination to be protected from updates during the execution of any operation (specified by the base operation and the augmentation operation); in other one embodiment, preserving the old value of each element of the destination where the corresponding mask bit has a 0. In contrast, when zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation (specified by the base operation and the augmentation operation); in one embodiment, an element of the destination is set to 0 when the corresponding mask bit has a 0 value. A subset of this functionality is the ability to control the vector length of the operation being performed (that is, the span of elements being modified, from the first to the last one); however, it is not necessary that the elements that are modified be consecutive. Thus, the write mask field 870 allows for partial vector operations, including loads, stores, arithmetic, logical, etc. While embodiments are described in which the write mask field's 870 content selects one of a number of write mask registers that contains the write mask to be used (and thus the write mask field's 870 content indirectly identifies that masking to be performed), alternative embodiments instead or additional allow the mask write field's 870 content to directly specify the masking to be performed.
Immediate field 872—its content allows for the specification of an immediate. This field is optional in the sense that is it not present in an implementation of the generic vector friendly format that does not support immediate and it is not present in instructions that do not use an immediate.
Class field 868—its content distinguishes between different classes of instructions. With reference to
In the case of the no memory access 805 instruction templates of class A, the alpha field 852 is interpreted as an RS field 852A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round 852A.1 and data transform 852A.2 are respectively specified for the no memory access, round type operation 810 and the no memory access, data transform type operation 815 instruction templates), while the beta field 854 distinguishes which of the operations of the specified type is to be performed. In the no memory access 805 instruction templates, the scale field 860, the displacement field 862A, and the displacement factor filed 862B (sometimes referred to as displacement scale field) are not present.
In the no memory access full round control type operation 810 instruction template, the beta field 854 is interpreted as a round control field 854A, whose content(s) provide static rounding. While in the described embodiments the round control field 854A includes a suppress all floating point exceptions (SAE) field 856 and a round operation control field 858, alternative embodiments may support may encode both these concepts into the same field or only have one or the other of these concepts/fields (e.g., may have only the round operation control field 858).
SAE field 856—its content distinguishes whether or not to disable the exception event reporting; when the SAE field's 856 content indicates suppression is enabled, a given instruction does not report any kind of floating-point exception flag and does not raise any floating point exception handler.
Round operation control field 858—its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field 858 allows for the changing of the rounding mode on a per instruction basis. In one embodiment where a processor includes a control register for specifying rounding modes, the round operation control field's 858 content overrides that register value.
In the no memory access data transform type operation 815 instruction template, the beta field 854 is interpreted as a data transform field 854B, whose content distinguishes which one of a number of data transforms is to be performed (e.g., no data transform, swizzle, broadcast).
In the case of a memory access 820 instruction template of class A, the alpha field 852 is interpreted as an eviction hint field 852B, whose content distinguishes which one of the eviction hints is to be used (in
Vector memory instructions perform vector loads from and vector stores to memory, with conversion support. As with regular vector instructions, vector memory instructions transfer data from/to memory in a data element-wise fashion, with the elements that are actually transferred is dictated by the contents of the vector mask that is selected as the write mask.
Temporal data is data likely to be reused soon enough to benefit from caching. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely.
Non-temporal data is data unlikely to be reused soon enough to benefit from caching in the 1st-level cache and should be given priority for eviction. This is, however, a hint, and different processors may implement it in different ways, including ignoring the hint entirely.
In the case of the instruction templates of class B, the alpha field 852 is interpreted as a write mask control (Z) field 852C, whose content distinguishes whether the write masking controlled by the write mask field 870 should be a merging or a zeroing.
In the case of the no memory access 805 instruction templates of class B, part of the beta field 854 is interpreted as an RL field 857A, whose content distinguishes which one of the different augmentation operation types are to be performed (e.g., round 857A.1 and vector length (VSIZE) 857A.2 are respectively specified for the no memory access, write mask control, partial round control type operation 812 instruction template and the no memory access, write mask control, VSIZE type operation 817 instruction template), while the rest of the beta field 854 distinguishes which of the operations of the specified type is to be performed. In the no memory access 805 instruction templates, the scale field 860, the displacement field 862A, and the displacement factor filed 862B are not present.
In the no memory access, write mask control, partial round control type operation 810 instruction template, the rest of the beta field 854 is interpreted as a round operation field 859A and exception event reporting is disabled (a given instruction does not report any kind of floating-point exception flag and does not raise any floating-point exception handler).
Round operation control field 859A—just as round operation control field 858, its content distinguishes which one of a group of rounding operations to perform (e.g., Round-up, Round-down, Round-towards-zero and Round-to-nearest). Thus, the round operation control field 859A allows for the changing of the rounding mode on a per instruction basis. In one embodiment where a processor includes a control register for specifying rounding modes, the round operation control field's 859 content overrides that register value.
In the no memory access, write mask control, VSIZE type operation 817 instruction template, the rest of the beta field 854 is interpreted as a vector length field 859B, whose content distinguishes which one of a number of data vector lengths is to be performed on (e.g., 128, 256, or 512 byte).
In the case of a memory access 820 instruction template of class B, part of the beta field 854 is interpreted as a broadcast field 857B, whose content distinguishes whether or not the broadcast type data manipulation operation is to be performed, while the rest of the beta field 854 is interpreted the vector length field 859B. The memory access 820 instruction templates include the scale field 860, and optionally the displacement field 862A or the displacement scale field 862B.
With regard to the generic vector friendly instruction format 800, a full opcode field 874 is shown including the format field 840, the base operation field 842, and the data element width field 864. While one embodiment is shown where the full opcode field 874 includes all of these fields, the full opcode field 874 includes less than all of these fields in embodiments that do not support all of them. The full opcode field 874 provides the operation code (opcode).
The augmentation operation field 850, the data element width field 864, and the write mask field 870 allow these features to be specified on a per instruction basis in the generic vector friendly instruction format.
The combination of write mask field and data element width field create typed instructions in that they allow the mask to be applied based on different data element widths.
The various instruction templates found within class A and class B are beneficial in different situations. In some embodiments, different processors or different cores within a processor may support only class A, only class B, or both classes. For instance, a high performance general purpose out-of-order core intended for general-purpose computing may support only class B, a core intended primarily for graphics and/or scientific (throughput) computing may support only class A, and a core intended for both may support both (of course, a core that has some mix of templates and instructions from both classes but not all templates and instructions from both classes is within the purview of the disclosure). Also, a single processor may include multiple cores, all of which support the same class or in which different cores support different class. For instance, in a processor with separate graphics and general-purpose cores, one of the graphics cores intended primarily for graphics and/or scientific computing may support only class A, while one or more of the general purpose cores may be high performance general purpose cores with out of order execution and register renaming intended for general-purpose computing that support only class B. Another processor that does not have a separate graphics core, may include one more general purpose in-order or out-of-order cores that support both class A and class B. Of course, features from one class may also be implement in the other class in different embodiments. Programs written in a high-level language would be put (e.g., just in time compiled or statically compiled) into an variety of different executable forms, including: 1) a form having only instructions of the class(es) supported by the target processor for execution; or 2) a form having alternative routines written using different combinations of the instructions of all classes and having control flow code that selects the routines to execute based on the instructions supported by the processor which is currently executing the code.
It should be understood that, although embodiments are described with reference to the specific vector friendly instruction format 900 in the context of the generic vector friendly instruction format 800 for illustrative purposes, the disclosure is not limited to the specific vector friendly instruction format 900 except where claimed. For example, the generic vector friendly instruction format 800 contemplates a variety of possible sizes for the various fields, while the specific vector friendly instruction format 900 is shown as having fields of specific sizes. By way of specific example, while the data element width field 864 is shown as a one-bit field in the specific vector friendly instruction format 900, the disclosure is not so limited (that is, the generic vector friendly instruction format 800 contemplates other sizes of the data element width field 864).
The generic vector friendly instruction format 800 includes the following fields listed below in the order shown in
EVEX Prefix (Bytes 0-3) 902—is encoded in a four-byte form.
Format Field 840 (EVEX Byte 0, bits [7:0])—the first byte (EVEX Byte 0) is the format field 840 and it contains 0x62 (the unique value used for distinguishing the vector friendly instruction format in one embodiment).
The second-fourth bytes (EVEX Bytes 1-3) include a number of bit fields providing specific capability.
REX field 905 (EVEX Byte 1, bits [7-5])—consists of a EVEX.R bit field (EVEX Byte 1, bit [7]—R), EVEX.X bit field (EVEX byte 1, bit [6]—X), and 1157BEX byte 1, bit [5]—B). The EVEX.R, EVEX.X, and EVEX.B bit fields provide the same functionality as the corresponding VEX bit fields, and are encoded using 1s complement form, i.e. ZMM0 is encoded as 1111B, ZMM15 is encoded as 0000B. Other fields of the instructions encode the lower three bits of the register indexes as is known in the art (rrr, xxx, and bbb), so that Rrrr, Xxxx, and Bbbb may be formed by adding EVEX.R, EVEX.X, and EVEX.B.
REX′ field 910—this is the first part of the REX′ field 910 and is the EVEX.R′ bit field (EVEX Byte 1, bit [4]—R′) that is used to encode either the upper 16 or lower 16 of the extended 32 register set. In one embodiment, this bit, along with others as indicated below, is stored in bit inverted format to distinguish (in the well-known x86 32-bit mode) from the BOUND instruction, whose real opcode byte is 62, but does not accept in the MOD R/M field (described below) the value of 11 in the MOD field; alternative embodiments do not store this and the other indicated bits below in the inverted format. A value of 1 is used to encode the lower 16 registers. In other words, R′Rrrr is formed by combining EVEX.R′, EVEX.R, and the other RRR from other fields.
Opcode map field 915 (EVEX byte 1, bits [3:0]-mmmm)—its content encodes an implied leading opcode byte (0F, 0F 38, or 0F 3).
Data element width field 864 (EVEX byte 2, bit [7]—W)—is represented by the notation EVEX.W. EVEX.W is used to define the granularity (size) of the datatype (either 32-bit data elements or 64-bit data elements).
EVEX.vvvv 920 (EVEX Byte 2, bits [6:3]-vvvv)—the role of EVEX.vvvv may include the following: 1) EVEX.vvvv encodes the first source register operand, specified in inverted (1s complement) form and is valid for instructions with 2 or more source operands; 2) EVEX.vvvv encodes the destination register operand, specified in 1s complement form for certain vector shifts; or 3) EVEX.vvvv does not encode any operand, the field is reserved and should contain 1111b. Thus, EVEX.vvvv field 920 encodes the 4 low-order bits of the first source register specifier stored in inverted (Is complement) form. Depending on the instruction, an extra different EVEX bit field is used to extend the specifier size to 32 registers.
EVEX.U 868 Class field (EVEX byte 2, bit [2]-U)—If EVEX.U=0, it indicates class A or EVEX.U0; if EVEX.U=1, it indicates class B or EVEX.U1.
Prefix encoding field 925 (EVEX byte 2, bits [1:0]-pp)—provides additional bits for the base operation field. In addition to providing support for the legacy SSE instructions in the EVEX prefix format, this also has the benefit of compacting the SIMD prefix (rather than requiring a byte to express the SIMD prefix, the EVEX prefix requires only 2 bits). In one embodiment, to support legacy SSE instructions that use a SIMD prefix (66H, F2H, F3H) in both the legacy format and in the EVEX prefix format, these legacy SIMD prefixes are encoded into the SIMD prefix encoding field; and at runtime are expanded into the legacy SIMD prefix prior to being provided to the decoder's PLA (so the PLA can execute both the legacy and EVEX format of these legacy instructions without modification). Although newer instructions could use the EVEX prefix encoding field's content directly as an opcode extension, certain embodiments expand in a similar fashion for consistency but allow for different meanings to be specified by these legacy SIMD prefixes. An alternative embodiment may redesign the PLA to support the 2-bit SIMD prefix encodings, and thus not require the expansion.
Alpha field 852 (EVEX byte 3, bit [7]—EH; also known as EVEX.EH, EVEX.rs, EVEX.RL, EVEX.write mask control, and EVEX.N; also shown with α)—as previously described, this field is context specific.
Beta field 854 (EVEX byte 3, bits [6:4]-SSS, also known as EVEX.s2-0, EVEX.r2-0, EVEX.rr1, EVEX.LL0, EVEX.LLB; also shown with βββ)—as previously described, this field is context specific.
REX′ field 910—this is the remainder of the REX′ field and is the EVEX. V′ bit field (EVEX Byte 3, bit [3]—V′) that may be used to encode either the upper 16 or lower 16 of the extended 32 register set. This bit is stored in bit inverted format. A value of 1 is used to encode the lower 16 registers. In other words, V′VVVV is formed by combining EVEX.V′, EVEX.vvvv.
Write mask field 870 (EVEX byte 3, bits [2:0]-kkk)—its content specifies the index of a register in the write mask registers as previously described. In one embodiment, the specific value EVEX.kkk=000 has a special behavior implying no write mask is used for the particular instruction (this may be implemented in a variety of ways including the use of a write mask hardwired to all ones or hardware that bypasses the masking hardware).
Real Opcode Field 930 (Byte 4) is also known as the opcode byte. Part of the opcode is specified in this field.
MOD R/M Field 940 (Byte 5) includes MOD field 942, Reg field 944, and R/M field 946. As previously described, the MOD field's 942 content distinguishes between memory access and non-memory access operations. The role of Reg field 944 can be summarized to two situations: encoding either the destination register operand or a source register operand, or be treated as an opcode extension and not used to encode any instruction operand. The role of R/M field 946 may include the following: encoding the instruction operand that references a memory address, or encoding either the destination register operand or a source register operand.
Scale, Index, Base (SIB) Byte (Byte 6)—As previously described, the scale field's 850 content is used for memory address generation. SIB.xxx 954 and SIB.bbb 956—the contents of these fields have been previously referred to with regard to the register indexes Xxxx and Bbbb.
Displacement field 862A (Bytes 7-10)—when MOD field 942 contains 10, bytes 7-10 are the displacement field 862A, and it works the same as the legacy 32-bit displacement (disp32) and works at byte granularity.
Displacement factor field 862B (Byte 7)—when MOD field 942 contains 01, byte 7 is the displacement factor field 862B. The location of this field is that same as that of the legacy x86 instruction set 8-bit displacement (disp8), which works at byte granularity. Since disp8 is sign extended, it can only address between −128 and 127 bytes offsets; in terms of 64 byte cache lines, disp8 uses 8 bits that can be set to only four really useful values −128, −64, 0, and 64; since a greater range is often needed, disp32 is used; however, disp32 requires 4 bytes. In contrast to disp8 and disp32, the displacement factor field 862B is a reinterpretation of disp8; when using displacement factor field 862B, the actual displacement is determined by the content of the displacement factor field multiplied by the size of the memory operand access (N). This type of displacement is referred to as disp8*N. This reduces the average instruction length (a single byte of used for the displacement but with a much greater range). Such compressed displacement is based on the assumption that the effective displacement is multiple of the granularity of the memory access, and hence, the redundant low-order bits of the address offset do not need to be encoded. In other words, the displacement factor field 862B substitutes the legacy x86 instruction set 8-bit displacement. Thus, the displacement factor field 862B is encoded the same way as an x86 instruction set 8-bit displacement (so no changes in the ModRM/SIB encoding rules) with the only exception that disp8 is overloaded to disp8*N. In other words, there are no changes in the encoding rules or encoding lengths but only in the interpretation of the displacement value by hardware (which needs to scale the displacement by the size of the memory operand to obtain a byte-wise address offset).
Immediate field 872 operates as previously described.
When U=1, the alpha field 852 (EVEX byte 3, bit [7]—EH) is interpreted as the write mask control (Z) field 852C. When U=1 and the MOD field 942 contains 11 (signifying a no memory access operation), part of the beta field 854 (EVEX byte 3, bit [4]—S0) is interpreted as the RL field 857A; when it contains a 1 (round 857A.1) the rest of the beta field 854 (EVEX byte 3, bit [6-5]—S2-1) is interpreted as the round operation field 859A, while when the RL field 857A contains a 0 (VSIZE 857.A2) the rest of the beta field 854 (EVEX byte 3, bit [6-5]—S2-1) is interpreted as the vector length field 859B (EVEX byte 3, bit [6-5]—L1-0). When U=1 and the MOD field 942 contains 00, 01, or 10 (signifying a memory access operation), the beta field 854 (EVEX byte 3, bits [6:4]—SSS) is interpreted as the vector length field 859B (EVEX byte 3, bit [6-5]—L1-0) and the broadcast field 857B (EVEX byte 3, bit [4]—B).
Processors 1070 and 1080 are shown including integrated memory controller (IMC) circuitry 1072 and 1082, respectively. Processor 1070 also includes interface circuits 1076 and 1078; similarly, second processor 1080 includes interface circuits 1086 and 1088. Processors 1070, 1080 may exchange information via the interface 1050 using interface circuits 1078, 1088. IMCs 1072 and 1082 couple the processors 1070, 1080 to respective memories, namely a memory 1032 and a memory 1034, which may be portions of main memory locally attached to the respective processors.
Processors 1070, 1080 may each exchange information with a network interface (NW I/F) 1090 via individual interfaces 1052, 1054 using interface circuits 1076, 1094, 1086, 1098. The network interface 1090 (e.g., one or more of an interconnect, bus, mesh, and/or fabric, and in some examples is a chipset) may optionally exchange information with a coprocessor 1038 via an interface circuit 1092. In some examples, the coprocessor 1038 is a special-purpose processor, such as, for example, a high-throughput processor, a network or communication processor, compression engine, graphics processor, general purpose graphics processing unit (GPGPU), neural-network processing unit (NPU), embedded processor, or the like.
A shared cache (not shown) may be included in either processor 1070, 1080 or outside of both processors, yet connected with the processors via an interface such as P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.
Network interface 1090 may be coupled to a first interface 1016 via interface circuit 1096. In some examples, first interface 1016 may be an interface such as a Peripheral Component Interconnect Express (PCI) interconnect, a PCI Express (PCIe) interconnect, Compute Express Link (CXL), NVLink, HyperTransport, or another I/O interconnect. In some examples, first interface 1016 is coupled to a power control unit (PCU) 1017, which may include circuitry, software, and/or firmware to perform power management operations with regard to the processors 1070, 1080 and/or coprocessor 1038. PCU 1017 provides control information to a voltage regulator (not shown) to cause the voltage regulator to generate the appropriate regulated voltage. PCU 1017 also provides control information to control the operating voltage generated. In various examples, PCU 1017 may include a variety of power management logic units (circuitry) to perform hardware-based power management. Such power management may be wholly processor controlled (e.g., by various processor hardware, and which may be triggered by workload and/or power, thermal or other processor constraints) and/or the power management may be performed responsive to external sources (such as a platform or power management source or system software).
PCU 1017 is illustrated as being present as logic separate from the processor 1070 and/or processor 1080. In other cases, PCU 1017 may execute on a given one or more of cores (not shown) of processor 1070 or 1080. In some cases, PCU 1017 may be implemented as a microcontroller (dedicated or general-purpose) or other control logic configured to execute its own dedicated power management code, sometimes referred to as P-code. In yet other examples, power management operations to be performed by PCU 1017 may be implemented externally to a processor, such as by way of a separate power management integrated circuit (PMIC) or another component external to the processor. In yet other examples, power management operations to be performed by PCU 1017 may be implemented within BIOS or other system software.
Various I/O devices 1014 may be coupled to first interface 1016, along with a bus bridge 1018 which couples first interface 1016 to a second interface 1020. In some examples, one or more additional processor(s) 1015, such as coprocessors, high throughput many integrated core (MIC) processors, GPGPUs, accelerators (such as graphics accelerators or digital signal processing (DSP) units), field programmable gate arrays (FPGAs), or any other processor, are coupled to first interface 1016. In some examples, second interface 1020 may be a low pin count (LPC) interface. Various devices may be coupled to second interface 1020 including, for example, a keyboard and/or mouse 1022, communication devices 1027 and storage circuitry 1028. Storage circuitry 1028 may be one or more non-transitory machine-readable storage media as described below, such as a disk drive or other mass storage device which may include instructions/code and data 1030 and may implement a storage to provide instructions in some examples. Further, an audio I/O 1024 may be coupled to second interface 1020. Note that other architectures than the point-to-point architecture described above are possible. For example, instead of the point-to-point architecture, a system such as multiprocessor system 1000 may implement a multi-drop interface or other such architecture.
Processor cores may be implemented in different ways, for different purposes, and in different processors. For instance, implementations of such cores may include: 1) a general purpose in-order core intended for general-purpose computing; 2) a high-performance general purpose out-of-order core intended for general-purpose computing; 3) a special purpose core intended primarily for graphics and/or scientific (throughput) computing. Implementations of different processors may include: 1) a CPU including one or more general purpose in-order cores intended for general-purpose computing and/or one or more general purpose out-of-order cores intended for general-purpose computing; and 2) a coprocessor including one or more special purpose cores intended primarily for graphics and/or scientific (throughput) computing. Such different processors lead to different computer system architectures, which may include: 1) the coprocessor on a separate chip from the CPU; 2) the coprocessor on a separate die in the same package as a CPU; 3) the coprocessor on the same die as a CPU (in which case, such a coprocessor is sometimes referred to as special purpose logic, such as integrated graphics and/or scientific (throughput) logic, or as special purpose cores); and 4) a system on a chip (SoC) that may be included on the same die as the described CPU (sometimes referred to as the application core(s) or application processor(s)), the above described coprocessor, and additional functionality. Example core architectures are described next, followed by descriptions of example processors and computer architectures.
Thus, different implementations of the processor 1100 may include: 1) a CPU with the special purpose logic 1108 being integrated graphics and/or scientific (throughput) logic (which may include one or more cores, not shown), and the cores 1102(A)-(N) being one or more general purpose cores (e.g., general purpose in-order cores, general purpose out-of-order cores, or a combination of the two); 2) a coprocessor with the cores 1102(A)-(N) being a large number of special purpose cores intended primarily for graphics and/or scientific (throughput); and 3) a coprocessor with the cores 1102(A)-(N) being a large number of general purpose in-order cores. Thus, the processor 1100 may be a general-purpose processor, coprocessor or special-purpose processor, such as, for example, a network or communication processor, compression engine, graphics processor, GPGPU (general purpose graphics processing unit), a high throughput many integrated core (MIC) coprocessor (including 30 or more cores), embedded processor, or the like. The processor may be implemented on one or more chips. The processor 1100 may be a part of and/or may be implemented on one or more substrates using any of a number of process technologies, such as, for example, complementary metal oxide semiconductor (CMOS), bipolar CMOS (BiCMOS), P-type metal oxide semiconductor (PMOS), or N-type metal oxide semiconductor (NMOS).
A memory hierarchy includes one or more levels of cache unit(s) circuitry 1104(A)-(N) within the cores 1102(A)-(N), a set of one or more shared cache unit(s) circuitry 1106, and external memory (not shown) coupled to the set of integrated memory controller unit(s) circuitry 1114. The set of one or more shared cache unit(s) circuitry 1106 may include one or more mid-level caches, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, such as a last level cache (LLC), and/or combinations thereof. While in some examples interface network circuitry 1112 (e.g., a ring interconnect) interfaces the special purpose logic 1108 (e.g., integrated graphics logic), the set of shared cache unit(s) circuitry 1106, and the system agent unit circuitry 1110, alternative examples use any number of well-known techniques for interfacing such units. In some examples, coherency is maintained between one or more of the shared cache unit(s) circuitry 1106 and cores 1102(A)-(N). In some examples, interface controller units circuitry 1116 couple the cores 1102 to one or more other devices 1118 such as one or more I/O devices, storage, one or more communication devices (e.g., wireless networking, wired networking, etc.), etc.
In some examples, one or more of the cores 1102(A)-(N) are capable of multi-threading. The system agent unit circuitry 1110 includes those components coordinating and operating cores 1102(A)-(N). The system agent unit circuitry 1110 may include, for example, power control unit (PCU) circuitry and/or display unit circuitry (not shown). The PCU may be or may include logic and components needed for regulating the power state of the cores 1102(A)-(N) and/or the special purpose logic 1108 (e.g., integrated graphics logic). The display unit circuitry is for driving one or more externally connected displays.
The cores 1102(A)-(N) may be homogenous in terms of instruction set architecture (ISA). Alternatively, the cores 1102(A)-(N) may be heterogeneous in terms of ISA; that is, a subset of the cores 1102(A)-(N) may be capable of executing an ISA, while other cores may be capable of executing only a subset of that ISA or another ISA.
The processing subsystem 1201, for example, includes one or more parallel processor(s) 1212 coupled to memory hub 1205 via a bus or other communication link 1213. The communication link 1213 may be one of any number of standards-based communication link technologies or protocols, such as, but not limited to PCI Express, or may be a vendor specific communications interface or communications fabric. The one or more parallel processor(s) 1212 may form a computationally focused parallel or vector processing system that can include a large number of processing cores and/or processing clusters, such as a many integrated core (MIC) processor. For example, the one or more parallel processor(s) 1212 form a graphics processing subsystem that can output pixels to one of the one or more display device(s) 1210A coupled via the I/O hub 1207. The one or more parallel processor(s) 1212 can also include a display controller and display interface (not shown) to enable a direct connection to one or more display device(s) 1210B.
Within the I/O subsystem 1211, a system storage unit 1214 can connect to the I/O hub 1207 to provide a storage mechanism for the computing system 1200. An I/O switch 1216 can be used to provide an interface mechanism to enable connections between the I/O hub 1207 and other components, such as a network adapter 1218 and/or wireless network adapter 1219 that may be integrated into the platform, and various other devices that can be added via one or more add-in device(s) 1220. The add-in device(s) 1220 may also include, for example, one or more external graphics processor devices, graphics cards, and/or compute accelerators. The network adapter 1218 can be an Ethernet adapter or another wired network adapter. The wireless network adapter 1219 can include one or more of a Wi-Fi, Bluetooth, near field communication (NFC), or other network device that includes one or more wireless radios.
The computing system 1200 can include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, which may also be connected to the I/O hub 1207. Communication paths interconnecting the various components in
The one or more parallel processor(s) 1212 may incorporate circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitutes a graphics processing unit (GPU). Alternatively or additionally, the one or more parallel processor(s) 1212 can incorporate circuitry optimized for general purpose processing, while preserving the underlying computational architecture, described in greater detail herein. Components of the computing system 1200 may be integrated with one or more other system elements on a single integrated circuit. For example, the one or more parallel processor(s) 1212, memory hub 1205, processor(s) 1202, and I/O hub 1207 can be integrated into a system on chip (SoC) integrated circuit. Alternatively, the components of the computing system 1200 can be integrated into a single package to form a system in package (SIP) configuration. In some examples at least a portion of the components of the computing system 1200 can be integrated into a multi-chip module (MCM), which can be interconnected with other multi-chip modules into a modular computing system.
It will be appreciated that the computing system 1200 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 1202, and the number of parallel processor(s) 1212, may be modified as desired. For instance, system memory 1204 can be connected to the processor(s) 1202 directly rather than through a bridge, while other devices communicate with system memory 1204 via the memory hub 1205 and the processor(s) 1202. In other alternative topologies, the parallel processor(s) 1212 are connected to the I/O hub 1207 or directly to one of the one or more processor(s) 1202, rather than to the memory hub 1205. In other examples, the I/O hub 1207 and memory hub 1205 may be integrated into a single chip. It is also possible that two or more sets of processor(s) 1202 are attached via multiple sockets, which can couple with two or more instances of the parallel processor(s) 1212.
Some of the particular components shown herein are optional and may not be included in all implementations of the computing system 1200. For example, any number of add-in cards or peripherals may be supported, or some components may be eliminated. Furthermore, some architectures may use different terminology for components similar to those illustrated in
The parallel processor 1300 includes a parallel processing unit 1302. The parallel processing unit includes an I/O unit 1304 that enables communication with other devices, including other instances of the parallel processing unit 1302. The I/O unit 1304 may be directly connected to other devices. For instance, the I/O unit 1304 connects with other devices via the use of a hub or switch interface, such as memory hub 1305. The connections between the memory hub 1305 and the I/O unit 1304 form a communication link 1213. Within the parallel processing unit 1302, the I/O unit 1304 connects with a host interface 1306 and a memory crossbar 1316, where the host interface 1306 receives commands directed to performing processing operations and the memory crossbar 1316 receives commands directed to performing memory operations.
When the host interface 1306 receives a command buffer via the I/O unit 1304, the host interface 1306 can direct work operations to perform those commands to a front end 1308. In some examples the front end 1308 couples with a scheduler 1310, which is configured to distribute commands or other work items to a processing cluster array 1312. The scheduler 1310 ensures that the processing cluster array 1312 is properly configured and in a valid state before tasks are distributed to the processing clusters of the processing cluster array 1312. The scheduler 1310 may be implemented via firmware logic executing on a microcontroller. The microcontroller implemented scheduler 1310 is configurable to perform complex scheduling and work distribution operations at coarse and fine granularity, enabling rapid preemption and context switching of threads executing on the processing cluster array 1312. Preferably, the host software can prove workloads for scheduling on the processing cluster array 1312 via one of multiple graphics processing doorbells. In other examples, polling for new workloads or interrupts can be used to identify or indicate availability of work to perform. The workloads can then be automatically distributed across the processing cluster array 1312 by the scheduler 1310 logic within the scheduler microcontroller.
The processing cluster array 1312 can include up to “N” processing clusters (e.g., cluster 1314A, cluster 1314B, through cluster 1314N). Each cluster 1314A-1314N of the processing cluster array 1312 can execute a large number of concurrent threads. The scheduler 1310 can allocate work to the clusters 1314A-1314N of the processing cluster array 1312 using various scheduling and/or work distribution algorithms, which may vary depending on the workload arising for each type of program or computation. The scheduling can be handled dynamically by the scheduler 1310 or can be assisted in part by compiler logic during compilation of program logic configured for execution by the processing cluster array 1312. Optionally, different clusters 1314A-1314N of the processing cluster array 1312 can be allocated for processing different types of programs or for performing different types of computations.
The processing cluster array 1312 can be configured to perform various types of parallel processing operations. For example, the processing cluster array 1312 is configured to perform general-purpose parallel compute operations. For example, the processing cluster array 1312 can include logic to execute processing tasks including filtering of video and/or audio data, performing modeling operations, including physics operations, and performing data transformations.
The processing cluster array 1312 is configured to perform parallel graphics processing operations. In such examples in which the parallel processor 1300 is configured to perform graphics processing operations, the processing cluster array 1312 can include additional logic to support the execution of such graphics processing operations, including, but not limited to texture sampling logic to perform texture operations, as well as tessellation logic and other vertex processing logic. Additionally, the processing cluster array 1312 can be configured to execute graphics processing related shader programs such as, but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. The parallel processing unit 1302 can transfer data from system memory via the I/O unit 1304 for processing. During processing the transferred data can be stored to on-chip memory (e.g., parallel processor memory 1322) during processing, then written back to system memory.
In examples in which the parallel processing unit 1302 is used to perform graphics processing, the scheduler 1310 may be configured to divide the processing workload into approximately equal sized tasks, to better enable distribution of the graphics processing operations to multiple clusters 1314A-1314N of the processing cluster array 1312. In some of these examples, portions of the processing cluster array 1312 can be configured to perform different types of processing. For example, a first portion may be configured to perform vertex shading and topology generation, a second portion may be configured to perform tessellation and geometry shading, and a third portion may be configured to perform pixel shading or other screen space operations, to produce a rendered image for display. Intermediate data produced by one or more of the clusters 1314A-1314N may be stored in buffers to allow the intermediate data to be transmitted between clusters 1314A-1314N for further processing.
During operation, the processing cluster array 1312 can receive processing tasks to be executed via the scheduler 1310, which receives commands defining processing tasks from front end 1308. For graphics processing operations, processing tasks can include indices of data to be processed, e.g., surface (patch) data, primitive data, vertex data, and/or pixel data, as well as state parameters and commands defining how the data is to be processed (e.g., what program is to be executed). The scheduler 1310 may be configured to fetch the indices corresponding to the tasks or may receive the indices from the front end 1308. The front end 1308 can be configured to ensure the processing cluster array 1312 is configured to a valid state before the workload specified by incoming command buffers (e.g., batch-buffers, push buffers, etc.) is initiated.
Each of the one or more instances of the parallel processing unit 1302 can couple with parallel processor memory 1322. The parallel processor memory 1322 can be accessed via the memory crossbar 1316, which can receive memory requests from the processing cluster array 1312 as well as the I/O unit 1304. The memory crossbar 1316 can access the parallel processor memory 1322 via a memory interface 1318. The memory interface 1318 can include multiple partition units (e.g., partition unit 1320A, partition unit 1320B, through partition unit 1320N) that can each couple to a portion (e.g., memory unit) of parallel processor memory 1322. The number of partition units 1320A-1320N may be configured to be equal to the number of memory units, such that a first partition unit 1320A has a corresponding first memory unit 1324A, a second partition unit 1320B has a corresponding second memory unit 1324B, and an Nth partition unit 1320N has a corresponding Nth memory unit 1324N. In other examples, the number of partition units 1320A-1320N may not be equal to the number of memory devices.
The memory units 1324A-1324N can include various types of memory devices, including dynamic random-access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. Optionally, the memory units 1324A-1324N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Persons skilled in the art will appreciate that the specific implementation of the memory units 1324A-1324N can vary and can be selected from one of various conventional designs. Render targets, such as frame buffers or texture maps may be stored across the memory units 1324A-1324N, allowing partition units 1320A-1320N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 1322. In some examples, a local instance of the parallel processor memory 1322 may be excluded in favor of a unified memory design that utilizes system memory in conjunction with local cache memory.
Optionally, any one of the clusters 1314A-1314N of the processing cluster array 1312 has the ability to process data that will be written to any of the memory units 1324A-1324N within parallel processor memory 1322. The memory crossbar 1316 can be configured to transfer the output of each cluster 1314A-1314N to any partition unit 1320A-1320N or to another cluster 1314A-1314N, which can perform additional processing operations on the output. Each cluster 1314A-1314N can communicate with the memory interface 1318 through the memory crossbar 1316 to read from or write to various external memory devices. In one of the examples with the memory crossbar 1316 the memory crossbar 1316 has a connection to the memory interface 1318 to communicate with the I/O unit 1304, as well as a connection to a local instance of the parallel processor memory 1322, enabling the processing units within the different processing clusters 1314A-1314N to communicate with system memory or other memory that is not local to the parallel processing unit 1302. Generally, the memory crossbar 1316 may, for example, be able to use virtual channels to separate traffic streams between the clusters 1314A-1314N and the partition units 1320A-1320N.
While a single instance of the parallel processing unit 1302 is illustrated within the parallel processor 1300, any number of instances of the parallel processing unit 1302 can be included. For example, multiple instances of the parallel processing unit 1302 can be provided on a single add-in card, or multiple add-in cards can be interconnected. For example, the parallel processor 1300 can be an add-in device, such as add-in device 1220 of
In some examples, the parallel processing unit 1302 can be partitioned into multiple instances. Those multiple instances can be configured to execute workloads associated with different clients in an isolated manner, enabling a pre-determined quality of service to be provided for each client. For example, each cluster 1314A-1314N can be compartmentalized and isolated from other clusters, allowing the processing cluster array 1312 to be divided into multiple compute partitions or instances. In such configuration, workloads that are executed on an isolated partition are protected from faults or errors associated with a different workload that is executed on a different partition. The partition units 1320A-1320N can be configured to enable a dedicated and/or isolated path to memory for the clusters 1314A-1314N associated with the respective compute partitions. This datapath isolation enables the compute resources within a partition can communicate with one or more assigned memory units 1324A-1324N without being subjected to inference by the activities of other partitions.
In graphics applications, the ROP 1326 is a processing unit that performs raster operations such as stencil, z test, blending, and the like. The ROP 1326 then outputs processed graphics data that is stored in graphics memory. In some examples the ROP 1326 includes or couples with a CODEC 1327 that includes compression logic to compress depth or color data that is written to memory or the L2 cache 1321 and decompress depth or color data that is read from memory or the L2 cache 1321. The compression logic can be lossless compression logic that makes use of one or more of multiple compression algorithms. The type of compression that is performed by CODEC 1327 can vary based on the statistical characteristics of the data to be compressed. For example, in some examples, delta color compression is performed on depth and color data on a per-tile basis. In some examples, CODEC 1327 includes compression and decompression logic that can compress and decompress compute data associated with machine learning operations. CODEC 1327 can, for example, compress sparse matrix data for sparse machine learning operations. CODEC 1327 can also compress sparse matrix data that is encoded in a sparse matrix format (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compress sparse column (CSC), etc.) to generate compressed and encoded sparse matrix data. The compressed and encoded sparse matrix data can be decompressed and/or decoded before being processed by processing elements or the processing elements can be configured to consume compressed, encoded, or compressed and encoded data for processing.
ROP 1326 may be included within each processing cluster (e.g., cluster 1314A-1314N of
Operation of the processing cluster 1314 can be controlled via a pipeline manager 1332 that distributes processing tasks to SIMT parallel processors. The pipeline manager 1332 receives instructions from scheduler 1310 of
Each graphics multiprocessor 1334 within the processing cluster 1314 can include an identical set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). The functional execution logic can be configured in a pipelined manner in which new instructions can be issued before previous instructions are complete. The functional execution logic supports a variety of operations including integer and floating-point arithmetic, comparison operations, Boolean operations, bit-shifting, and computation of various algebraic functions. The same functional-unit hardware could be leveraged to perform different operations and any combination of functional units may be present.
The instructions transmitted to the processing cluster 1314 constitute a thread. A set of threads executing across the set of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread within a thread group can be assigned to a different processing engine within a graphics multiprocessor 1334. A thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 1334. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during cycles in which that thread group is being processed. A thread group may also include more threads than the number of processing engines within the graphics multiprocessor 1334. When the thread group includes more threads than the number of processing engines within the graphics multiprocessor 1334, processing can be performed over consecutive clock cycles. Optionally, multiple thread groups can be executed concurrently on graphics multiprocessor 1334.
The graphics multiprocessor 1334 may include an internal cache memory to perform load and store operations. Optionally, the graphics multiprocessor 1334 can forego an internal cache and use a cache memory (e.g., level 1 (L1) cache 1348) within the processing cluster 1314. Each graphics multiprocessor 1334 also has access to level 2 (L2) caches within the partition units (e.g., partition units 1320A-1320N of
Each processing cluster 1314 may include an MMU 1345 (memory management unit) that is configured to map virtual addresses into physical addresses. In other examples, one or more instances of the MMU 1345 may reside within the memory interface 1318 of
In graphics and computing applications, a processing cluster 1314 may be configured such that each graphics multiprocessor 1334 is coupled to a texture unit 1336 for performing texture mapping operations, e.g., determining texture sample positions, reading texture data, and filtering the texture data. Texture data is read from an internal texture L1 cache (not shown) or in some examples from the L1 cache within graphics multiprocessor 1334 and is fetched from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 1334 outputs processed tasks to the data crossbar 1340 to provide the processed task to another processing cluster 1314 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 1316. A preROP 1342 (pre-raster operations unit) is configured to receive data from graphics multiprocessor 1334, direct data to ROP units, which may be located with partition units as described herein (e.g., partition units 1320A-1320N of
It will be appreciated that the core architecture described herein is illustrative and that variations and modifications are possible. Any number of processing units, e.g., graphics multiprocessor 1334, texture units 1336, preROPs 1342, etc., may be included within a processing cluster 1314. Further, while only one processing cluster 1314 is shown, a parallel processing unit as described herein may include any number of instances of the processing cluster 1314. Optionally, each processing cluster 1314 can be configured to operate independently of other processing clusters 1314 using separate and distinct processing units, L1 caches, L2 caches, etc.
The instruction cache 1352 may receive a stream of instructions to execute from the pipeline manager 1332. The instructions are cached in the instruction cache 1352 and dispatched for execution by the instruction unit 1354. The instruction unit 1354 can dispatch instructions as thread groups (e.g., warps), with each thread of the thread group assigned to a different execution unit within GPGPU core 1362. An instruction can access any of a local, shared, or global address space by specifying an address within a unified address space. The address mapping unit 1356 can be used to translate addresses in the unified address space into a distinct memory address that can be accessed by the load/store units 1366.
The register file 1358 provides a set of registers for the functional units of the graphics multiprocessor 1334. The register file 1358 provides temporary storage for operands connected to the data paths of the functional units (e.g., GPGPU cores 1362, load/store units 1366) of the graphics multiprocessor 1334. The register file 1358 may be divided between each of the functional units such that each functional unit is allocated a dedicated portion of the register file 1358. For example, the register file 1358 may be divided between the different warps being executed by the graphics multiprocessor 1334.
The GPGPU cores 1362 can each include floating point units (FPUs) and/or integer arithmetic logic units (ALUs) that are used to execute instructions of the graphics multiprocessor 1334. In some implementations, the GPGPU cores 1362 can include hardware logic that may otherwise reside within the tensor and/or ray-tracing cores 1363. The GPGPU cores 1362 can be similar in architecture or can differ in architecture. For example and in some examples, a first portion of the GPGPU cores 1362 include a single precision FPU and an integer ALU while a second portion of the GPGPU cores include a double precision FPU. Optionally, the FPUs can implement the IEEE 754-2008 standard for floating point arithmetic or enable variable precision floating point arithmetic. The graphics multiprocessor 1334 can additionally include one or more fixed function or special function units to perform specific functions such as copy rectangle or pixel blending operations. One or more of the GPGPU cores can also include fixed or special function logic.
The GPGPU cores 1362 may include SIMD logic capable of performing a single instruction on multiple sets of data. Optionally, GPGPU cores 1362 can physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. The SIMD instructions for the GPGPU cores can be generated at compile time by a shader compiler or automatically generated when executing programs written and compiled for single program multiple data (SPMD) or SIMT architectures. Multiple threads of a program configured for the SIMT execution model can be executed via a single SIMD instruction. For example and in some examples, eight SIMT threads that perform the same or similar operations can be executed in parallel via a single SIMD8 logic unit.
The memory and cache interconnect 1368 is an interconnect network that connects each of the functional units of the graphics multiprocessor 1334 to the register file 1358 and to the shared memory 1370. For example, the memory and cache interconnect 1368 is a crossbar interconnect that allows the load/store unit 1366 to implement load and store operations between the shared memory 1370 and the register file 1358. The register file 1358 can operate at the same frequency as the GPGPU cores 1362, thus data transfer between the GPGPU cores 1362 and the register file 1358 is very low latency. The shared memory 1370 can be used to enable communication between threads that execute on the functional units within the graphics multiprocessor 1334. The cache memory 1372 can be used as a data cache for example, to cache texture data communicated between the functional units and the texture unit 1336. The shared memory 1370 can also be used as a program managed cached. The shared memory 1370 and the cache memory 1372 can couple with the data crossbar 1340 to enable communication with other components of the processing cluster. Threads executing on the GPGPU cores 1362 can programmatically store data within the shared memory in addition to the automatically cached data that is stored within the cache memory 1372.
The graphics multiprocessor 1425 of
The various components can communicate via an interconnect fabric 1427. The interconnect fabric 1427 may include one or more crossbar switches to enable communication between the various components of the graphics multiprocessor 1425. The interconnect fabric 1427 may be a separate, high-speed network fabric layer upon which each component of the graphics multiprocessor 1425 is stacked. The components of the graphics multiprocessor 1425 communicate with remote components via the interconnect fabric 1427. For example, the cores 1436A-1436B, 1437A-1437B, and 1438A-1438B can each communicate with shared memory 1446 via the interconnect fabric 1427. The interconnect fabric 1427 can arbitrate communication within the graphics multiprocessor 1425 to ensure a fair bandwidth allocation between components.
The graphics multiprocessor 1450 of
Persons skilled in the art will understand that the architecture described in
The parallel processor or GPGPU as described herein may be communicatively coupled to host/processor cores to accelerate graphics operations, machine-learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor/cores over a bus or other interconnect (e.g., a high-speed interconnect such as PCIe, NVLink, or other known protocols, standardized protocols, or proprietary protocols). In other examples, the GPU may be integrated on the same package or chip as the cores and communicatively coupled to the cores over an internal processor bus/interconnect (e.g., internal to the package or chip). Regardless of the manner in which the GPU is connected, the processor cores may allocate work to the GPU in the form of sequences of commands/instructions contained in a work descriptor. The GPU then uses dedicated circuitry/logic for efficiently processing these commands/instructions.
As illustrated, a multi-core group 1465A may include a set of graphics cores 1470, a set of tensor cores 1471, and a set of ray tracing cores 1472. A scheduler/dispatcher 1468 schedules and dispatches the graphics threads for execution on the various cores 1470, 1471, 1472. A set of register files 1469 store operand values used by the cores 1470, 1471, 1472 when executing the graphics threads. These may include, for example, integer registers for storing integer values, floating point registers for storing floating point values, vector registers for storing packed data elements (integer and/or floating-point data elements) and tile registers for storing tensor/matrix values. The tile registers may be implemented as combined sets of vector registers.
One or more combined level 1 (L1) caches and shared memory units 1473 store graphics data such as texture data, vertex data, pixel data, ray data, bounding volume data, etc., locally within each multi-core group 1465A. One or more texture units 1474 can also be used to perform texturing operations, such as texture mapping and sampling. A Level 2 (L2) cache 1475 shared by all or a subset of the multi-core groups 1465A-1465N stores graphics data and/or instructions for multiple concurrent graphics threads. As illustrated, the L2 cache 1475 may be shared across a plurality of multi-core groups 1465A-1465N. One or more memory controllers 1467 couple the GPU 1480 to a memory 1466 which may be a system memory (e.g., DRAM) and/or a dedicated graphics memory (e.g., GDDR6 memory).
Input/output (I/O) circuitry 1463 couples the GPU 1480 to one or more I/O devices 1462 such as digital signal processors (DSPs), network controllers, or user input devices. An on-chip interconnect may be used to couple the I/O devices 1462 to the GPU 1480 and memory 1466. One or more I/O memory management units (IOMMUs) 1464 of the I/O circuitry 1463 couple the I/O devices 1462 directly to the system memory 1466. Optionally, the IOMMU 1464 manages multiple sets of page tables to map virtual addresses to physical addresses in system memory 1466. The I/O devices 1462, CPU(s) 1461, and GPU(s) 1480 may then share the same virtual address space.
In one implementation of the IOMMU 1464, the IOMMU 1464 supports virtualization. In this case, it may manage a first set of page tables to map guest/graphics virtual addresses to guest/graphics physical addresses and a second set of page tables to map the guest/graphics physical addresses to system/host physical addresses (e.g., within system memory 1466). The base addresses of each of the first and second sets of page tables may be stored in control registers and swapped out on a context switch (e.g., so that the new context is provided with access to the relevant set of page tables). While not illustrated in
The CPU(s) 1461, GPUs 1480, and I/O devices 1462 may be integrated on a single semiconductor chip and/or chip package. The illustrated memory 1466 may be integrated on the same chip or may be coupled to the memory controllers 1467 via an off-chip interface. In one implementation, the memory 1466 comprises GDDR6 memory which shares the same virtual address space as other physical system-level memories, although the underlying principles described herein are not limited to this specific implementation.
The tensor cores 1471 may include a plurality of execution units specifically designed to perform matrix operations, which are the fundamental compute operations used to perform deep learning operations. For example, simultaneous matrix multiplication operations may be used for neural network training and inferencing. The tensor cores 1471 may perform matrix processing using a variety of operand precisions including single precision floating-point (e.g., 32 bits), half-precision floating point (e.g., 16 bits), integer words (16 bits), bytes (8 bits), and half-bytes (4 bits). For example, a neural network implementation extracts features of each rendered scene, potentially combining details from multiple frames, to construct a high-quality final image.
In deep learning implementations, parallel matrix multiplication work may be scheduled for execution on the tensor cores 1471. The training of neural networks, in particular, requires a significant number of matrix dot product operations. In order to process an inner-product formulation of an N×N×N matrix multiply, the tensor cores 1471 may include at least N dot-product processing elements. Before the matrix multiply begins, one entire matrix is loaded into tile registers and at least one column of a second matrix is loaded each cycle for N cycles. Each cycle, there are N dot products that are processed.
Matrix elements may be stored at different precisions depending on the particular implementation, including 16-bit words, 8-bit bytes (e.g., INT8) and 4-bit half-bytes (e.g., INT4). Different precision modes may be specified for the tensor cores 1471 to ensure that the most efficient precision is used for different workloads (e.g., such as inferencing workloads which can tolerate quantization to bytes and half-bytes). Supported formats additionally include 64-bit floating point (FP64) and non-IEEE floating point formats such as the bfloat 16 format (e.g., Brain floating point), a 16-bit floating point format with one sign bit, eight exponent bits, and eight significand bits, of which seven are explicitly stored. One example includes support for a reduced precision tensor-float (TF32) mode, which performs computations using the range of FP32 (8-bits) and the precision of FP16 (10-bits). Reduced precision TF32 operations can be performed on FP32 inputs and produce FP32 outputs at higher performance relative to FP32 and increased precision relative to FP16. In some examples, one or more 8-bit floating point formats (FP8) are supported.
In some examples the tensor cores 1471 support a sparse mode of operation for matrices in which the vast majority of values are zero. The tensor cores 1471 include support for sparse input matrices that are encoded in a sparse matrix representation (e.g., coordinate list encoding (COO), compressed sparse row (CSR), compress sparse column (CSC), etc.). The tensor cores 1471 also include support for compressed sparse matrix representations in the event that the sparse matrix representation may be further compressed. Compressed, encoded, and/or compressed and encoded matrix data, along with associated compression and/or encoding metadata, can be read by the tensor cores 1471 and the non-zero values can be extracted. For example, for a given input matrix A, a non-zero value can be loaded from the compressed and/or encoded representation of at least a portion of matrix A. Based on the location in matrix A for the non-zero value, which may be determined from index or coordinate metadata associated with the non-zero value, a corresponding value in input matrix B may be loaded. Depending on the operation to be performed (e.g., multiply), the load of the value from input matrix B may be bypassed if the corresponding value is a zero value. In some examples, the pairings of values for certain operations, such as multiply operations, may be pre-scanned by scheduler logic and only operations between non-zero inputs are scheduled. Depending on the dimensions of matrix A and matrix B and the operation to be performed, output matrix C may be dense or sparse. Where output matrix C is sparse and depending on the configuration of the tensor cores 1471, output matrix C may be output in a compressed format, a sparse encoding, or a compressed sparse encoding.
The ray tracing cores 1472 may accelerate ray tracing operations for both real-time ray tracing and non-real-time ray tracing implementations. In particular, the ray tracing cores 1472 may include ray traversal/intersection circuitry for performing ray traversal using bounding volume hierarchies (BVHs) and identifying intersections between rays and primitives enclosed within the BVH volumes. The ray tracing cores 1472 may also include circuitry for performing depth testing and culling (e.g., using a Z buffer or similar arrangement). In one implementation, the ray tracing cores 1472 perform traversal and intersection operations in concert with the image denoising techniques described herein, at least a portion of which may be executed on the tensor cores 1471. For example, the tensor cores 1471 may implement a deep learning neural network to perform denoising of frames generated by the ray tracing cores 1472. However, the CPU(s) 1461, graphics cores 1470, and/or ray tracing cores 1472 may also implement all or a portion of the denoising and/or deep learning algorithms.
In addition, as described above, a distributed approach to denoising may be employed in which the GPU 1480 is in a computing device coupled to other computing devices over a network or high-speed interconnect. In this distributed approach, the interconnected computing devices may share neural network learning/training data to improve the speed with which the overall system learns to perform denoising for different types of image frames and/or different graphics applications.
The ray tracing cores 1472 may process all BVH traversal and/or ray-primitive intersections, saving the graphics cores 1470 from being overloaded with thousands of instructions per ray. For example, each ray tracing core 1472 includes a first set of specialized circuitry for performing bounding box tests (e.g., for traversal operations) and/or a second set of specialized circuitry for performing the ray-triangle intersection tests (e.g., intersecting rays which have been traversed). Thus, for example, the multi-core group 1465A can simply launch a ray probe, and the ray tracing cores 1472 independently perform ray traversal and intersection and return hit data (e.g., a hit, no hit, multiple hits, etc.) to the thread context. The other cores 1470, 1471 are freed to perform other graphics or compute work while the ray tracing cores 1472 perform the traversal and intersection operations.
Optionally, each ray tracing core 1472 may include a traversal unit to perform BVH testing operations and/or an intersection unit which performs ray-primitive intersection tests. The intersection unit generates a “hit,” “no hit,” or “multiple hit” response, which it provides to the appropriate thread. During the traversal and intersection operations, the execution resources of the other cores (e.g., graphics cores 1470 and tensor cores 1471) are freed to perform other forms of graphics work.
In some examples described below, a hybrid rasterization/ray tracing approach is used in which work is distributed between the graphics cores 1470 and ray tracing cores 1472.
The ray tracing cores 1472 (and/or other cores 1470, 1471) may include hardware support for a ray tracing instruction set such as Microsoft's DirectX Ray Tracing (DXR) which includes a DispatchRays command, as well as ray-generation, closest-hit, any-hit, and miss shaders, which enable the assignment of unique sets of shaders and textures for each object. Another ray tracing platform which may be supported by the ray tracing cores 1472, graphics cores 1470 and tensor cores 1471 is Vulkan API (e.g., Vulkan version 1.1.85 and later). Note, however, that the underlying principles described herein are not limited to any particular ray tracing ISA.
In general, the various cores 1472, 1471, 1470 may support a ray tracing instruction set that includes instructions/functions for one or more of ray generation, closest hit, any hit, ray-primitive intersection, per-primitive and hierarchical bounding box construction, miss, visit, and exceptions. More specifically, some examples include ray tracing instructions to perform one or more of the following functions:
In some examples the ray tracing cores 1472 may be adapted to accelerate general-purpose compute operations that can be accelerated using computational techniques that are analogous to ray intersection tests. A compute framework can be provided that enables shader programs to be compiled into low level instructions and/or primitives that perform general-purpose compute operations via the ray tracing cores. Exemplary computational problems that can benefit from compute operations performed on the ray tracing cores 1472 include computations involving beam, wave, ray, or particle propagation within a coordinate space. Interactions associated with that propagation can be computed relative to a geometry or mesh within the coordinate space. For example, computations associated with electromagnetic signal propagation through an environment can be accelerated via the use of instructions or primitives that are executed via the ray tracing cores. Diffraction and reflection of the signals by objects in the environment can be computed as direct ray-tracing analogies.
Ray tracing cores 1472 can also be used to perform computations that are not directly analogous to ray tracing. For example, mesh projection, mesh refinement, and volume sampling computations can be accelerated using the ray tracing cores 1472. Generic coordinate space calculations, such as nearest neighbor calculations can also be performed. For example, the set of points near a given point can be discovered by defining a bounding box in the coordinate space around the point. BVH and ray probe logic within the ray tracing cores 1472 can then be used to determine the set of point intersections within the bounding box. The intersections constitute the origin point and the nearest neighbors to that origin point. Computations that are performed using the ray tracing cores 1472 can be performed in parallel with computations performed on the graphics cores 1472 and tensor cores 1471. A shader compiler can be configured to compile a compute shader or other general-purpose graphics processing program into low level primitives that can be parallelized across the graphics cores 1470, tensor cores 1471, and ray tracing cores 1472.
Building larger and larger silicon dies is challenging for a variety of reasons. As silicon dies become larger, manufacturing yields become smaller and process technology requirements for different components may diverge. On the other hand, in order to have a high-performance system, key components should be interconnected by high speed, high bandwidth, low latency interfaces. These contradicting needs pose a challenge to high performance chip development.
Embodiments described herein provide techniques to disaggregate an architecture of a system on a chip integrated circuit into multiple distinct chiplets that can be packaged onto a common chassis. In some examples, a graphics processing unit or parallel processor is composed from diverse silicon chiplets that are separately manufactured. A chiplet is an at least partially packaged integrated circuit that includes distinct units of logic that can be assembled with other chiplets into a larger package. A diverse set of chiplets with different IP core logic can be assembled into a single device. Additionally the chiplets can be integrated into a base die or base chiplet using active interposer technology. The concepts described herein enable the interconnection and communication between the different forms of IP within the GPU. The development of IPs on different process may be mixed. This avoids the complexity of converging multiple IPs, especially on a large SoC with several flavors IPs, to the same process.
Enabling the use of multiple process technologies improves the time to market and provides a cost-effective way to create multiple product SKUs. For customers, this means getting products that are more tailored to their requirements in a cost effective and timely manner. Additionally, the disaggregated IPs are more amenable to being power gated independently, components that are not in use on a given workload can be powered off, reducing overall power consumption.
In some examples, the register architecture 1600 includes writemask/predicate registers 1615. For example, in some examples, there are 8 writemask/predicate registers (sometimes called k0 through k7) that are each 16-bit, 32-bit, 64-bit, or 128-bit in size. Writemask/predicate registers 1615 may allow for merging (e.g., allowing any set of elements in the destination to be protected from updates during the execution of any operation) and/or zeroing (e.g., zeroing vector masks allow any set of elements in the destination to be zeroed during the execution of any operation). In some examples, each data element position in a given writemask/predicate register 1615 corresponds to a data element position of the destination. In other examples, the writemask/predicate registers 1615 are scalable and consists of a set number of enable bits for a given vector element (e.g., 8 enable bits per 64-bit vector element).
The register architecture 1600 includes a plurality of general-purpose registers 1625. These registers may be 16-bit, 32-bit, 64-bit, etc. and can be used for scalar operations. In some examples, these registers are referenced by the names RAX, RBX, RCX, RDX, RBP, RSI, RDI, RSP, and R8 through R15.
In some examples, the register architecture 1600 includes scalar floating-point (FP) register file 1645 which is used for scalar floating-point operations on 32/64/80-bit floating-point data using the x87 instruction set architecture extension or as MMX registers to perform operations on 64-bit packed integer data, as well as to hold operands for some operations performed between the MMX and XMM registers.
One or more flag registers 1640 (e.g., EFLAGS, RFLAGS, etc.) store status and control information for arithmetic, compare, and system operations. For example, the one or more flag registers 1640 may store condition code information such as carry, parity, auxiliary carry, zero, sign, and overflow. In some examples, the one or more flag registers 1640 are called program status and control registers.
Segment registers 1620 contain segment points for use in accessing memory. In some examples, these registers are referenced by the names CS, DS, SS, ES, FS, and GS.
Model specific registers or machine specific registers (MSRs) 1635 control and report on processor performance. Most MSRs 1635 handle system-related functions and are not accessible to an application program. For example, MSRs may provide control for one or more of: performance-monitoring counters, debug extensions, memory type range registers, thermal and power management, instruction-specific support, and/or processor feature/mode support. Machine check registers 1660 consist of control, status, and error reporting MSRs that are used to detect and report on hardware errors. Control register(s) 1655 (e.g., CR0-CR4) determine the operating mode of a processor (e.g., processor 1070, 1080, 1038, 1015, and/or 1100) and the characteristics of a currently executing task. In some examples, MSRs 1635 are a subset of control registers 1655.
One or more instruction pointer register(s) 1630 store an instruction pointer value. Debug registers 1650 control and allow for the monitoring of a processor or core's debugging operations.
Memory (mem) management registers 1665 specify the locations of data structures used in protected mode memory management. These registers may include a global descriptor table register (GDTR), interrupt descriptor table register (IDTR), task register, and a local descriptor table register (LDTR) register.
Alternative examples may use wider or narrower registers. Additionally, alternative examples may use more, less, or different register files and registers. The register architecture 1600 may, for example, be used in f register file/memory, or physical register file(s) circuitry 758.
As illustrated in
In some examples, the execution units 1708A-1708N are primarily used to execute shader programs. A shader processor 1702 can process the various shader programs and dispatch execution threads associated with the shader programs via a thread dispatcher 1704. In some examples the thread dispatcher includes logic to arbitrate thread initiation requests from the graphics and media pipelines and instantiate the requested threads on one or more execution unit in the execution units 1708A-1708N. For example, a geometry pipeline can dispatch vertex, tessellation, or geometry shaders to the thread execution logic for processing. In some examples, thread dispatcher 1704 can also process runtime thread spawning requests from the executing shader programs.
In some examples, the execution units 1708A-1708N support an instruction set that includes native support for many standard 3D graphics shader instructions, such that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with a minimal translation. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders) and general-purpose processing (e.g., compute and media shaders). Each of the execution units 1708A-1708N is capable of multi-issue single instruction multiple data (SIMD) execution and multi-threaded operation enables an efficient execution environment in the face of higher latency memory accesses. Each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread-state. Execution is multi-issue per clock to pipelines capable of integer, single and double precision floating point operations, SIMD branch capability, logical operations, transcendental operations, and other miscellaneous operations. While waiting for data from memory or one of the shared functions, dependency logic within the execution units 1708A-1708N causes a waiting thread to sleep until the requested data has been returned. While the waiting thread is sleeping, hardware resources may be devoted to processing other threads. For example, during a delay associated with a vertex shader operation, an execution unit can perform operations for a pixel shader, fragment shader, or another type of shader program, including a different vertex shader. Various examples can apply to use execution by use of Single Instruction Multiple Thread (SIMT) as an alternate to use of SIMD or in addition to use of SIMD. Reference to a SIMD core or operation can apply also to SIMT or apply to SIMD in combination with SIMT.
Each execution unit in execution units 1708A-1708N operates on arrays of data elements. The number of data elements is the “execution size,” or the number of channels for the instruction. An execution channel is a logical unit of execution for data element access, masking, and flow control within instructions. The number of channels may be independent of the number of physical Arithmetic Logic Units (ALUs) or Floating-Point Units (FPUs) for a particular graphics processor. In some examples, execution units 1708A-1708N support integer and floating-point data types.
The execution unit instruction set includes SIMD instructions. The various data elements can be stored as a packed data type in a register and the execution unit will process the various elements based on the data size of the elements. For example, when operating on a 256-bit wide vector, the 256 bits of the vector are stored in a register and the execution unit operates on the vector as four separate 64-bit packed data elements (Quad-Word (QW) size data elements), eight separate 32-bit packed data elements (Double Word (DW) size data elements), sixteen separate 16-bit packed data elements (Word (W) size data elements), or thirty-two separate 8-bit data elements (byte (B) size data elements). However, different vector widths and register sizes are possible.
In some examples one or more execution units can be combined into a fused execution unit 1709A-1709N having thread control logic (1707A-1707N) that is common to the fused EUs. Multiple EUs can be fused into an EU group. Each EU in the fused EU group can be configured to execute a separate SIMD hardware thread. The number of EUs in a fused EU group can vary according to examples. Additionally, various SIMD widths can be performed per-EU, including but not limited to SIMD8, SIMD16, and SIMD32. Each fused graphics execution unit 1709A-1709N includes at least two execution units. For example, fused execution unit 1709A includes a first EU 1708A, second EU 1708B, and thread control logic 1707A that is common to the first EU 1708A and the second EU 1708B. The thread control logic 1707A controls threads executed on the fused graphics execution unit 1709A, allowing each EU within the fused execution units 1709A-1709N to execute using a common instruction pointer register.
One or more internal instruction caches (e.g., 1706) are included in the thread execution logic 1700 to cache thread instructions for the execution units. In some examples, one or more data caches (e.g., 1712) are included to cache thread data during thread execution. Threads executing on the execution logic 1700 can also store explicitly managed data in the shared local memory 1711. In some examples, a sampler 1710 is included to provide texture sampling for 3D operations and media sampling for media operations. In some examples, sampler 1710 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to an execution unit.
During execution, the graphics and media pipelines send thread initiation requests to thread execution logic 1700 via thread spawning and dispatch logic. Once a group of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within the shader processor 1702 is invoked to further compute output information and cause results to be written to output surfaces (e.g., color buffers, depth buffers, stencil buffers, etc.). In some examples, a pixel shader or fragment shader calculates the values of the various vertex attributes that are to be interpolated across the rasterized object. In some examples, pixel processor logic within the shader processor 1702 then executes an application programming interface (API)-supplied pixel or fragment shader program. To execute the shader program, the shader processor 1702 dispatches threads to an execution unit (e.g., 1708A) via thread dispatcher 1704. In some examples, shader processor 1702 uses texture sampling logic in the sampler 1710 to access texture data in texture maps stored in memory. Arithmetic operations on the texture data and the input geometry data compute pixel color data for each geometric fragment, or discards one or more pixels from further processing.
In some examples, the data port 1714 provides a memory access mechanism for the thread execution logic 1700 to output processed data to memory for further processing on a graphics processor output pipeline. In some examples, the data port 1714 includes or couples to one or more cache memories (e.g., data cache 1712) to cache data for memory access via the data port.
In some examples, the execution logic 1700 can also include a ray tracer 1705 that can provide ray tracing acceleration functionality. The ray tracer 1705 can support a ray tracing instruction set that includes instructions/functions for ray generation.
In some examples the graphics execution unit 1708 has an architecture that is a combination of Simultaneous Multi-Threading (SMT) and fine-grained Interleaved Multi-Threading (IMT). The architecture has a modular configuration that can be fine-tuned at design time based on a target number of simultaneous threads and number of registers per execution unit, where execution unit resources are divided across logic used to execute multiple simultaneous threads. The number of logical threads that may be executed by the graphics execution unit 1708 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread.
In some examples, the graphics execution unit 1708 can co-issue multiple instructions, which may each be different instructions. The thread arbiter 1722 of the graphics execution unit thread 1708 can dispatch the instructions to one of the send unit 1730, branch unit 1732, or SIMD FPU(s) 1734 for execution. Each execution thread can access 128 general-purpose registers within the GRF 1724, where each register can store 32 bytes, accessible as a SIMD 8-element vector of 32-bit data elements. In some examples, each execution unit thread has access to 4 Kbytes within the GRF 1724, although examples are not so limited, and greater or fewer register resources may be provided in other examples. In some examples the graphics execution unit 1708 is partitioned into seven hardware threads that can independently perform computational operations, although the number of threads per execution unit can also vary according to examples. For example, in some examples up to 16 hardware threads are supported. In an example in which seven threads may access 4 Kbytes, the GRF 1724 can store a total of 28 Kbytes. Where 16 threads may access 4 Kbytes, the GRF 1724 can store a total of 64 Kbytes. Flexible addressing modes can permit registers to be addressed together to build effectively wider registers or to represent strided rectangular block data structures.
In some examples, memory operations, sampler operations, and other longer-latency system communications are dispatched via “send” instructions that are executed by the message passing send unit 1730. In some examples, branch instructions are dispatched to a dedicated branch unit 1732 to facilitate SIMD divergence and eventual convergence.
In some examples the graphics execution unit 1708 includes one or more SIMD floating point units (FPU(s)) 1734 to perform floating-point operations. In some examples, the FPU(s) 1734 also support integer computation. In some examples the FPU(s) 1734 can SIMD execute up to M number of 32-bit floating-point (or integer) operations, or SIMD execute up to 2M 16-bit integer or 16-bit floating-point operations. In some examples, at least one of the FPU(s) provides extended math capability to support high-throughput transcendental math functions and double precision 64-bit floating-point. In some examples, a set of 8-bit integer SIMD ALUs 1735 are also present, and may be specifically optimized to perform operations associated with machine learning computations.
In some examples, arrays of multiple instances of the graphics execution unit 1708 can be instantiated in a graphics sub-core grouping (e.g., a sub-slice). For scalability, product architects can choose the exact number of execution units per sub-core grouping. In some examples the execution unit 1708 can execute instructions across a plurality of execution channels. In a further example, each thread executed on the graphics execution unit 1708 is executed on a different channel.
The execution unit 1800 also includes a compute unit 1810 that includes multiple different types of functional units. In some examples the compute unit 1810 includes an ALU unit 1811 that includes an array of arithmetic logic units. The ALU unit 1811 can be configured to perform 64-bit, 32-bit, and 16-bit integer and floating-point operations. Integer and floating-point operations may be performed simultaneously. The compute unit 1810 can also include a systolic array 1812, and a math unit 1813. The systolic array 1812 includes a W wide and D deep network of data processing units that can be used to perform vector or other data-parallel operations in a systolic manner. In some examples the systolic array 1812 can be configured to perform matrix operations, such as matrix dot product operations. In some examples the systolic array 1812 support 16-bit floating point operations, as well as 8-bit and 4-bit integer operations. In some examples the systolic array 1812 can be configured to accelerate machine learning operations. In such examples, the systolic array 1812 can be configured with support for the bfloat 16-bit floating point format. In some examples, a math unit 1813 can be included to perform a specific subset of mathematical operations in an efficient and lower-power manner than then ALU unit 1811. The math unit 1813 can include a variant of math logic that may be found in shared function logic of a graphics processing engine provided by other examples. In some examples the math unit 1813 can be configured to perform 32-bit and 64-bit floating point operations.
The thread control unit 1801 includes logic to control the execution of threads within the execution unit. The thread control unit 1801 can include thread arbitration logic to start, stop, and preempt execution of threads within the execution unit 1800. The thread state unit 1802 can be used to store thread state for threads assigned to execute on the execution unit 1800. Storing the thread state within the execution unit 1800 enables the rapid pre-emption of threads when those threads become blocked or idle. The instruction fetch/prefetch unit 1803 can fetch instructions from an instruction cache of higher level execution logic (e.g., instruction cache 1706 as in
The execution unit 1800 additionally includes a register file 1806 that can be used by hardware threads executing on the execution unit 1800. Registers in the register file 1806 can be divided across the logic used to execute multiple simultaneous threads within the compute unit 1810 of the execution unit 1800. The number of logical threads that may be executed by the graphics execution unit 1800 is not limited to the number of hardware threads, and multiple logical threads can be assigned to each hardware thread. The size of the register file 1806 can vary across examples based on the number of supported hardware threads. In some examples, register renaming may be used to dynamically allocate registers to hardware threads.
Program code may be applied to input information to perform the functions described herein and generate output information. The output information may be applied to one or more output devices, in known fashion. For purposes of this application, a processing system includes any system that has a processor, such as, for example, a digital signal processor (DSP), a microcontroller, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microprocessor, or any combination thereof.
The program code may be implemented in a high-level procedural or object-oriented programming language to communicate with a processing system. The program code may also be implemented in assembly or machine language, if desired. In fact, the mechanisms described herein are not limited in scope to any particular programming language. In any case, the language may be a compiled or interpreted language.
Examples of the mechanisms disclosed herein may be implemented in hardware, software, firmware, or a combination of such implementation approaches. Examples may be implemented as computer programs or program code executing on programmable systems comprising at least one processor, a storage system (including volatile and non-volatile memory and/or storage elements), at least one input device, and at least one output device.
Such machine-readable storage media may include, without limitation, non-transitory, tangible arrangements of articles manufactured or formed by a machine or device, including storage media such as hard disks, any other type of disk including floppy disks, optical disks, compact disk read-only memories (CD-ROMs), compact disk rewritables (CD-RWs), and magneto-optical disks, semiconductor devices such as read-only memories (ROMs), random access memories (RAMs) such as dynamic random access memories (DRAMs), static random access memories (SRAMs), erasable programmable read-only memories (EPROMs), flash memories, electrically erasable programmable read-only memories (EEPROMs), phase change memory (PCM), magnetic or optical cards, or any other type of media suitable for storing electronic instructions.
Accordingly, examples also include non-transitory, tangible machine-readable media containing instructions or containing design data, such as Hardware Description Language (HDL), which defines structures, circuits, apparatuses, processors and/or system features described herein. Such examples may also be referred to as program products.
References to “some examples,” “an example,” etc., indicate that the example described may include a particular feature, structure, or characteristic, but every example may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same example. Further, when a particular feature, structure, or characteristic is described in connection with an example, it is submitted that it is within the knowledge of one skilled in the art to affect such feature, structure, or characteristic in connection with other examples whether or not explicitly described.
Moreover, in the various examples described above, unless specifically noted otherwise, disjunctive language such as the phrase “at least one of A, B, or C” or “A, B, and/or C” is intended to be understood to mean either A, B, or C, or any combination thereof (i.e., A and B, A and C, B and C, and A, B and C).
The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. It will, however, be evident that various modifications and changes may be made thereunto without departing from the broader spirit and scope of the disclosure as set forth in the claims.
Example 1 provides an exemplary method comprising: decoding an instruction to access data or code by a core of a computer processor, the instruction to provide one or more hints on how the data or code is to be processed through a cache hierarchy of the computer processor based on the instruction, the one or more hints indicating which level of the cache hierarchy or which cache in a level of the cache hierarchy to load or store the data or code, a priority of the data or code in a cache, or how the data or code is to be shared among multiple cores of the computer processor; and processing the data or code based on the one or more hints responsive to the decoded instruction.
Example 2 includes the substance of Example 1, wherein the one or more hints are indicated by one or more immediate bits of the instruction.
Example 3 includes the substance of Examples 1 to 2, wherein one or more immediate bits of the instruction indicate one or more registers from which the one or more hints is to be obtained.
Example 4 includes the substance of Examples 1 to 3, wherein the one or more bits of the one or more registers are read during decoding the instruction and the one or more bits are passed along in a processor pipeline for executing the instruction to provide further hint on how the data or code is to be processed through the cache hierarchy.
Example 5 includes the substance of Examples 1 to 4, wherein the access to the second set of resources is saved in a record, and wherein which resources are to be included in the second set of resources in a subsequent context switch may be identified based on the record.
Example 6 includes the substance of Examples 1 to 5, wherein the one or more registers comprises a source register from which the data or code is stored, or a destination register to which the data or code is loaded, wherein the source or destination register is indicated in the instruction, and wherein the one or more bits in the source register or destination register indicates a hint on how the data or code is to be stored or loaded, respectively.
Example 7 includes the substance of Examples 1 to 6, wherein upon context switching, a state of the one or more registers is to be stored as a part of state of a thread switching out of the core.
Example 8 includes the substance of Examples 1 to 7, wherein the instruction is to load the data or code to the core, store the data or code from the core, or prefetch the data or code to the core.
Example 9 includes the substance of Examples 1 to 8, wherein the one or more hints further indicates one or more of: how the data or code is to be ordered, how the data or code is to be transformed upon accessing, an eviction treatment to specify how the data or code is to be replaced, or how the data or code is to interact with a prefetcher of the computer processor, how the data or code is to be prefetched, or a priority of the data or code in prefetching.
Example 10 includes the substance of Examples 1 to 9, wherein a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit, a tensor processing unit, a matrix math unit comprises the processor core.
Example 11 provides an exemplary computer processor comprising: a set of processor cores, wherein a core with the set of processor cores comprising: a decode circuitry to decode an instruction to access data or code by a core of a computer processor, the instruction to provide one or more hints on how the data or code is to be processed through a cache hierarchy of the computer processor based on the instruction, the one or more hints indicating which level of the cache hierarchy or which cache in a level of the cache hierarchy to load or store the data or code, a priority of the data or code in a cache, or how the data or code is to be shared among the set of cores of the computer processor; and execution circuitry to process the data or code based on the one or more hints responsive to the decoded instruction.
Example 12 includes the substance of Example 11, wherein the one or more hints are indicated by one or more immediate bits of the instruction.
Example 13 includes the substance of Examples 11 to 12, wherein the one or more hints are indicated by one or more bits of one or more registers accessible by the core upon decoding the instruction.
Example 14 includes the substance of Examples 11 to 13, wherein the one or more bits of the one or more registers are read during decoding the instruction and the one or more bits are passed along in a processor pipeline for executing the instruction to provide further hint on how the data or code is to be processed through the cache hierarchy.
Example 15 includes the substance of Examples 11 to 14, wherein the one or more hints further indicates one or more of: how the data or code is to be ordered, how the data or code is to be transformed upon accessing, an eviction treatment to specify how the data or code is to be replaced, or how the data or code is to interact with a prefetcher of the computer processor, how the data or code is to be prefetched, or a priority of the data or code in prefetching.
Example 16 provides non-transitory machine-readable storage medium storing instructions that when executed by a machine, are capable of causing performance of: decoding an instruction to access data or code by a core of a computer processor, the instruction to provide one or more hints on how the data or code is to be processed through a cache hierarchy of the computer processor based on the instruction, the one or more hints indicating which level of the cache hierarchy or which cache in a level of the cache hierarchy to load or store the data or code, a priority of the data or code in a cache, or how the data or code is to be shared among multiple cores of the computer processor; and processing the data or code based on the one or more hints responsive to the decoded instruction.
Example 17 includes the substance of Example 16, wherein the one or more hints are indicated by one or more immediate bits of the instruction.
Example 18 includes the substance of Examples 16 to 17, wherein the one or more hints are indicated by one or more bits of one or more registers accessible by the core upon decoding the instruction.
Example 19 includes the substance of Examples 16 to 18, wherein the one or more registers comprises a source register from which the data or code is stored, or a destination register to which the data or code is loaded, wherein the source or destination register is indicated in the instruction, and wherein the one or more bits in the source register or destination register indicate the hint on how the data or code is to be stored or loaded, respectively.
Example 20 includes the substance of Examples 16 to 19, wherein upon context switching, a state of the one or more registers is to be stored as a part of state of a thread switching out of the core.
As described herein, instructions may refer to specific configurations of hardware such as application specific integrated circuits (ASICs) configured to perform certain operations or having a predetermined functionality or software instructions stored in memory embodied in a non-transitory computer-readable medium. Thus, the techniques shown in the Figures can be implemented using code and data stored and executed on one or more electronic devices (e.g., an end station, a network element, etc.). Such electronic devices store and communicate (internally and/or with other electronic devices over a network) code and data using computer machine-readable media, such as non-transitory computer machine-readable storage media (e.g., magnetic disks; optical disks; random access memory; read only memory; flash memory devices; phase-change memory) and transitory computer machine-readable communication media (e.g., electrical, optical, acoustical, or other form of propagated signals-such as carrier waves, infrared signals, digital signals, etc.). In addition, such electronic devices typically include a set of one or more processors coupled to one or more other components, such as one or more storage devices (non-transitory machine-readable storage media), user input/output devices (e.g., a keyboard, a touchscreen, and/or a display), and network connections. The coupling of the set of processors and other components is typically through one or more buses and bridges (also termed as bus controllers). The storage device and signals carrying the network traffic respectively represent one or more machine-readable storage media and machine-readable communication media. Thus, the storage device of a given electronic device typically stores code and/or data for execution on the set of one or more processors of that electronic device. Of course, one or more parts of an embodiment of the disclosure may be implemented using different combinations of software, firmware, and/or hardware. Throughout this detailed description, for the purposes of explanation, numerous specific details were set forth in order to provide a thorough understanding of the present disclosure. It will be apparent, however, to one skilled in the art that the disclosure may be practiced without some of these specific details. In certain instances, well-known structures and functions were not described in elaborate detail in order to avoid obscuring the subject matter of the present disclosure. Accordingly, the scope and spirit of the disclosure should be judged in terms of the claims which follow.
