Delay-insensitive circuit design

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions

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G06F17/5059Delay-insensitive circuit design

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Patents Grantslast 30 patents

Information Patent Grant
Providing guidance to an equivalence checker when a design contains...
- Patent number 10,628,545
- Issue date Apr 21, 2020
- Synopsys, Inc.
- Muzaffer Hiraoglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design analyzer
- Patent number 10,599,792
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing-adaptive, configurable logic architecture
- Patent number 10,565,339
- Issue date Feb 18, 2020
- Mellanox Technologies, Ltd.
- Uria Basher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for virtual clock and mode extraction in hierarchical...
- Patent number 10,558,782
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Glitch-aware phase algebra for clock analysis
- Patent number 10,552,559
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital design with bundled data asynchronous logic and body-biasin...
- Patent number 10,552,563
- Issue date Feb 4, 2020
- QUALCOMM Incorporated
- Mark Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional phase algebra for clock analysis
- Patent number 10,552,558
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock-gating phase algebra for clock analysis
- Patent number 10,515,164
- Issue date Dec 24, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
RC tool accuracy time reduction
- Patent number 10,515,172
- Issue date Dec 24, 2019
- Taiwan Semiconductor Manufacturing Company Limited
- Hui-I Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Optimum stage number calculation method, information processing app...
- Patent number 10,509,879
- Issue date Dec 17, 2019
- Fujitsu Limited
- Michitaka Hashimoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for specifying clocks and modes in hierarchical designs
- Patent number 10,503,856
- Issue date Dec 10, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network logic synthesis
- Patent number 10,496,773
- Issue date Dec 3, 2019
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chi-Chuan Chuang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bisection methodology for on-chip variation tolerant clock signal d...
- Patent number 10,474,779
- Issue date Nov 12, 2019
- Juniper Networks, Inc.
- Vincent C. Leung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for application specific integrated circuit design
- Patent number 10,467,367
- Issue date Nov 5, 2019
- CHRONOS TECH LLC
- Stefano Giaconi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Static timing analysis in circuit design
- Patent number 10,380,285
- Issue date Aug 13, 2019
- International Business Machines Corporation
- Hongwei Dai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dual-rail delay insensitive asynchronous logic processor with singl...
- Patent number 10,338,930
- Issue date Jul 2, 2019
- Eta Compute, Inc.
- Ben Melton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for implementing user-guided speculative regis...
- Patent number 10,339,244
- Issue date Jul 2, 2019
- Altera Corporation
- Benjamin Gamsa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock-gating phase algebra for clock analysis
- Patent number 10,331,822
- Issue date Jun 25, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional phase algebra for clock analysis
- Patent number 10,325,040
- Issue date Jun 18, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synchronizing a self-timed processor with an external event
- Patent number 10,326,452
- Issue date Jun 18, 2019
- Eta Compute, Inc.
- David Baker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design analyzer
- Patent number 10,325,041
- Issue date Jun 18, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for virtual clock and mode extraction in hierarchical...
- Patent number 10,318,695
- Issue date Jun 11, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing analysis and optimization of asynchronous circuit designs
- Patent number 10,318,691
- Issue date Jun 11, 2019
- Wave Computing, Inc.
- Philippe Francis Sarrazin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Model-building method and model-building system
- Patent number 10,311,185
- Issue date Jun 4, 2019
- Global Unichip Corporation
- Hsin-Hsiung Liao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Sensitivity calculation filtering for statistical static timing ana...
- Patent number 10,289,776
- Issue date May 14, 2019
- International Business Machines Corporation
- Nathan Buck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay propagation for multiple logic cells using correlation and co...
- Patent number 10,275,554
- Issue date Apr 30, 2019
- Cadence Design Systems, Inc.
- Mikhail Chetin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Application specific integrated circuit interconnect
- Patent number 10,235,488
- Issue date Mar 19, 2019
- CHRONOS TECH LLC
- Stefano Giaconi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transition test generation for detecting cell internal defects
- Patent number 10,222,420
- Issue date Mar 5, 2019
- Mentor Graphics Corporation
- Xijiang Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for analysis of hierarchical designs
- Patent number 10,216,881
- Issue date Feb 26, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing circuits for parallel asynchronous modeling and execution
- Patent number 10,181,003
- Issue date Jan 15, 2019
- You Know Solutions, LLC
- Ronald J. Lavallee
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Hardware Support for OS-Centric Performance Monitoring with Data Co...
- Publication number 20200319884
- Publication date Oct 8, 2020
- NXP USA, Inc.
- Michael Rohleder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN
- Publication number 20200065437
- Publication date Feb 27, 2020
- CHRONOS TECH LLC
- Stefano Giaconi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROVIDING GUIDANCE TO AN EQUIVALENCE CHECKER WHEN A DESIGN CONTAINS...
- Publication number 20200026813
- Publication date Jan 23, 2020
- Synopsys, Inc.
- Muzaffer Hiraoglu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PESSIMISM IN STATIC TIMING ANALYSIS
- Publication number 20200026812
- Publication date Jan 23, 2020
- Synopsys, Inc.
- Chunyang Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Timing-adaptive, configurable logic architecture
- Publication number 20200026814
- Publication date Jan 23, 2020
- MELLANOX TECHNOLOGIES, LTD.
- Uria Basher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ADAPTIVE VOLTAGE SCALING TO ELIMINATE DELA...
- Publication number 20190384868
- Publication date Dec 19, 2019
- Realtek Semiconductor Corp.
- Mei-Li Yu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20190266302
- Publication date Aug 29, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALGEBRA FOR VIRTUAL CLOCK AND MODE EXTRACTION IN HIERARCHICAL...
- Publication number 20190258772
- Publication date Aug 22, 2019
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL DESIGN WITH BUNDLED DATA ASYNCHRONOUS LOGIC AND BODY-BIASIN...
- Publication number 20190213296
- Publication date Jul 11, 2019
- QUALCOMM Incorporated
- Mark Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT INCLUDING LOAD STANDARD CELL AND METHOD OF DESIG...
- Publication number 20190197214
- Publication date Jun 27, 2019
- Samsung Electronics Co., Ltd.
- Kwan-Yeob Chae
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISTRIBUTED PROGRAMMABLE DELAY LINES IN A CLOCK TREE
- Publication number 20190179990
- Publication date Jun 13, 2019
- Intel Corporation
- Herman Henry Schmit
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION SPECIFIC INTEGRATED CIRCUIT INTERCONNECT
- Publication number 20190179992
- Publication date Jun 13, 2019
- CHRONOS TECH LLC
- Stefano GIACONI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RC Tool Accuracy Time Reduction
- Publication number 20190121928
- Publication date Apr 25, 2019
- Taiwan Semiconductor Manufacturing Company Limited
- Hui-I Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYNCHRONIZING A SELF-TIMED PROCESSOR WITH AN EXTERNAL EVENT
- Publication number 20190097634
- Publication date Mar 28, 2019
- Eta Compute, Inc.
- David Baker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN
- Publication number 20190095553
- Publication date Mar 28, 2019
- CHRONOS TECH LLC
- Stefano Giaconi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED-POWER DYNAMIC DATA CIRCUITS WITH WIDE-BAND ENERGY RECOVERY
- Publication number 20190095568
- Publication date Mar 28, 2019
- REZONENT CORPORATION
- IGNATIUS BEZZAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-RAIL DELAY INSENSITIVE ASYNCHRONOUS LOGIC PROCESSOR WITH SINGL...
- Publication number 20190004811
- Publication date Jan 3, 2019
- Eta Compute, Inc.
- Ben Melton
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL-RAIL DELAY INSENSITIVE ASYNCHRONOUS LOGIC PROCESSOR WITH SINGL...
- Publication number 20190004812
- Publication date Jan 3, 2019
- Eta Compute, Inc.
- Ben Melton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
OPTIMUM STAGE NUMBER CALCULATION METHOD, INFORMATION PROCESSING APP...
- Publication number 20180349534
- Publication date Dec 6, 2018
- Fujitsu Limited
- Michitaka Hashimoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODEL-BUILDING METHOD AND MODEL-BUILDING SYSTEM
- Publication number 20180330033
- Publication date Nov 15, 2018
- Global Unichip Corporation
- Hsin-Hsiung LIAO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SENSITIVITY CALCULATION FILTERING FOR STATISTICAL STATIC TIMING ANA...
- Publication number 20180285503
- Publication date Oct 4, 2018
- International Business Machines Corporation
- Nathan Buck
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION SPECIFIC INTEGRATED CIRCUIT INTERCONNECT
- Publication number 20180144079
- Publication date May 24, 2018
- CHRONOS TECH LLC
- Stefano GIACONI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS
- Publication number 20180107776
- Publication date Apr 19, 2018
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT DESIGN ANALYZER
- Publication number 20180082003
- Publication date Mar 22, 2018
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS
- Publication number 20180075178
- Publication date Mar 15, 2018
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TIMING ANALYSIS AND OPTIMIZATION OF ASYNCHRONOUS CIRCUIT DESIGNS
- Publication number 20170371993
- Publication date Dec 28, 2017
- Wave Computing, Inc.
- Philippe Francis Sarrazin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING SYSTEM
- Publication number 20170337316
- Publication date Nov 23, 2017
- Huawei Technologies Co., Ltd
- Xingshan Zhao
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK LOGIC SYNTHESIS
- Publication number 20170116354
- Publication date Apr 27, 2017
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Chuan CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC CIRCUIT AND SYSTEM AND COMPUTER PROGRAM PRODUCT FOR LOGIC SYN...
- Publication number 20160055270
- Publication date Feb 25, 2016
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chi-Chuan CHUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STATIC CHECKING OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS
- Publication number 20150269296
- Publication date Sep 24, 2015
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING

Delay-insensitive circuit design

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Providing guidance to an equivalence checker when a design contains...

Circuit design analyzer

Timing-adaptive, configurable logic architecture

Phase algebra for virtual clock and mode extraction in hierarchical...

Glitch-aware phase algebra for clock analysis

Digital design with bundled data asynchronous logic and body-biasin...

Conditional phase algebra for clock analysis

Clock-gating phase algebra for clock analysis

RC tool accuracy time reduction

Optimum stage number calculation method, information processing app...

Phase algebra for specifying clocks and modes in hierarchical designs

Network logic synthesis

Bisection methodology for on-chip variation tolerant clock signal d...

System and method for application specific integrated circuit design

Static timing analysis in circuit design

Dual-rail delay insensitive asynchronous logic processor with singl...

Method and apparatus for implementing user-guided speculative regis...

Clock-gating phase algebra for clock analysis

Conditional phase algebra for clock analysis

Synchronizing a self-timed processor with an external event

Circuit design analyzer

Phase algebra for virtual clock and mode extraction in hierarchical...

Timing analysis and optimization of asynchronous circuit designs

Model-building method and model-building system

Sensitivity calculation filtering for statistical static timing ana...

Delay propagation for multiple logic cells using correlation and co...

Application specific integrated circuit interconnect

Transition test generation for detecting cell internal defects

Phase algebra for analysis of hierarchical designs

Processing circuits for parallel asynchronous modeling and execution

Patents Applicationslast 30 patents

Hardware Support for OS-Centric Performance Monitoring with Data Co...

SYSTEM AND METHOD FOR APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN

PROVIDING GUIDANCE TO AN EQUIVALENCE CHECKER WHEN A DESIGN CONTAINS...

PESSIMISM IN STATIC TIMING ANALYSIS

Timing-adaptive, configurable logic architecture

METHOD AND APPARATUS FOR ADAPTIVE VOLTAGE SCALING TO ELIMINATE DELA...

CLOCK-GATING PHASE ALGEBRA FOR CLOCK ANALYSIS

PHASE ALGEBRA FOR VIRTUAL CLOCK AND MODE EXTRACTION IN HIERARCHICAL...

DIGITAL DESIGN WITH BUNDLED DATA ASYNCHRONOUS LOGIC AND BODY-BIASIN...

INTEGRATED CIRCUIT INCLUDING LOAD STANDARD CELL AND METHOD OF DESIG...

DISTRIBUTED PROGRAMMABLE DELAY LINES IN A CLOCK TREE

APPLICATION SPECIFIC INTEGRATED CIRCUIT INTERCONNECT

RC Tool Accuracy Time Reduction

SYNCHRONIZING A SELF-TIMED PROCESSOR WITH AN EXTERNAL EVENT

SYSTEM AND METHOD FOR APPLICATION SPECIFIC INTEGRATED CIRCUIT DESIGN

REDUCED-POWER DYNAMIC DATA CIRCUITS WITH WIDE-BAND ENERGY RECOVERY

DUAL-RAIL DELAY INSENSITIVE ASYNCHRONOUS LOGIC PROCESSOR WITH SINGL...

DUAL-RAIL DELAY INSENSITIVE ASYNCHRONOUS LOGIC PROCESSOR WITH SINGL...

OPTIMUM STAGE NUMBER CALCULATION METHOD, INFORMATION PROCESSING APP...

MODEL-BUILDING METHOD AND MODEL-BUILDING SYSTEM

SENSITIVITY CALCULATION FILTERING FOR STATISTICAL STATIC TIMING ANA...

APPLICATION SPECIFIC INTEGRATED CIRCUIT INTERCONNECT

PHASE ALGEBRA FOR ANALYSIS OF HIERARCHICAL DESIGNS

CIRCUIT DESIGN ANALYZER

GLITCH-AWARE PHASE ALGEBRA FOR CLOCK ANALYSIS

TIMING ANALYSIS AND OPTIMIZATION OF ASYNCHRONOUS CIRCUIT DESIGNS

DATA PROCESSING SYSTEM

NETWORK LOGIC SYNTHESIS

LOGIC CIRCUIT AND SYSTEM AND COMPUTER PROGRAM PRODUCT FOR LOGIC SYN...

STATIC CHECKING OF ASYNCHRONOUS CLOCK DOMAIN CROSSINGS