Patent Application
20190384868
The present invention is related to adaptive voltage scaling, and more particularly, to a method and apparatus for adaptive voltage scaling to eliminate delay variation of a whole design.
Regarding the development of semiconductor process technology in recent years, process variation information provided by wafer fab may help system development engineers to perform system design having high yield. However, component types, component sizes and operating voltage used for different blocks within the system design may be different according to respective design consideration. In addition, when global variation and local variation are considered together, conventional corner variation method cannot precisely determine the variation in the system design, for example, it may be too optimistic or too pessimistic. As a result, it is hard to improve the yield, and therefore additional costs may be introduced. Thus, a novel method is needed to precisely estimate the variation of the system design, in order to eliminate delay variation of the system design without introducing any side effect or in a way that is less likely to introduce a side effect.
An objective of the present invention is to provide a method for adaptive voltage scaling to eliminate delay variation of a whole design and associated analyzing device, to solve the aforementioned problems.
Another objective of the present invention is to provide a method for adaptive voltage scaling to eliminate delay variation of a whole design and associated analyzing device, to eliminate the delay variation of the system design without introducing any side effect or in a way that is less likely to introduce a side effect.
At least one embodiment of the present invention provides a method for adaptive voltage scaling to eliminate delay variation of a whole design. The method comprises: reading a circuit simulation netlist file, a circuit design database, and a path list, wherein the circuit simulation netlist file indicates component information of the whole design; according to the circuit design database, building a delay variation database of each minimum unit within multiple minimum units of the whole design under various voltage levels; utilizing an initial voltage level to be a voltage level of a driving voltage of the whole design to apply the initial voltage level to the whole design, and according to the delay variation database, performing static timing analysis (STA) on the whole design, to determine whether any timing violation path exists in the path list; and according to whether the timing violation path exists, selectively adjusting the voltage level of the driving voltage and re-performing the STA until no timing violation path exists.
At least one embodiment of the present invention provides an analyzing device. The analyzing device may comprise a processing circuit. The analyzing device is arranged to control the analyzing device to perform the following operations: reading a circuit simulation netlist file, a circuit design database, and a path list, wherein the circuit simulation netlist file indicates component information of the whole design; according to the circuit design database, building a delay variation database of each minimum unit within multiple minimum units of the whole design under various voltage levels; utilizing an initial voltage level to be a voltage level of a driving voltage of the whole design to apply the initial voltage level to the whole design, and according to the delay variation database, performing static timing analysis (STA) on the whole design, to determine whether any timing violation path exists in the path list; and according to whether the timing violation path exists, selectively adjusting the voltage level of the driving voltage and re-performing the STA until no timing violation path exists.
One of advantages of the present invention is that the present invention can perform analysis having high precision for delay variation of the whole design, and find an adaptive voltage level to eliminate the delay variation to improve yield. In addition, implementing according to the embodiments of the present invention will not greatly increase additional costs. Therefore, problems of the related art can be solved without greatly increasing the overall cost. In comparison with the related art, the present invention can precisely analyze delay variation of the whole design, and eliminate the delay variation of system design to improve yield without introducing side effects or in a way that is less likely to introduce side effects.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment that is illustrated in the various figures and drawings.
Embodiments of the present invention provide a method for adaptive voltage scaling to eliminate delay variation of a whole design (referred to as the method hereafter, for brevity) and associated apparatus such as an analyzing device (which may be referred to as the device, for brevity). Based on at least one of multiple control schemes of the method (e.g. the control schemes in some embodiments such as that shown in
In this embodiment, a circuit simulation netlist file may be generated according to the network, and indicate component information of the whole design 10 (e.g. respective input terminals and output terminals of each of the flip-flops FF1-FFN). In addition, a path list may indicate at least one portion (a portion or all) of path information of the whole design 10. For example, the path list may comprise at least one path of the whole design 10, such as a path PATH1 passing through the flip-flops FF1 and FF2. In this embodiment, in addition to the path PATH1 passing through the flip-flops FF1 and FF2, the path list may further comprise a path PATH2 passing through the flip-flops FF3 and FF4, . . . , a path PATHM-1 passing through the flip-flops FFN-3 and FFN-2, and a path PATHM passing through the flip-flops FFN-3 and FFN-1 (M is a positive integer), but the present invention is not limited thereto.
In this embodiment, a delay variation database for each of the multiple minimum units (such as the flip-flops FF1-FFN) under various voltage levels may be built according to a circuit design database. For example, the circuit design database may comprise process information provided by the wafer fab, specification requirements, and resistor or capacitor information (which may be referred to as RC information) within the whole design 10, where the process information may comprise circuit characteristics and behaviors (for example, component characteristics such as process variation) of each minimum unit (such as each of the flip-flops FF1-FFN). In this embodiment, through a statistics method (e.g. Monte-Carlo method), the device (e.g. a processing circuit therein) may build the delay variation database (such as a mapping table) according to the process information. More particularly, for the aforementioned each minimum unit of the whole design 10, the device (e.g. the processing circuit) may determine delay variation of the aforementioned each minimum unit, such as the delay variation corresponding to a certain voltage level of the driving voltage, through the mapping table, but the present invention is not limited thereto.
Then, the device (e.g. the processing circuit) may utilize an initial voltage level to be a voltage level of a driving voltage provided by the voltage supply circuit 100 coupled to the whole design 10, to apply the initial voltage level to the whole design 10, and according to the aforementioned delay variation database, the device may perform static timing analysis (STA) on the whole design 10, to determine whether any timing violation path (e.g. at least one timing violation path, such as one or more timing violation paths) exists in the paths {PATH1, PATH2, . . . , PATHM-1, PATHM} within the path list. The path list includes combinational cells from Flip-Flop to Flip-Flop in PATH1 . . . M, for example, each of the paths {PATH1, PATH2, . . . , PATHM-1, PATHM} includes combinational cells from Flip-Flop to Flip-Flop. The timing violation path may include, but are not limited to: a path having a delay that is not within in an allowable range of delay specification requirement.
For example, provided that the allowable range of delay specification requirement is set to be within +1 ns of the delay specification requirement (e.g. 1 ns), when a delay of the path PATH1 is 1.06 ns (i.e. this delay corresponds to an error of +6%), the path PATH1 may be regarded as a timing violation path. When a delay of the path PATH1 is 0.94 ns (i.e. this delay corresponds to an error of −6%), the path PATH1 may not be regarded as a timing violation path.
Additionally, according to whether the timing violation path exists, the device (e.g. the processing circuit) may selectively adjust the voltage level of the driving voltage and re-perform the STA until no timing violation path exists (e.g. the aforementioned at least one timing violation path no longer exists). For example, after the STA is performed for the first time, the timing violation path (e.g. the paths PATH1 and PATH2) exists in the path list, and then the voltage level of the driving voltage is adjusted to a second voltage level (e.g. 0.91 V) that is different from the initial voltage level (e.g. 0.9 V). After adjusting the voltage level of the driving voltage to the second voltage level (e.g. 0.91 V) and performing the STA for the second time, the device (e.g. the processing circuit) determines that the timing violation path has been removed, and the second voltage level (e.g. 0.91 V) may be utilized as a voltage level of an adaptive voltage conforming to the delay specification requirement of the whole design 10. For another example, after the STA is performed for the first time, the timing violation path (e.g. the path PATH1 and PATH2) exists in the path list, and then the voltage level of the driving voltage is adjusted to a second voltage level (e.g. 0.91 V) that is different from the initial voltage level (e.g. 0.9 V). After the STA is performed for the second time, the timing violation path (e.g. the path PATH1) still exists in the path list, and then the voltage level of the driving voltage is adjusted to a third voltage level (e.g. 0.92 V) that is different from the initial voltage level (e.g. 0.9 V) and the second voltage level (e.g. 0.91 V). After adjusting the voltage level of the driving voltage to the third voltage level (e.g. 0.92 V) and performing the STA for the third time, the device (e.g. the processing circuit) determines that the timing violation path has been removed, and the third voltage level (e.g. 0.92 V) may be utilized as the voltage level of the adaptive voltage conforming to the delay specification requirement of the whole design 10. As shown in the above examples, when the timing violation path exists in the path list, the device (e.g. the processing circuit) may adjust the voltage level of the driving voltage and re-perform the STA, iteratively, until no timing violation path exists (e.g. the aforementioned at least one timing violation path no longer exists). For yet another example, after the STA is performed for the first time, when no timing violation path exists in the path list (e.g. the aforementioned at least one timing violation path no longer exists), the device (e.g. the processing circuit) may determine that the initial voltage level (e.g. 0.9 V) may be utilized as the voltage level of the adaptive voltage conforming to the delay specification requirement of the whole design 10, and more particularly, may prevent adjusting the voltage level of the driving voltage and prevent re-performing the STA, but the present invention is not limited thereto.
In addition, after the voltage level of the driving voltage conforming to the delay specification requirement of the whole design 10 (such as the voltage level of the aforementioned adaptive voltage) is found, the device (e.g. the processing circuit) may utilize a circuit simulator to perform verification, to guarantee correctness of the voltage level of the driving voltage (for example, a simulation result of the circuit simulator is identical or similar to an analysis result of the aforementioned STA, which may indicate that the voltage level of the driving voltage is correct), where the circuit simulator may be equipped with transistor-level simulation capability.
In this embodiment, according to the physical layout of the whole design 20 shown in
Step S1: the device (e.g. the processing circuit) may read a circuit simulation netlist file, a circuit design database, a path list and IR drop information.
Step S2: according to the circuit design database, the device (e.g. the processing circuit) may build a delay variation database of each minimum unit within multiple minimum units (such as the Process Device (e.g. devices or component for a specific process)) of the whole design 20 under various voltage levels.
Step S3: the device (e.g. the processing circuit) may utilize an initial voltage level (e.g. 1 V) to be a voltage level of a driving voltage of the whole design 20, and determine effective voltage levels applied to the one critical path such as the critical one of the paths {PATH1, PATH2, . . . , PATHM-1, PATHM} (e.g. effective voltage levels equal to 0.95 V for a critical path case from FF1 to FF2 (such as minimum units within the PATH1)) of the whole design 20 according to the IR drop information, respectively, to apply the effective voltage levels to the one critical path within the whole design 20, respectively, and perform the STA on the whole design 20 to generate an analysis result according to the delay variation database.
Step S4: according to the analysis result in Step S3, the device (e.g. the processing circuit) may determine whether any timing violation path (e.g. at least one timing violation path such as that mentioned above) exists in the path list. When the timing violation path (e.g. the paths PATH1 and PATH2) exists in the path list, Step S5 is entered; otherwise, Step S7 is entered.
Step S5: the device (e.g. the processing circuit) may adjust the voltage level of the driving voltage to another voltage level (e.g. 1.01 V), and determine the effective voltage levels applied to all paths (e.g. 0.96 V for all paths {PATH1, PATH2, . . . , PATHM-1, PATHM} (such as all minimum units within the paths {PATH1, PATH2, . . . , PATHM-1, PATHM}, or respective effective voltage levels for different paths)) within the whole design 20 according to the IR drop information, respectively, to apply the effective voltage levels to the all paths within the whole design 20, respectively, and re-perform the STA to generate an analysis result.
Step S6: according to the analysis result in Step S5, the device (e.g. the processing circuit) may determine whether any timing violation path (e.g. at least one timing violation path such as that mentioned above) exists in the path list. When the timing violation path (e.g. the paths PATH1) exists in the path list, Step S5 is entered; otherwise, Step S7 is entered.
Step S7: the device (e.g. the processing circuit) may utilize a circuit simulator to perform verification, to guarantee correctness of the voltage level of the driving voltage, wherein the circuit simulator is equipped with transistor-level simulation capability.
Please note that, as long as it does not hinder the implementation of the present invention, one or more steps may be altered, added, or deleted in the workflow. After reading the above paragraphs regarding
Through the adaptive voltage scaling and timing path analysis mechanisms of the present invention, in comparison with conventional design method and corner analysis method, the method and apparatus of the present invention can precisely determine the delay variation of a whole design (i.e. the delay variation of signal paths within the whole design), and quickly eliminate the delay variation of the whole design by adaptive voltage scaling without using other way such as amending circuit structure, and therefore can prevent any side effect (e.g. additional risks and costs) due to the other way such as amending circuit structure.
Those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention. Accordingly, the above disclosure should be construed as limited only by the metes and bounds of the appended claims.
| Number | Date | Country | Kind |
|---|---|---|---|
| 107120275 | Jun 2018 | TW | national |
