Determining start or end of instruction; determining instruction length

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G06F9/30152

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/30152Determining start or end of instruction; determining instruction length

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Patents Grantslast 30 patents

Information Patent Grant
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Dynamic designation of instructions as sensitive for constraining i...
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Fixed-size pool storage for handling out-of order receipt of data
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Encoding and decoding variable length instructions
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Information Patent Grant
Encoding and decoding variable length instructions
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Information Patent Grant
Instruction length based parallel instruction demarcator
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Information Patent Grant
Conditional transaction end instruction
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Information Patent Grant
Electronic apparatus, VLIW processor and control methods for updati...
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Information Patent Grant
Conditional transaction end instruction
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Electronic apparatus, VLIW processor and control methods for updati...
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Conditional transaction end instruction
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Reordering buffer for memory access locality
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Information Patent Grant
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Information Patent Grant
Conditional transaction end instruction
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- Issue date Sep 27, 2016
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- Dan F. Greiner
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Information Patent Grant
Conditional transaction end instruction
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Information Patent Grant
Conditional transaction end instruction
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- Issue date Aug 9, 2016
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Information Patent Grant
Systems, apparatuses, and methods for determining a trailing least...
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- Issue date Apr 26, 2016
- Intel Corporation
- Christopher J. Hughes
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Information Patent Grant
Instruction boundary prediction for variable length instruction set
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- Issue date Dec 29, 2015
- Intel Corporation
- Mauricio Breternitz
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Information Patent Grant
Assembling long instruction encapsulated in short instructions acco...
- Patent number 9,152,421
- Issue date Oct 6, 2015
- QUALCOMM Incorporated
- Peter Smith
- G06 - COMPUTING CALCULATING COUNTING

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Determining start or end of instruction; determining instruction length

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Circuitry and methods for power efficient generation of length mark...

Wavefront selection and execution

Wavefront selection and execution

Dynamic designation of instructions as sensitive for constraining i...

Parallel instruction demarcator

Fixed-size pool storage for handling out-of order receipt of data

Processor having a register file, processing unit, and instruction...

Encoding and decoding variable length instructions

AI synaptic coprocessor

Non-transitory computer-readable medium, analysis device, and analy...

Wavefront selection and execution

AI synaptic coprocessor

Instruction packing scheme for VLIW CPU architecture

Encoding and decoding variable length instructions

Processing method, device, equipment and storage medium of loop ins...

Dynamic designation of instructions as sensitive for constraining m...

Instruction length based parallel instruction demarcator

Conditional transaction end instruction

Electronic apparatus, VLIW processor and control methods for updati...

Conditional transaction end instruction

Electronic apparatus, VLIW processor and control methods for updati...

Conditional transaction end instruction

Reordering buffer for memory access locality

Indicating a length of an instruction of a variable length instruct...

Conditional transaction end instruction

Conditional transaction end instruction

Conditional transaction end instruction

Systems, apparatuses, and methods for determining a trailing least...

Instruction boundary prediction for variable length instruction set

Assembling long instruction encapsulated in short instructions acco...

Patents Applicationslast 30 patents

CLIPPING OPERATIONS USING PARTIAL CLIP INSTRUCTIONS

INSTRUCTION LENGTH BASED PARALLEL INSTRUCTION DEMARCATOR

AI SYNAPTIC COPROCESSOR

INTERLEAVED MACHINE INSTRUCTION PLACEMENT IN MEMORY

WAVEFRONT SELECTION AND EXECUTION

INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE

AI SYNAPTIC COPROCESSOR

SYSTEMS AND METHODS FOR PROCESSING OUT-OF-ORDER EVENTS

NON-TRANSITORY COMPUTER-READABLE MEDIUM, ANALYSIS DEVICE, AND ANALY...

WAVEFRONT SELECTION AND EXECUTION

Encoding and Decoding Variable Length Instructions

ADDRESS GENERATION METHOD, RELATED APPARATUS, AND STORAGE MEDIUM

INSTRUCTION PACKING SCHEME FOR VLIW CPU ARCHITECTURE

AI SYNAPTIC COPROCESSOR

Dynamic Designation of Instructions as Sensitive for Constraining I...

INSTRUCTION LENGTH BASED PARALLEL INSTRUCTION DEMARCATOR

PROCESSING METHOD, DEVICE, EQUIPMENT AND STORAGE MEDIUM OF LOOP INS...

Dynamic Designation of Instructions as Sensitive

METHOD, APPARATUS AND TERMINAL DEVICE FOR ACQUIRING APPLICATION INT...

INSTRUCTION FUSION USING DEPENDENCE ANALYSIS

DATA LOADING AND STORAGE INSTRUCTION PROCESSING METHOD AND DEVICE

INSTRUCTION SET ARCHITECTURE TRANSFORMATIONS WHEN EMULATING NON-TRA...

Method for Accessing Memory of Multi-Core System, Related Apparatus...

CONDITIONAL TRANSACTION END INSTRUCTION

SYSTEM AND METHOD FOR AUTOMATED AGGREGATION OF SYSTEM INFORMATION F...

CONDITIONAL TRANSACTION END INSTRUCTION

ELECTRONIC APPARATUS, VLIW PROCESSOR AND CONTROL METHODS THEREOF

Hardware apparatuses and methods for data decompression

CONDITIONAL TRANSACTION END INSTRUCTION

INSTRUCTION BOUNDARY PREDICTION FOR VARIABLE LENGTH INSTRUCTION SET