Hit rate improvement

Industry

CPC
G06F2212/1021

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures

Current Industry

G06F2212/1021Hit rate improvement

Industries

Please log in for detailed analytics

Patents Grantslast 30 patents

Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for increasing cache hit rates for neural networks
- Patent number 12,265,908
- Issue date Apr 1, 2025
- Advanced Micro Devices, Inc.
- Benjamin Thomas Sander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for software multicore optimization
- Patent number 12,265,471
- Issue date Apr 1, 2025
- C SQUARED IP HOLDINGS LLC
- Kevin David Howard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing data using persistent storage
- Patent number 12,253,952
- Issue date Mar 18, 2025
- TWILIO INC.
- Christopher O'Hara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for cache management in a network device
- Patent number 12,253,946
- Issue date Mar 18, 2025
- Telefonaktiebolaget LM Ericsson (publ)
- Anju Thomas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for memory bandwidth allocation
- Patent number 12,248,400
- Issue date Mar 11, 2025
- Alibaba (China) Co., Ltd.
- Lide Duan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient logical to physical mapping updates
- Patent number 12,242,386
- Issue date Mar 4, 2025
- Western Digital Technologies, Inc.
- Dinesh Kumar Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a transient cache list and prolonged cache list to manage tra...
- Patent number 12,235,775
- Issue date Feb 25, 2025
- International Business Machines Corporation
- Beth Ann Peterson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Criticality-informed caching policies with multiple criticality levels
- Patent number 12,235,769
- Issue date Feb 25, 2025
- Apple Inc.
- Tyler J. Huberty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Message call request data having error frequency metrics
- Patent number 12,235,716
- Issue date Feb 25, 2025
- ADP, Inc.
- Anand Muralidharan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Insertion/promotion vectors to update replacement data in caches ba...
- Patent number 12,222,875
- Issue date Feb 11, 2025
- Apple Inc.
- Tyler J. Huberty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information processing system and memory system
- Patent number 12,210,458
- Issue date Jan 28, 2025
- Kioxia Corporation
- Tomoya Suzuki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-stalling, non-blocking translation lookaside buffer invalidation
- Patent number 12,210,459
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Daniel Brad Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data cache region prefetcher
- Patent number 12,204,459
- Issue date Jan 21, 2025
- Advanced Micro Devices, Inc.
- Donald W. McCauley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache support for indirect loads and indirect stores in graph appli...
- Patent number 12,204,901
- Issue date Jan 21, 2025
- Intel Corporation
- Robert Pawlowski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence signaling protocol
- Patent number 12,197,331
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for adjusting data storage and computer device
- Patent number 12,174,740
- Issue date Dec 24, 2024
- Shanghai Bilibili Technology Co., Ltd.
- Sheng Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache data provided based on data availability
- Patent number 12,164,433
- Issue date Dec 10, 2024
- Microsoft Technology Licensing, LLC
- Ahmed Abdelsalam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and device for data caching
- Patent number 12,153,522
- Issue date Nov 26, 2024
- Samsung Electronics Co., Ltd.
- Yangxu Zhou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Preemptive Flushing of Processing-in-Memory Data Structures
- Publication number 20250110887
- Publication date Apr 3, 2025
- ADVANCED MICRO DEVICES, INC.
- David Andrew Werner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE LOOKUP RESPONSE FILTERING
- Publication number 20250110874
- Publication date Apr 3, 2025
- ARM Limited
- Fabrice Jean VERPLANKEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BRANCH TARGET BUFFER RUN-AHEAD
- Publication number 20250110882
- Publication date Apr 3, 2025
- Microsoft Technology Licensing, LLC
- Julio Gago Alonso
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...
- Publication number 20250061060
- Publication date Feb 20, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS M...
- Publication number 20250053511
- Publication date Feb 13, 2025
- Next Silicon Ltd
- Dan SHECHTER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOOM-BASED HIT PREDICTOR
- Publication number 20250045206
- Publication date Feb 6, 2025
- ADVANCED MICRO DEVICES, INC.
- Patrick J. Shyvers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE SHARED STATE SUPPRESSION
- Publication number 20250013569
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR SOFTWARE MULTICORE OPTIMIZATION
- Publication number 20250013571
- Publication date Jan 9, 2025
- C Squared IP Holdings LLC
- Kevin David HOWARD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, DEVICE, AND COMPUTER PROGRAM PRODUCT FOR STORING DATA
- Publication number 20240394184
- Publication date Nov 28, 2024
- Dell Products L.P.
- Hailan Dong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Configuration of Address Translation Cache
- Publication number 20240345963
- Publication date Oct 17, 2024
- MELLANOX TECHNOLOGIES, LTD.
- Gal Shalom
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART
- Publication number 20240320094
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A TRANSIENT CACHE LIST AND PROLONGED CACHE LIST TO MANAGE TRA...
- Publication number 20240303206
- Publication date Sep 12, 2024
- International Business Machines Corporation
- Beth Ann PETERSON
- G06 - COMPUTING CALCULATING COUNTING

Hit rate improvement

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Hybrid victim cache and write miss buffer with fence operation

Methods for increasing cache hit rates for neural networks

Method and system for software multicore optimization

Methods and apparatus for multi-banked victim cache with dual datapath

Managing data using persistent storage

Method and system for cache management in a network device

Systems and methods for memory bandwidth allocation

Efficient logical to physical mapping updates

Data initialization techniques

Using a transient cache list and prolonged cache list to manage tra...

Criticality-informed caching policies with multiple criticality levels

Message call request data having error frequency metrics

Insertion/promotion vectors to update replacement data in caches ba...

Atomic compare and swap in a coherent cache system

Information processing system and memory system

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Non-stalling, non-blocking translation lookaside buffer invalidation

Graphics processor data access and sharing

Data cache region prefetcher

Cache support for indirect loads and indirect stores in graph appli...

Methods and apparatus to reduce bank pressure using aggressive writ...

Hardware coherence signaling protocol

Fully pipelined read-modify-write support

Multi-tile memory management

Methods and apparatus for allocation in a victim cache system

Method and apparatus for adjusting data storage and computer device

Cache data provided based on data availability

Method and device for data caching

Cache structure and utilization

Patents Applicationslast 30 patents

Preemptive Flushing of Processing-in-Memory Data Structures

CACHE LOOKUP RESPONSE FILTERING

BRANCH TARGET BUFFER RUN-AHEAD

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...

SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS M...

BLOOM-BASED HIT PREDICTOR

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

CACHE COHERENCE SHARED STATE SUPPRESSION

METHOD AND SYSTEM FOR SOFTWARE MULTICORE OPTIMIZATION

MULTI-TILE MEMORY MANAGEMENT

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

CACHE STRUCTURE AND UTILIZATION

COMPRESSION TECHNIQUES

METHOD, DEVICE, AND COMPUTER PROGRAM PRODUCT FOR STORING DATA

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

Adaptive Configuration of Address Translation Cache

STREAMING ENGINE WITH ERROR DETECTION, CORRECTION AND RESTART

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

USING A TRANSIENT CACHE LIST AND PROLONGED CACHE LIST TO MANAGE TRA...