Implementation on processors

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CPC
H03M13/6569

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HELECTRICITY H03Electronic circuits H03MCODING DECODING CODE CONVERSION IN GENERAL H03M13/00Coding, decoding or code conversion, for error detection or error correction Coding theory basic assumptions Coding bounds Error probability evaluation methods Channel models Simulation or testing of codes

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H03M13/6569Implementation on processors

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Optimized implementation of (DE−)interleaving and rate (DE−)matchin...
- Patent number 11,811,423
- Issue date Nov 7, 2023
- Telefonaktiebolaget LM Ericsson (publ)
- Qingchao Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Optimized implementation of (de-)interleaving and rate (de-)matchin...
- Patent number 11,290,130
- Issue date Mar 29, 2022
- Telefonaktiebolaget LM Ericsson (publ)
- Qingchao Liu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Program flow monitoring for deterministic firmware functions
- Patent number 11,277,150
- Issue date Mar 15, 2022
- Infineon Technologies AG
- Bernhard Gstoettenbauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Storage system and method for interleaving data for enhanced qualit...
- Patent number 11,221,950
- Issue date Jan 11, 2022
- Western Digital Technologies, Inc.
- Ramanathan Muthiah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying the correctness of a deflate compression accelerator
- Patent number 11,031,951
- Issue date Jun 8, 2021
- International Business Machines Corporation
- Timothy Slegel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying the correctness of a deflate compression accelerator
- Patent number 10,985,778
- Issue date Apr 20, 2021
- International Business Machines Corporation
- Timothy Siegel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Verifying the correctness of a deflate compression accelerator
- Patent number 10,944,423
- Issue date Mar 9, 2021
- International Business Machines Corporation
- Timothy Siegel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flexible error correction
- Patent number 10,608,674
- Issue date Mar 31, 2020
- Sequans Communications S.A.
- Guillaume Vivier
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Program flow monitoring for deterministic firmware functions
- Patent number 10,536,168
- Issue date Jan 14, 2020
- Infineon Technologies AG
- Bernhard Gstoettenbauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Self-addressing memory
- Patent number 10,331,361
- Issue date Jun 25, 2019
- National Instruments Corporation
- Tai A. Ly
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for layered storage of enterprise data
- Patent number 10,089,009
- Issue date Oct 2, 2018
- INURON
- Kurt Glazemakers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system configured to avoid memory access hazards for LDPC de...
- Patent number 10,078,456
- Issue date Sep 18, 2018
- National Instruments Corporation
- Tai A. Ly
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-configurable device for interleaving/deinterleaving data frames
- Patent number 9,971,684
- Issue date May 15, 2018
- Universite de Bretagne Sud
- Philippe Coussy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power low-density parity-check decoding
- Patent number 9,935,654
- Issue date Apr 3, 2018
- Alcatel-Lucent USA Inc.
- Behnam Sedighi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems, methods, and computer readable media for digital radio bro...
- Patent number 9,842,048
- Issue date Dec 12, 2017
- iBiquity Digital Corporation
- Marek Milbar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configuring circuitry with memory access constraints for a program
- Patent number 9,740,411
- Issue date Aug 22, 2017
- National Instruments Corporation
- Tai A. Ly
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Self-addressing memory
- Patent number 9,569,119
- Issue date Feb 14, 2017
- National Instruments Corporation
- Tai A. Ly
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multicore type error correction processing system and error correct...
- Patent number 9,250,996
- Issue date Feb 2, 2016
- NEC Corporation
- Tomoyoshi Kobori
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel processing of overlapping subsequences to generate soft es...
- Patent number 9,252,920
- Issue date Feb 2, 2016
- Coherent Logix, Incorporated
- David B. Drumm
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems, methods, and computer readable media for digital radio bro...
- Patent number 9,203,668
- Issue date Dec 1, 2015
- iBiquity Digital Corporation
- Marek Milbar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Parallel execution of trellis-based methods using overlapping sub-s...
- Patent number 9,008,242
- Issue date Apr 14, 2015
- Coherent Logix, Incorporated
- David B. Drumm
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low latency SIMD architecture for iterative decoders
- Patent number 8,908,814
- Issue date Dec 9, 2014
- Marvell World Trade Ltd.
- Neelmani Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Flexible channel decoder
- Patent number 8,879,670
- Issue date Nov 4, 2014
- Agence Spatiale Europeenne
- Giuseppe Gentile
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Recursion unit scheduling
- Patent number 8,848,842
- Issue date Sep 30, 2014
- Xilinx, Inc.
- Christopher H. Dick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Data input and output method of NAND flash memory and embedded syst...
- Patent number 8,850,291
- Issue date Sep 30, 2014
- Electronics and Telecommunications Research Institute
- Dong Wook Kang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Parallel execution of trellis-based methods
- Patent number 8,761,318
- Issue date Jun 24, 2014
- Coherent Logix, Incorporated
- David B. Drumm
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Processor instructions to accelerate Viterbi decoding
- Patent number 8,694,878
- Issue date Apr 8, 2014
- Texas Instruments Incorporated
- Prohor Chowdhury
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Systems and methods for non-binary decoding biasing control
- Patent number 8,661,324
- Issue date Feb 25, 2014
- LSI Corporation
- Shaohua Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Parallel execution of trellis-based methods
- Patent number 8,644,431
- Issue date Feb 4, 2014
- Coherent Logix, Incorporated
- David B. Drumm
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Optimized Viterbi decoder and GNSS receiver
- Patent number 8,621,335
- Issue date Dec 31, 2013
- QUALCOMM Incorporated
- Philip John Young
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING AND RATE (DE-)MATCHIN...
- Publication number 20220263522
- Publication date Aug 18, 2022
- Telefonaktiebolaget LM Ericsson (publ)
- Qingchao LIU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING AND RATE (DE-)MATCHIN...
- Publication number 20210320675
- Publication date Oct 14, 2021
- Telefonaktiebolaget LM Ericsson (publ)
- Qingchao LIU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
VERIFYING THE CORRECTNESS OF A DEFLATE COMPRESSION ACCELERATOR
- Publication number 20200295780
- Publication date Sep 17, 2020
- International Business Machines Corporation
- Timothy Slegel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFYING THE CORRECTNESS OF A DEFLATE COMPRESSION ACCELERATOR
- Publication number 20200295781
- Publication date Sep 17, 2020
- International Business Machines Corporation
- Timothy Slegel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAM FLOW MONITORING FOR DETERMINISTIC FIRMWARE FUNCTIONS
- Publication number 20200153455
- Publication date May 14, 2020
- INFINEON TECHNOLOGIES AG
- Bernhard Gstoettenbauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAM FLOW MONITORING FOR DETERMINISTIC FIRMWARE FUNCTIONS
- Publication number 20180131387
- Publication date May 10, 2018
- INFINEON TECHNOLOGIES AG
- Bernhard Gstoettenbauer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR LAYERED STORAGE OF ENTERPRISE DATA
- Publication number 20170123675
- Publication date May 4, 2017
- iNuron
- Kurt GLAZEMAKERS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel Execution of Trellis-Based Methods Using Overlapping Sub-S...
- Publication number 20140247910
- Publication date Sep 4, 2014
- COHERENT LOGIX INCORPORATED
- David B. Drumm
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RECURSION UNIT SCHEDULING
- Publication number 20140050286
- Publication date Feb 20, 2014
- Xilinx, Inc.
- Christopher H. Dick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MULTICORE TYPE ERROR CORRECTION PROCESSING SYSTEM AND ERROR CORRECT...
- Publication number 20140040700
- Publication date Feb 6, 2014
- Tomoyoshi Kobori
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Flexible Channel Decoder
- Publication number 20130156133
- Publication date Jun 20, 2013
- Giuseppe Gentile
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Parallel Execution of Trellis-Based Methods
- Publication number 20130121447
- Publication date May 16, 2013
- COHERENT LOGIX INCORPORATED
- David B. Drumm
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Systems and Methods for Non-Binary Decoding Biasing Control
- Publication number 20130067297
- Publication date Mar 14, 2013
- LSI CORPORATION
- Shaohua Yang
- G11 - INFORMATION STORAGE
Information Patent Application
Processor Instructions to Accelerate Viterbi Decoding
- Publication number 20120324318
- Publication date Dec 20, 2012
- Prohor Chowdhury
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
LOW LATENCY SIMD ARCHITECTURE FOR ITERATIVE DECODERS
- Publication number 20120177152
- Publication date Jul 12, 2012
- Neelmani KUMAR
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DATA INPUT AND OUTPUT METHOD OF NAND FLASH MEMORY AND EMBEDDED SYST...
- Publication number 20120096333
- Publication date Apr 19, 2012
- ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
- Dong Wook KANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR VITERBI DECODING USING APPLICATION SPECIFIC E...
- Publication number 20110231741
- Publication date Sep 22, 2011
- NXP B.V.
- Xavier Chabot
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Systems, methods, and computer readable media for digital radio bro...
- Publication number 20110026640
- Publication date Feb 3, 2011
- iBiquity Digital Corporation
- Marek Milbar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Parallel Execution of Trellis-Based Methods
- Publication number 20100322358
- Publication date Dec 23, 2010
- David B. Drumm
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Programmable CRC Unit
- Publication number 20100313104
- Publication date Dec 9, 2010
- MICROCHIP TECHNOLOGY INCORPORATED
- Sudhir Bommena
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Receiver Equipped with a Trellis Viterbi Decoder
- Publication number 20100313103
- Publication date Dec 9, 2010
- THALES
- Pierre-Yves Dumas
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
OPTIMIZED VITERBI DECODER AND GNSS RECEIVER
- Publication number 20100299583
- Publication date Nov 25, 2010
- Qualcomm Incorporated
- Philip John Young
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ASIP ARCHITECTURE FOR EXECUTING AT LEAST TWO DECODING METHODS
- Publication number 20100268918
- Publication date Oct 21, 2010
- IMEC
- Robert Priewasser
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
MAXIMUM LIKELIHOOD DECODER AND INFORMATION REPRODUCTION APPARATUS
- Publication number 20100177615
- Publication date Jul 15, 2010
- Akira Yamamoto
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Contention-free parallel processing multimode LDPC decoder
- Publication number 20100146362
- Publication date Jun 10, 2010
- Samsung Electronics Co., Ltd.
- Eran Pisek
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Method and apparatus for software-defined radio LDPC decoder
- Publication number 20090319856
- Publication date Dec 24, 2009
- Samsung Electronics Co., Ltd.
- Eran Pisek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and apparatus for parallel processing multimode LDPC decoder
- Publication number 20090319857
- Publication date Dec 24, 2009
- Samsung Electronics Co., Ltd.
- Eran Pisek
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF C...
- Publication number 20090309770
- Publication date Dec 17, 2009
- Alexander Andreev
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LDPC CODES AND STOCHASTIC DECODING FOR OPTICAL TRANSMISSION
- Publication number 20090259912
- Publication date Oct 15, 2009
- NEC Laboratories America, Inc.
- IVAN B. DJORDJEVIC
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Methods and Apparatus for Reduced Complexity Soft-Output Viterbi De...
- Publication number 20090187813
- Publication date Jul 23, 2009
- Erich F. Haratsch
- H03 - BASIC ELECTRONIC CIRCUITRY

Implementation on processors

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Optimized implementation of (DE−)interleaving and rate (DE−)matchin...

Optimized implementation of (de-)interleaving and rate (de-)matchin...

Program flow monitoring for deterministic firmware functions

Storage system and method for interleaving data for enhanced qualit...

Verifying the correctness of a deflate compression accelerator

Verifying the correctness of a deflate compression accelerator

Verifying the correctness of a deflate compression accelerator

Flexible error correction

Program flow monitoring for deterministic firmware functions

Self-addressing memory

Method for layered storage of enterprise data

Memory system configured to avoid memory access hazards for LDPC de...

Self-configurable device for interleaving/deinterleaving data frames

Low power low-density parity-check decoding

Systems, methods, and computer readable media for digital radio bro...

Configuring circuitry with memory access constraints for a program

Self-addressing memory

Multicore type error correction processing system and error correct...

Parallel processing of overlapping subsequences to generate soft es...

Systems, methods, and computer readable media for digital radio bro...

Parallel execution of trellis-based methods using overlapping sub-s...

Low latency SIMD architecture for iterative decoders

Flexible channel decoder

Recursion unit scheduling

Data input and output method of NAND flash memory and embedded syst...

Parallel execution of trellis-based methods

Processor instructions to accelerate Viterbi decoding

Systems and methods for non-binary decoding biasing control

Parallel execution of trellis-based methods

Optimized Viterbi decoder and GNSS receiver

Patents Applicationslast 30 patents

OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING AND RATE (DE-)MATCHIN...

OPTIMIZED IMPLEMENTATION OF (DE-)INTERLEAVING AND RATE (DE-)MATCHIN...

VERIFYING THE CORRECTNESS OF A DEFLATE COMPRESSION ACCELERATOR

VERIFYING THE CORRECTNESS OF A DEFLATE COMPRESSION ACCELERATOR

PROGRAM FLOW MONITORING FOR DETERMINISTIC FIRMWARE FUNCTIONS

PROGRAM FLOW MONITORING FOR DETERMINISTIC FIRMWARE FUNCTIONS

METHOD FOR LAYERED STORAGE OF ENTERPRISE DATA

Parallel Execution of Trellis-Based Methods Using Overlapping Sub-S...

RECURSION UNIT SCHEDULING

MULTICORE TYPE ERROR CORRECTION PROCESSING SYSTEM AND ERROR CORRECT...

Flexible Channel Decoder

Parallel Execution of Trellis-Based Methods

Systems and Methods for Non-Binary Decoding Biasing Control

Processor Instructions to Accelerate Viterbi Decoding

LOW LATENCY SIMD ARCHITECTURE FOR ITERATIVE DECODERS

DATA INPUT AND OUTPUT METHOD OF NAND FLASH MEMORY AND EMBEDDED SYST...

SYSTEM AND METHOD FOR VITERBI DECODING USING APPLICATION SPECIFIC E...

Systems, methods, and computer readable media for digital radio bro...

Parallel Execution of Trellis-Based Methods

Programmable CRC Unit

Receiver Equipped with a Trellis Viterbi Decoder

OPTIMIZED VITERBI DECODER AND GNSS RECEIVER

ASIP ARCHITECTURE FOR EXECUTING AT LEAST TWO DECODING METHODS

MAXIMUM LIKELIHOOD DECODER AND INFORMATION REPRODUCTION APPARATUS

Contention-free parallel processing multimode LDPC decoder

Method and apparatus for software-defined radio LDPC decoder

Method and apparatus for parallel processing multimode LDPC decoder

METHODS AND APPARATUS FOR PROGRAMMABLE DECODING OF A PLURALITY OF C...

LDPC CODES AND STOCHASTIC DECODING FOR OPTICAL TRANSMISSION

Methods and Apparatus for Reduced Complexity Soft-Output Viterbi De...