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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F7/00Methods or arrangements for processing data by operating upon the order or content of the data handled

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Patents Grantslast 30 patents

Information Patent Grant
Adder circuit using lookup tables
- Patent number 11,960,857
- Issue date Apr 16, 2024
- Achronix Semiconductor Corporation
- Christopher C. LaFrieda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuit using lookup tables
- Patent number 11,714,607
- Issue date Aug 1, 2023
- Achronix Semiconductor Corporation
- Christopher LaFrieda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Protection of an iterative calculation
- Patent number 11,456,853
- Issue date Sep 27, 2022
- STMicroelectronics (Rousset) SAS
- Ibrahima Diop
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-serial linear algebra processor
- Patent number 11,275,713
- Issue date Mar 15, 2022
- International Business Machines Corporation
- Heiner Giefers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Connected devices information
- Patent number 10,585,674
- Issue date Mar 10, 2020
- Hewlett-Packard Development Company, L.P.
- Mark A. Piwonka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for processing data in an adder based circuit
- Patent number 10,402,166
- Issue date Sep 3, 2019
- Sony Corporation
- Jeremy Chatwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for a stage optimized high speed adder
- Patent number 10,282,170
- Issue date May 7, 2019
- Intel Corporation
- Mohammad Abdallah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-serial multiplier for FPGA applications
- Patent number 10,275,219
- Issue date Apr 30, 2019
- Embry. Riddle Aeronautical University, Inc.
- Akhan Almagambetov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and method for outer product accumulate operations
- Patent number 10,120,649
- Issue date Nov 6, 2018
- Microunity Systems Engineering, Inc.
- Craig Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transformation on input operands to reduce hardware overhead for im...
- Patent number 10,037,190
- Issue date Jul 31, 2018
- International Business Machines Corporation
- Mihir Choudhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for a stage optimized high speed adder
- Patent number 9,753,691
- Issue date Sep 5, 2017
- Intel Corporation
- Mohammad Abdallah
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Algorithm and architecture for multi-argument associative operation...
- Patent number 8,775,147
- Issue date Jul 8, 2014
- The MathWorks, Inc.
- Alireza Pakyari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Arithmetic or logical operation tree computation
- Patent number 8,326,909
- Issue date Dec 4, 2012
- NXP B.V.
- Bruno Ballarin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for decrypting serial transmission signal
- Patent number 8,259,943
- Issue date Sep 4, 2012
- HTC Corporation
- David Huang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Algorithm and architecture for multi-argument associative operation...
- Patent number 8,041,551
- Issue date Oct 18, 2011
- The MathWorks, Inc.
- Alireza Pakyari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary adder
- Patent number 6,711,604
- Issue date Mar 23, 2004
- British Telecommunications public limited company
- Alistair James Poustie
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Floating-point calculator
- Patent number 6,701,337
- Issue date Mar 2, 2004
- Kabushiki Kaisha Toshiba
- Nobuhiro Ide
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reconfigurable digit-serial arithmetic system having a plurality of...
- Patent number 6,230,175
- Issue date May 8, 2001
- Matsushita Electric Industrial Co., Ltd.
- Tadashi Okamoto
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Small, fast CMOS 4-2 carry-save adder cell
- Patent number 5,818,747
- Issue date Oct 6, 1998
- Sun Microsystems, Inc.
- Ming G. Wong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital data processing circuit
- Patent number 5,189,635
- Issue date Feb 23, 1993
- Sony Corporation
- Mitsuharu Ohki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Incrementing subtractive circuits
- Patent number 5,105,379
- Issue date Apr 14, 1992
- VLSI Technology, Inc.
- Stewart G. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary calculation circuit
- Patent number 4,920,509
- Issue date Apr 24, 1990
- Etat Francais, represente par le ministres Delegue des Postes et Telecommunic...
- Hedi Hmida
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bit-serial integrator circuitry
- Patent number 4,841,466
- Issue date Jun 20, 1989
- RCA Licensing Corporation
- Todd J. Christopher
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Amorphous semiconductor devices having increased switching speed du...
- Patent number 4,588,903
- Issue date May 13, 1986
- Energy Conversion Devices, Inc.
- Robert R. Johnson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Binary word processing method using a high-speed sequential adder
- Patent number 4,336,600
- Issue date Jun 22, 1982
- Thomson-CSF
- Jean-Pierre Houdard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital adder circuit with a plurality of 1-bit adders and improved...
- Patent number 4,285,047
- Issue date Aug 18, 1981
- Hitachi, Ltd.
- Makoto Ohnishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Asynchronous circuit and system
- Patent number 4,167,789
- Issue date Sep 11, 1979
- The Aiken Fund, Inc.
- Carlo Faustini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Electronic calculator or microprocessor having a hexadecimal/binary...
- Patent number 4,125,867
- Issue date Nov 14, 1978
- Texas Instruments Incorporated
- Michael J. Cochran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Digital function generator
- Patent number 3,962,573
- Issue date Jun 8, 1976
- Rockwell International Corporation
- Lewis E. Staley
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Series type adder for adding plural binary numbers
- Patent number 3,941,990
- Issue date Mar 2, 1976
- Compagnie Industrielle des Telecommunications Cit-Alcatel
- Jean Rabasse
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
FLEXIBLE HARDWARE ACCELERATORS FOR MASKING CONVERSIONS WITH A POWER...
- Publication number 20240338492
- Publication date Oct 10, 2024
- NXP B.V.
- Olivier Bronchain
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDER CIRCUIT USING LOOKUP TABLES
- Publication number 20240281212
- Publication date Aug 22, 2024
- Achronix Semiconductor Corporation
- Christopher C. LaFrieda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR OPERATING MEMORY PROCESSOR
- Publication number 20240103809
- Publication date Mar 28, 2024
- Samsung Electronics Co., Ltd.
- Dong-Jin CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPUTE-IN MEMORY (CIM) DEVICE AND COMPUTING METHOD THEREOF
- Publication number 20230333814
- Publication date Oct 19, 2023
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Jui-Che TSAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDER CIRCUIT USING LOOKUP TABLES
- Publication number 20230315390
- Publication date Oct 5, 2023
- Christopher C. LaFrieda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDER CIRCUIT USING LOOKUP TABLES
- Publication number 20220206758
- Publication date Jun 30, 2022
- Achronix Semiconductor Corporation
- Christopher LaFrieda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROTECTION OF AN ITERATIVE CALCULATION
- Publication number 20200313846
- Publication date Oct 1, 2020
- STMicroelectronics (Rousset) SAS
- Ibrahima DIOP
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT-SERIAL LINEAR ALGEBRA PROCESSOR
- Publication number 20190377707
- Publication date Dec 12, 2019
- International Business Machines Corporation
- Heiner Giefers
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR AND METHOD FOR OUTER PRODUCT ACCUMULATE OPERATIONS
- Publication number 20190065149
- Publication date Feb 28, 2019
- MicroUnity Systems Engineering, Inc.
- Craig Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONNECTED DEVICES INFORMATION
- Publication number 20190056959
- Publication date Feb 21, 2019
- Hewlett-Packard Development Company, L.P.
- Mark A. PIWONKA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT-SERIAL MULTIPLIER FOR FPGA APPLICATIONS
- Publication number 20180129475
- Publication date May 10, 2018
- Embry-Riddle Aeronautical University, Inc.
- Akhan Almagambetov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR AND METHOD FOR OUTER PRODUCT ACCUMULATE OPERATIONS
- Publication number 20180032312
- Publication date Feb 1, 2018
- MicroUnity Systems Engineering, Inc.
- Craig Hansen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR A STAGE OPTIMIZED HIGH SPEED ADDER
- Publication number 20170322772
- Publication date Nov 9, 2017
- Intel Corporation
- Mohammad Abdallah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Transformation on Input Operands to Reduce Hardware Overhead for Im...
- Publication number 20170277515
- Publication date Sep 28, 2017
- International Business Machines Corporation
- Mihir Choudhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PROCESSING DATA IN AN ADDER BASED CIRCUIT
- Publication number 20170228215
- Publication date Aug 10, 2017
- SONY CORPORATION
- JEREMY CHATWIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR A STAGE OPTIMIZED HIGH SPEED ADDER
- Publication number 20140324937
- Publication date Oct 30, 2014
- SOFT MACHINES, INC.
- Mohammad Abdallah
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TERMINAL AND APPLICATION EXECUTION METHOD THEREOF
- Publication number 20130050229
- Publication date Feb 28, 2013
- Samsung Electronics Co., Ltd.
- Jeongig Song
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPERATION AND CONSTRUCTION OF ELECTRIC POWER CONSUMING FACILITIES U...
- Publication number 20100262310
- Publication date Oct 14, 2010
- Wilsun Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARITHMETIC OR LOGICAL OPERATION TREE COMPUTATION
- Publication number 20090271464
- Publication date Oct 29, 2009
- Koninklijke Philips Electronics N.V.
- Bruno Ballarin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Serial Adder Based On "No-Carry" Addition
- Publication number 20090106337
- Publication date Apr 23, 2009
- Rada Ruth Higgins
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR DECRYPTING SERIAL TRANSMISSION SIGNAL
- Publication number 20090074186
- Publication date Mar 19, 2009
- HTC CORPORATION
- David HUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Variable clocked heterogeneous serial array processor
- Publication number 20070226455
- Publication date Sep 27, 2007
- Laurence Hager Cooke
- G06 - COMPUTING CALCULATING COUNTING

in bit-serial fashion

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Adder circuit using lookup tables

Adder circuit using lookup tables

Protection of an iterative calculation

Bit-serial linear algebra processor

Connected devices information

System and method for processing data in an adder based circuit

Method for a stage optimized high speed adder

Bit-serial multiplier for FPGA applications

Processor and method for outer product accumulate operations

Transformation on input operands to reduce hardware overhead for im...

Method for a stage optimized high speed adder

Algorithm and architecture for multi-argument associative operation...

Arithmetic or logical operation tree computation

Method for decrypting serial transmission signal

Algorithm and architecture for multi-argument associative operation...

Binary adder

Floating-point calculator

Reconfigurable digit-serial arithmetic system having a plurality of...

Small, fast CMOS 4-2 carry-save adder cell

Digital data processing circuit

Incrementing subtractive circuits

Binary calculation circuit

Bit-serial integrator circuitry

Amorphous semiconductor devices having increased switching speed du...

Binary word processing method using a high-speed sequential adder

Digital adder circuit with a plurality of 1-bit adders and improved...

Asynchronous circuit and system

Electronic calculator or microprocessor having a hexadecimal/binary...

Digital function generator

Series type adder for adding plural binary numbers

Patents Applicationslast 30 patents

FLEXIBLE HARDWARE ACCELERATORS FOR MASKING CONVERSIONS WITH A POWER...

ADDER CIRCUIT USING LOOKUP TABLES

METHOD AND APPARATUS FOR OPERATING MEMORY PROCESSOR

COMPUTE-IN MEMORY (CIM) DEVICE AND COMPUTING METHOD THEREOF

ADDER CIRCUIT USING LOOKUP TABLES

ADDER CIRCUIT USING LOOKUP TABLES

PROTECTION OF AN ITERATIVE CALCULATION

BIT-SERIAL LINEAR ALGEBRA PROCESSOR

PROCESSOR AND METHOD FOR OUTER PRODUCT ACCUMULATE OPERATIONS

CONNECTED DEVICES INFORMATION

BIT-SERIAL MULTIPLIER FOR FPGA APPLICATIONS

PROCESSOR AND METHOD FOR OUTER PRODUCT ACCUMULATE OPERATIONS

METHOD FOR A STAGE OPTIMIZED HIGH SPEED ADDER

Transformation on Input Operands to Reduce Hardware Overhead for Im...

SYSTEM AND METHOD FOR PROCESSING DATA IN AN ADDER BASED CIRCUIT

METHOD FOR A STAGE OPTIMIZED HIGH SPEED ADDER

TERMINAL AND APPLICATION EXECUTION METHOD THEREOF

OPERATION AND CONSTRUCTION OF ELECTRIC POWER CONSUMING FACILITIES U...

ARITHMETIC OR LOGICAL OPERATION TREE COMPUTATION

Serial Adder Based On "No-Carry" Addition

METHOD FOR DECRYPTING SERIAL TRANSMISSION SIGNAL

Variable clocked heterogeneous serial array processor