in I/O circuitry

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CPC
G11C29/022

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

Current Industry

G11C29/022in I/O circuitry

Industries

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Patents Grantslast 30 patents

Information Patent Grant
On-die termination of address and command signals
- Patent number 12,249,399
- Issue date Mar 11, 2025
- RAMBUS INC.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed test of functional memory interface logic in devices
- Patent number 12,243,603
- Issue date Mar 4, 2025
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, memory system, and read operation method thereof
- Patent number 12,230,342
- Issue date Feb 18, 2025
- Yangtze Memory Technologies Co., Ltd.
- Hongtao Liu
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for supporting command bus training mode and method o...
- Patent number 12,217,823
- Issue date Feb 4, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device, memory system, and operation method of memory device
- Patent number 12,211,581
- Issue date Jan 28, 2025
- Samsung Electronics Co., Ltd.
- Donghun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for testing inaccessible interface circuits i...
- Patent number 12,196,805
- Issue date Jan 14, 2025
- RAMBUS INC.
- Frederick A. Ware
- G01 - MEASURING TESTING
Information Patent Grant
Dynamic random access memory built-in self-test power fail mitigation
- Patent number 12,190,979
- Issue date Jan 7, 2025
- Intel Corporation
- Bill Nale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data storage apparatus comprising cell section operable as dosimete...
- Patent number 12,183,410
- Issue date Dec 31, 2024
- ams International AG
- Tommaso Vincenzi
- G11 - INFORMATION STORAGE
Information Patent Grant
Block family error avoidance bin scans after memory device power-on
- Patent number 12,183,413
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Guang Hu
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses and methods for identifying memory devices of a semicon...
- Patent number 12,184,280
- Issue date Dec 31, 2024
- Dean Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable memory timing
- Patent number 12,176,061
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Kang-Yong Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit and operation method and inspection method thereof
- Patent number 12,119,073
- Issue date Oct 15, 2024
- Aspeed Technology Inc.
- Hung-Ming Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Efficient soft decoding of error correction code via extrinsic bit...
- Patent number 12,119,075
- Issue date Oct 15, 2024
- Kioxia Corporation
- Avi Steiner
- G11 - INFORMATION STORAGE
Information Patent Grant
Low-power source-synchronous signaling
- Patent number 12,119,042
- Issue date Oct 15, 2024
- RAMBUS INC.
- Jared L. Zerbe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device including error correction device
- Patent number 12,100,466
- Issue date Sep 24, 2024
- SK Hynix Inc.
- Jin Ho Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Mediating directed refresh management induced row hammer and row ac...
- Patent number 12,086,270
- Issue date Sep 10, 2024
- Micron Technology, Inc.
- Yang Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of error correction code (ECC) decoding and memory system pe...
- Patent number 12,080,366
- Issue date Sep 3, 2024
- Samsung Electronics Co., Ltd.
- Kangseok Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile memory including on-die-termination circuit and storage...
- Patent number 12,073,898
- Issue date Aug 27, 2024
- Samsung Electronics Co., Ltd.
- Eun-Ji Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage calibration scans to reduce memory device overhead
- Patent number 12,057,185
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory block programming using defectivity information
- Patent number 12,051,479
- Issue date Jul 30, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer circuit with adaptive repair capability
- Patent number 12,040,035
- Issue date Jul 16, 2024
- RAMBUS INC.
- Scott C. Best
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for receiver equalization and stressed eye testin...
- Patent number 12,032,018
- Issue date Jul 9, 2024
- Huawei Technologies Co., Ltd.
- Gang Zhao
- G11 - INFORMATION STORAGE
Information Patent Grant
Continuous adaptive data capture optimization for interface circuits
- Patent number 12,019,573
- Issue date Jun 25, 2024
- Uniquify, Inc.
- Jung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double data rate (DDR) memory controller apparatus and method
- Patent number 12,014,767
- Issue date Jun 18, 2024
- Uniquify, Inc.
- Mahesh Gopalan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for determining an interface connection status
- Patent number 12,014,787
- Issue date Jun 18, 2024
- Micron Technology, Inc.
- Melissa I. Uribe
- G11 - INFORMATION STORAGE
Information Patent Grant
On-die termination of address and command signals
- Patent number 12,002,540
- Issue date Jun 4, 2024
- RAMBUS INC.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices and systems with parallel impedance adjustment circu...
- Patent number 12,001,368
- Issue date Jun 4, 2024
- Hyun Yoo Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power signaling interface
- Patent number 11,996,160
- Issue date May 28, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data transmission using delayed timing signals
- Patent number 11,990,912
- Issue date May 21, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory systems with on-die data buffering
- Patent number 11,960,418
- Issue date Apr 16, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
BLOCK FAMILY ERROR AVOIDANCE BIN SCANS AFTER MEMORY DEVICE POWER-ON
- Publication number 20250087292
- Publication date Mar 13, 2025
- Micron Technology, Inc.
- Guang Hu
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICON...
- Publication number 20250070782
- Publication date Feb 27, 2025
- Lodestar Licensing Group LLC
- Dean Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
- Publication number 20250069644
- Publication date Feb 27, 2025
- Rambus Inc.
- Jared L. ZERBE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT AND METHOD OF OPERATING SAME
- Publication number 20250054562
- Publication date Feb 13, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Yu-Wei LIN
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT SOFT DECODING OF ERROR CORRECTION CODE VIA EXTRINSIC BIT...
- Publication number 20250037784
- Publication date Jan 30, 2025
- KIOXIA Corporation
- Avi Steiner
- G11 - INFORMATION STORAGE
Information Patent Application
On-Die Termination of Address and Command Signals
- Publication number 20250037746
- Publication date Jan 30, 2025
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
EVOLVING BAD BLOCK DETECTION IN NON-VOLATILE MEMORY
- Publication number 20250006285
- Publication date Jan 2, 2025
- Western Digital Technologies, Inc.
- Abhijith Prakash
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM, METHOD OF OPERATING MEMORY SYSTEM, AND COMPUTER-READ...
- Publication number 20240428873
- Publication date Dec 26, 2024
- Yangtze Memory Technologies Co., Ltd.
- Lingling MA
- G11 - INFORMATION STORAGE
Information Patent Application
BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY
- Publication number 20240420793
- Publication date Dec 19, 2024
- Rambus Inc.
- Scott C. Best
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD OF ERROR CORRECTION CODE (ECC) DECODING AND MEMORY SYSTEM PE...
- Publication number 20240395352
- Publication date Nov 28, 2024
- Samsung Electronics Co., Ltd.
- Kangseok Lee
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR HANDLING DURING A MEMORY COMPACTION PROCESS
- Publication number 20240386984
- Publication date Nov 21, 2024
- Western Digital Technologies, Inc.
- Ravi Dutt Sharma
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME
- Publication number 20240379184
- Publication date Nov 14, 2024
- WINBOND ELECTRONICS CORP.
- Yoshihisa MICHIOKA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND READING METHOD THEREOF
- Publication number 20240371455
- Publication date Nov 7, 2024
- Macronix International Co., Ltd.
- You-Liang CHOU
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND READING METHOD THEREOF
- Publication number 20240371456
- Publication date Nov 7, 2024
- Macronix International Co., Ltd.
- You-Liang CHOU
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE MEMORY INCLUDING ON-DIE-TERMINATION CIRCUIT AND STORAGE...
- Publication number 20240371457
- Publication date Nov 7, 2024
- Samsung Electronics Co., Ltd.
- Eun-Ji Kim
- G11 - INFORMATION STORAGE
Information Patent Application
DATA TRANSMISSION USING DELAYED TIMING SIGNALS
- Publication number 20240372542
- Publication date Nov 7, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN
- Publication number 20240363187
- Publication date Oct 31, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION
- Publication number 20240347128
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
FAILSAFE MEMORY CARD ARCHITECTURE USING VOLTAGE DRIVER OUTPUT ENABL...
- Publication number 20240347120
- Publication date Oct 17, 2024
- SANDISK TECHNOLOGIES LLC
- SHIV HARIT MATHUR
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20240345971
- Publication date Oct 17, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE BLOCK FAMILY ERROR AVOIDANCE SCAN BASED ON DYNAMIC PAGE ER...
- Publication number 20240339172
- Publication date Oct 10, 2024
- Micron Technology, Inc.
- Yugang Yu
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT READ DISTURB SCANNING
- Publication number 20240312554
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Chun Sum Yeung
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT SOFT DECODING OF ERROR CORRECTION CODE VIA EXTRINSIC BIT...
- Publication number 20240312552
- Publication date Sep 19, 2024
- KIOXIA Corporation
- Avi Steiner
- G11 - INFORMATION STORAGE
Information Patent Application
CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS
- Publication number 20240303209
- Publication date Sep 12, 2024
- Uniquify, Inc.
- Jung Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR DETERMINING AN INTERFACE CONNECTION STATUS
- Publication number 20240296897
- Publication date Sep 5, 2024
- Micron Technology, Inc.
- Melissa I. Uribe
- G11 - INFORMATION STORAGE
Information Patent Application
DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD
- Publication number 20240290372
- Publication date Aug 29, 2024
- Uniquify, Inc.
- Mahesh GOPALAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROTOCOL FOR MEMORY POWER-MODE CONTROL
- Publication number 20240282354
- Publication date Aug 22, 2024
- Rambus Inc.
- Wayne F. Ellis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROTECTING MEMORY CONTROLS AND ADDRESS
- Publication number 20240274218
- Publication date Aug 15, 2024
- Xilinx, Inc.
- David TRAN
- G11 - INFORMATION STORAGE
Information Patent Application
STORAGE DEVICES HAVING ENHANCED ERROR DETECTION AND MEMORY CELL REPAIR
- Publication number 20240257889
- Publication date Aug 1, 2024
- Samsung Electronics Co., Ltd.
- Dong KIM
- G11 - INFORMATION STORAGE
Information Patent Application
PAGE BUFFER BLOCK AND MEMORY DEVICE INCLUDING THE SAME
- Publication number 20240249794
- Publication date Jul 25, 2024
- Samsung Electronics Co., Ltd.
- Jaeyun Lee
- G11 - INFORMATION STORAGE

in I/O circuitry

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

On-die termination of address and command signals

At-speed test of functional memory interface logic in devices

Memory device, memory system, and read operation method thereof

Memory device for supporting command bus training mode and method o...

Memory device, memory system, and operation method of memory device

Methods and apparatus for testing inaccessible interface circuits i...

Dynamic random access memory built-in self-test power fail mitigation

Data storage apparatus comprising cell section operable as dosimete...

Block family error avoidance bin scans after memory device power-on

Apparatuses and methods for identifying memory devices of a semicon...

Programmable memory timing

Integrated circuit and operation method and inspection method thereof

Efficient soft decoding of error correction code via extrinsic bit...

Low-power source-synchronous signaling

Memory device including error correction device

Mediating directed refresh management induced row hammer and row ac...

Method of error correction code (ECC) decoding and memory system pe...

Nonvolatile memory including on-die-termination circuit and storage...

Voltage calibration scans to reduce memory device overhead

Memory block programming using defectivity information

Buffer circuit with adaptive repair capability

System and method for receiver equalization and stressed eye testin...

Continuous adaptive data capture optimization for interface circuits

Double data rate (DDR) memory controller apparatus and method

Techniques for determining an interface connection status

On-die termination of address and command signals

Memory devices and systems with parallel impedance adjustment circu...

Low power signaling interface

Data transmission using delayed timing signals

Semiconductor memory systems with on-die data buffering

Patents Applicationslast 30 patents

BLOCK FAMILY ERROR AVOIDANCE BIN SCANS AFTER MEMORY DEVICE POWER-ON

APPARATUSES AND METHODS FOR IDENTIFYING MEMORY DEVICES OF A SEMICON...

LOW-POWER SOURCE-SYNCHRONOUS SIGNALING

INTEGRATED CIRCUIT AND METHOD OF OPERATING SAME

EFFICIENT SOFT DECODING OF ERROR CORRECTION CODE VIA EXTRINSIC BIT...

On-Die Termination of Address and Command Signals

EVOLVING BAD BLOCK DETECTION IN NON-VOLATILE MEMORY

MEMORY SYSTEM, METHOD OF OPERATING MEMORY SYSTEM, AND COMPUTER-READ...

BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY

METHOD OF ERROR CORRECTION CODE (ECC) DECODING AND MEMORY SYSTEM PE...

ERROR HANDLING DURING A MEMORY COMPACTION PROCESS

SEMICONDUCTOR MEMORY DEVICE AND CONTROL METHOD OF THE SAME

MEMORY DEVICE AND READING METHOD THEREOF

MEMORY DEVICE AND READING METHOD THEREOF

NONVOLATILE MEMORY INCLUDING ON-DIE-TERMINATION CIRCUIT AND STORAGE...

DATA TRANSMISSION USING DELAYED TIMING SIGNALS

AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN

MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION

FAILSAFE MEMORY CARD ARCHITECTURE USING VOLTAGE DRIVER OUTPUT ENABL...

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

ADAPTIVE BLOCK FAMILY ERROR AVOIDANCE SCAN BASED ON DYNAMIC PAGE ER...

EFFICIENT READ DISTURB SCANNING

EFFICIENT SOFT DECODING OF ERROR CORRECTION CODE VIA EXTRINSIC BIT...

CONTINUOUS ADAPTIVE DATA CAPTURE OPTIMIZATION FOR INTERFACE CIRCUITS

TECHNIQUES FOR DETERMINING AN INTERFACE CONNECTION STATUS

DOUBLE DATA RATE (DDR) MEMORY CONTROLLER APPARATUS AND METHOD

PROTOCOL FOR MEMORY POWER-MODE CONTROL

PROTECTING MEMORY CONTROLS AND ADDRESS

STORAGE DEVICES HAVING ENHANCED ERROR DETECTION AND MEMORY CELL REPAIR

PAGE BUFFER BLOCK AND MEMORY DEVICE INCLUDING THE SAME