in which the counter of the loop counts between two different non zero numbers

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CPC
H03L7/195

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HELECTRICITY H03Electronic circuits H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES H03L7/00Automatic control of frequency or phase Synchronisation

Current Industry

H03L7/195in which the counter of the loop counts between two different non zero numbers

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Patents Grantslast 30 patents

Information Patent Grant
Methods and circuits for slew-rate calibration
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- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for PLL gain calibration
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- Apple Inc.
- Karim M Megawer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for PLL gain calibration and duty cycle calibra...
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- Issue date Oct 15, 2024
- Apple Inc.
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Information Patent Grant
Methods and apparatus for synchronizing data transfers across clock...
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- Issue date Apr 23, 2024
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Information Patent Grant
Phase locked circuit, method of operating the same, and transceiver
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- Issue date Jan 19, 2021
- Samsung Electronics Co., Ltd.
- Shinwoong Kim
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Information Patent Grant
Use of Frequency addition in a PLL control loop
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- Issue date Mar 31, 2015
- Ess Technology, Inc.
- Hu Jing Yao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for alteration of terminal counts of phase-lo...
- Patent number 6,597,246
- Issue date Jul 22, 2003
- DSP Group, Inc.
- Eric L. Unruh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frequency synthesizer incorporating vernier phase adjuster
- Patent number 5,256,980
- Issue date Oct 26, 1993
- PairGain Technologies, Inc.
- Benedict A. Itri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable divider
- Patent number 4,162,450
- Issue date Jul 24, 1979
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Information Patent Grant
Digital frequency synthesizer having selectable frequency offset be...
- Patent number 4,002,995
- Issue date Jan 11, 1977
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Information Patent Grant
Phase-locked loop transceiver having automatic frequency offset sel...
- Patent number 3,944,925
- Issue date Mar 16, 1976
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- Jon M. De Laune
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Information Patent Grant
3918006
- Patent number 3,918,006
- Issue date Nov 4, 1975
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
3538442
- Patent number 3,538,442
- Issue date Nov 3, 1970
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3431499
- Patent number 3,431,499
- Issue date Mar 4, 1969
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3375448
- Patent number 3,375,448
- Issue date Mar 26, 1968
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3286191
- Patent number 3,286,191
- Issue date Nov 15, 1966
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
FREQUENCY OFFSET OF A CLOCK SIGNAL
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SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION AND DUTY CYCLE CALIBRA...
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- Publication date Sep 19, 2024
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SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION
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- Publication date Sep 19, 2024
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METHOD AND AN APPARATUS FOR GENERATING AN OUTPUT CLOCK IN A MULTI-L...
- Publication number 20240297656
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- Xue-Mei Gong
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Use of Frequency Addition in a PLL Control Loop
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Methods and apparatus for alteration of terminal counts of phase-lo...
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- Eric L. Unruh
- H03 - BASIC ELECTRONIC CIRCUITRY

in which the counter of the loop counts between two different non zero numbers

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Methods and circuits for slew-rate calibration

Systems and methods for PLL gain calibration

Systems and methods for PLL gain calibration and duty cycle calibra...

Methods and apparatus for synchronizing data transfers across clock...

Phase locked circuit, method of operating the same, and transceiver

Use of Frequency addition in a PLL control loop

Methods and apparatus for alteration of terminal counts of phase-lo...

Frequency synthesizer incorporating vernier phase adjuster

Programmable divider

Digital frequency synthesizer having selectable frequency offset be...

Phase-locked loop transceiver having automatic frequency offset sel...

3918006

3538442

3431499

3375448

3286191

Patents Applicationslast 30 patents

FREQUENCY OFFSET OF A CLOCK SIGNAL

SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION AND DUTY CYCLE CALIBRA...

SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION

METHOD AND AN APPARATUS FOR GENERATING AN OUTPUT CLOCK IN A MULTI-L...

CLOCK SYNCHRONIZATION

CONTROL OF SKEW BETWEEN MULTIPLE DATA LANES

METHODS AND CIRCUITS FOR SLEW-RATE CALIBRATION

METHODS AND APPARATUS FOR SYNCHRONIZING DATA TRANSFERS ACROSS CLOCK...

PHASE LOCKED CIRCUIT, METHOD OF OPERATING THE SAME, AND TRANSCEIVER

CLOCK FREQUENCY DETECTION METHOD AND APPARATUS

Use of Frequency Addition in a PLL Control Loop

Methods and apparatus for alteration of terminal counts of phase-lo...