in which the counter of the loop counts between two different non zero numbers

Industry

CPC
H03L7/195

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

HELECTRICITY H03Electronic circuits H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES H03L7/00Automatic control of frequency or phase Synchronisation

Current Industry

H03L7/195in which the counter of the loop counts between two different non zero numbers

Industries

Patents Grantslast 30 patents

Information Patent Grant
Clock synchronization
- Patent number 12,278,642
- Issue date Apr 15, 2025
- NXP USA, INC.
- Ya-Wei Huang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and circuits for slew-rate calibration
- Patent number 12,166,485
- Issue date Dec 10, 2024
- RAMBUS INC.
- Cosmin Iorga
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for PLL gain calibration
- Patent number 12,132,490
- Issue date Oct 29, 2024
- Apple Inc.
- Karim M Megawer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Systems and methods for PLL gain calibration and duty cycle calibra...
- Patent number 12,119,830
- Issue date Oct 15, 2024
- Apple Inc.
- Jongmin Park
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for synchronizing data transfers across clock...
- Patent number 11,967,960
- Issue date Apr 23, 2024
- Advanced Micro Devices, Inc.
- David M. Dahle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase locked circuit, method of operating the same, and transceiver
- Patent number 10,897,259
- Issue date Jan 19, 2021
- Samsung Electronics Co., Ltd.
- Shinwoong Kim
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Use of Frequency addition in a PLL control loop
- Patent number 8,994,422
- Issue date Mar 31, 2015
- Ess Technology, Inc.
- Hu Jing Yao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatus for alteration of terminal counts of phase-lo...
- Patent number 6,597,246
- Issue date Jul 22, 2003
- DSP Group, Inc.
- Eric L. Unruh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Frequency synthesizer incorporating vernier phase adjuster
- Patent number 5,256,980
- Issue date Oct 26, 1993
- PairGain Technologies, Inc.
- Benedict A. Itri
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable divider
- Patent number 4,162,450
- Issue date Jul 24, 1979
- GTE Laboratories Incorporated
- Carl F. Buhrer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital frequency synthesizer having selectable frequency offset be...
- Patent number 4,002,995
- Issue date Jan 11, 1977
- Motorola, Inc.
- L. J. Reed
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase-locked loop transceiver having automatic frequency offset sel...
- Patent number 3,944,925
- Issue date Mar 16, 1976
- Motorola, Inc.
- Jon M. De Laune
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
3918006
- Patent number 3,918,006
- Issue date Nov 4, 1975
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
3538442
- Patent number 3,538,442
- Issue date Nov 3, 1970
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3431499
- Patent number 3,431,499
- Issue date Mar 4, 1969
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3375448
- Patent number 3,375,448
- Issue date Mar 26, 1968
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3286191
- Patent number 3,286,191
- Issue date Nov 15, 1966
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
METHODS AND CIRCUITS FOR SLEW-RATE CALIBRATION
- Publication number 20250141434
- Publication date May 1, 2025
- Rambus Inc.
- Cosmin Iorga
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME
- Publication number 20250119149
- Publication date Apr 10, 2025
- Samsung Electronics Co., Ltd.
- Tongsung Kim
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED PHASE-LOCKED LOOP (PLL) CIRCUITRY FOR MULTIPLE TRANSMISSION...
- Publication number 20250096807
- Publication date Mar 20, 2025
- QUALCOMM Incorporated
- Mustafa KESKIN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FREQUENCY OFFSET OF A CLOCK SIGNAL
- Publication number 20240333292
- Publication date Oct 3, 2024
- STMicroelectronics International N.V.
- Cao-Thong TU
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION AND DUTY CYCLE CALIBRA...
- Publication number 20240313787
- Publication date Sep 19, 2024
- Apple Inc.
- Jongmin Park
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION
- Publication number 20240313789
- Publication date Sep 19, 2024
- Apple Inc.
- Karim M Megawer
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHOD AND AN APPARATUS FOR GENERATING AN OUTPUT CLOCK IN A MULTI-L...
- Publication number 20240297656
- Publication date Sep 5, 2024
- Skyworks Solutions, Inc.
- Xue-Mei Gong
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK SYNCHRONIZATION
- Publication number 20240171185
- Publication date May 23, 2024
- NXP USA, Inc.
- Ya-Wei Huang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CONTROL OF SKEW BETWEEN MULTIPLE DATA LANES
- Publication number 20240039545
- Publication date Feb 1, 2024
- STMicroelectronics International N.V.
- Rupesh Singh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND CIRCUITS FOR SLEW-RATE CALIBRATION
- Publication number 20230080033
- Publication date Mar 16, 2023
- Rambus Inc.
- Cosmin Iorga
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
METHODS AND APPARATUS FOR SYNCHRONIZING DATA TRANSFERS ACROSS CLOCK...
- Publication number 20230035110
- Publication date Feb 2, 2023
- ADVANCED MICRO DEVICES, INC.
- David M. Dahle
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHASE LOCKED CIRCUIT, METHOD OF OPERATING THE SAME, AND TRANSCEIVER
- Publication number 20210013888
- Publication date Jan 14, 2021
- Samsung Electronics Co., Ltd.
- SHINWOONG KIM
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK FREQUENCY DETECTION METHOD AND APPARATUS
- Publication number 20180137276
- Publication date May 17, 2018
- Huawei Technologies Co., Ltd
- Qi Su
- G01 - MEASURING TESTING
Information Patent Application
Use of Frequency Addition in a PLL Control Loop
- Publication number 20140103977
- Publication date Apr 17, 2014
- ESS Technology, Inc.
- Hu Jing Yao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Methods and apparatus for alteration of terminal counts of phase-lo...
- Publication number 20020167359
- Publication date Nov 14, 2002
- Eric L. Unruh
- H03 - BASIC ELECTRONIC CIRCUITRY

in which the counter of the loop counts between two different non zero numbers

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Clock synchronization

Methods and circuits for slew-rate calibration

Systems and methods for PLL gain calibration

Systems and methods for PLL gain calibration and duty cycle calibra...

Methods and apparatus for synchronizing data transfers across clock...

Phase locked circuit, method of operating the same, and transceiver

Use of Frequency addition in a PLL control loop

Methods and apparatus for alteration of terminal counts of phase-lo...

Frequency synthesizer incorporating vernier phase adjuster

Programmable divider

Digital frequency synthesizer having selectable frequency offset be...

Phase-locked loop transceiver having automatic frequency offset sel...

3918006

3538442

3431499

3375448

3286191

Patents Applicationslast 30 patents

METHODS AND CIRCUITS FOR SLEW-RATE CALIBRATION

MEMORY DEVICE AND STORAGE DEVICE INCLUDING THE SAME

SHARED PHASE-LOCKED LOOP (PLL) CIRCUITRY FOR MULTIPLE TRANSMISSION...

FREQUENCY OFFSET OF A CLOCK SIGNAL

SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION AND DUTY CYCLE CALIBRA...

SYSTEMS AND METHODS FOR PLL GAIN CALIBRATION

METHOD AND AN APPARATUS FOR GENERATING AN OUTPUT CLOCK IN A MULTI-L...

CLOCK SYNCHRONIZATION

CONTROL OF SKEW BETWEEN MULTIPLE DATA LANES

METHODS AND CIRCUITS FOR SLEW-RATE CALIBRATION

METHODS AND APPARATUS FOR SYNCHRONIZING DATA TRANSFERS ACROSS CLOCK...

PHASE LOCKED CIRCUIT, METHOD OF OPERATING THE SAME, AND TRANSCEIVER

CLOCK FREQUENCY DETECTION METHOD AND APPARATUS

Use of Frequency Addition in a PLL Control Loop

Methods and apparatus for alteration of terminal counts of phase-lo...