Input synchronization

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CPC
G11C7/1093

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C7/00Arrangements for writing information into, or reading information out from, a digital store

Current Industry

G11C7/1093Input synchronization

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Clock mode determination in a memory system
- Patent number 12,321,600
- Issue date Jun 3, 2025
- Mosaid Technologies Incorporated
- Peter B. Gillingham
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory controller operable in data loop-back mode
- Patent number 12,314,113
- Issue date May 27, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses for timing control in write path
- Patent number 12,315,592
- Issue date May 27, 2025
- Micron Technology, Inc.
- Shingo Mitsubori
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory device, controller and memory system
- Patent number 12,300,355
- Issue date May 13, 2025
- Samsung Electronics Co., Ltd.
- Kuiyon Mun
- G11 - INFORMATION STORAGE
Information Patent Grant
Equalizer for removing inter symbol interference of data signal by...
- Patent number 12,301,236
- Issue date May 13, 2025
- Samsung Electronics Co., Ltd.
- Daehoon Na
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device
- Patent number 12,300,352
- Issue date May 13, 2025
- Samsung Electronics Co., Ltd.
- Jaewoo Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Die disablement
- Patent number 12,300,351
- Issue date May 13, 2025
- Micron Technology, Inc.
- Yang Lu
- G11 - INFORMATION STORAGE
Information Patent Grant
Offset calibration training method for adjusting data receiver offs...
- Patent number 12,293,807
- Issue date May 6, 2025
- Samsung Electronics Co., Ltd.
- Younggil Go
- G11 - INFORMATION STORAGE
Information Patent Grant
Pulse generator, error check and scrub (ECS) circuit and memory
- Patent number 12,283,345
- Issue date Apr 22, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Zequn Huang
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with reset voltage control
- Patent number 12,277,991
- Issue date Apr 15, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Ali Taghvaei
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller performing training to improve communication and...
- Patent number 12,272,425
- Issue date Apr 8, 2025
- SK Hynix Inc.
- Nam Hyeok Jeong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Duty cycle adjuster optimization training algorithm to minimize the...
- Patent number 12,272,426
- Issue date Apr 8, 2025
- Intel Corporation
- Arvind Kumar
- G11 - INFORMATION STORAGE
Information Patent Grant
Extended address interface activate sequence using mode register write
- Patent number 12,260,931
- Issue date Mar 25, 2025
- Micron Technology, Inc.
- Paul Philip Grahek
- G11 - INFORMATION STORAGE
Information Patent Grant
Data receiving circuit, data receiving system and memory device
- Patent number 12,237,042
- Issue date Feb 25, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Feng Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system including an interface circuit connecting a controlle...
- Patent number 12,237,046
- Issue date Feb 25, 2025
- Samsung Electronics Co., Ltd.
- Youngmin Jo
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory devices having efficient serializers therein f...
- Patent number 12,237,049
- Issue date Feb 25, 2025
- Samsung Electronics Co., Ltd.
- Sanguk Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system using asymmetric source-synchronous clocking
- Patent number 12,228,961
- Issue date Feb 18, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical bank group timing
- Patent number 12,230,355
- Issue date Feb 18, 2025
- RAMBUS INC.
- John Eric Linstadt
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component with input/output data rate alignment
- Patent number 12,229,435
- Issue date Feb 18, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory component having internal read-modify-write operation
- Patent number 12,223,207
- Issue date Feb 11, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device for supporting command bus training mode and method o...
- Patent number 12,217,823
- Issue date Feb 4, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Storage device and operating method with multiple channels
- Patent number 12,217,821
- Issue date Feb 4, 2025
- SK Hynix Inc.
- Seung Han Ryu
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device with adjustment of phase of data signal and cl...
- Patent number 12,205,668
- Issue date Jan 21, 2025
- Samsung Electronics Co., Ltd.
- Jaemin Choi
- G11 - INFORMATION STORAGE
Information Patent Grant
Pipe latch circuit, operating method thereof, and semiconductor mem...
- Patent number 12,205,666
- Issue date Jan 21, 2025
- SK hynix Inc.
- Bo Kyeom Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Off-chip driving device and driving capability enhancement method t...
- Patent number 12,190,991
- Issue date Jan 7, 2025
- NANYA TECHNOLOGY CORPORATION
- Chang-Ting Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Command processing circuit and data processing circuit
- Patent number 12,190,992
- Issue date Jan 7, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Liping Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Internal and external data transfer for stacked memory dies
- Patent number 12,176,059
- Issue date Dec 24, 2024
- Micron Technology, Inc.
- Kang-Yong Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for detecting margins of data signal and stora...
- Patent number 12,159,034
- Issue date Dec 3, 2024
- Huawei Technologies Co., Ltd.
- Yongyao Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device for performing data alignment operation
- Patent number 12,154,653
- Issue date Nov 26, 2024
- SK hynix Inc.
- Young Mok Jeong
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic random access memory speed bin compatibility
- Patent number 12,154,654
- Issue date Nov 26, 2024
- Micron Technology, Inc.
- Erik V. Pohlmann
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY MODULE WITH LOCAL SYNCHRONIZATION
- Publication number 20250181504
- Publication date Jun 5, 2025
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
- Publication number 20250182802
- Publication date Jun 5, 2025
- Samsung Electronics Co., Ltd.
- Youngmin Jo
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICES HAVING EFFICIENT SERIALIZERS THEREIN F...
- Publication number 20250157513
- Publication date May 15, 2025
- Samsung Electronics Co., Ltd.
- Sanguk Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...
- Publication number 20250149076
- Publication date May 8, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...
- Publication number 20250124959
- Publication date Apr 17, 2025
- Samsung Electronics Co., Ltd.
- Young-hun Kim
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM
- Publication number 20250111873
- Publication date Apr 3, 2025
- Rambus Inc.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP
- Publication number 20250095703
- Publication date Mar 20, 2025
- KIOXIA Corporation
- Shinya KOIZUMI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR OPERATING IN-MEMORY COMPUTING ARCHITECTURE...
- Publication number 20250078881
- Publication date Mar 6, 2025
- PEKING UNIVERSITY
- Peng HUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, AND MEMORY SY...
- Publication number 20250078888
- Publication date Mar 6, 2025
- Samsung Electronics Co., Ltd.
- Tongsung Kim
- G11 - INFORMATION STORAGE
Information Patent Application
LOW-POWER SOURCE-SYNCHRONOUS SIGNALING
- Publication number 20250069644
- Publication date Feb 27, 2025
- Rambus Inc.
- Jared L. ZERBE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC RANDOM ACCESS MEMORY SPEED BIN COMPATIBILITY
- Publication number 20250046353
- Publication date Feb 6, 2025
- Micron Technology, Inc.
- Erik V. Pohlmann
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE FOR PERFORMING DATA ALIGNMENT OPERATION
- Publication number 20250046352
- Publication date Feb 6, 2025
- SK HYNIX INC.
- Young Mok JEONG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING
- Publication number 20250028660
- Publication date Jan 23, 2025
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE CIRCUIT FOR CONVERTING A SERIAL DATA STREAM TO A PARALLEL...
- Publication number 20250021270
- Publication date Jan 16, 2025
- Rambus Inc.
- Dongyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MODIFICATION OF A COMMAND TIMING PATTERN
- Publication number 20250006235
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Carl L. Minifie
- G11 - INFORMATION STORAGE
Information Patent Application
SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING
- Publication number 20240428835
- Publication date Dec 26, 2024
- Rambus Inc.
- Andrew M. Fuller
- G11 - INFORMATION STORAGE
Information Patent Application
Synchronous Input Buffer Control Using a Ripple Counter
- Publication number 20240420746
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Brian W. Huber
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES
- Publication number 20240402788
- Publication date Dec 5, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM PERFORMING HIERARCHICAL DUTY CYCLE ADJUSTER TRAINING...
- Publication number 20240404570
- Publication date Dec 5, 2024
- Samsung Electronics Co., Ltd.
- Ki-Seok PARK
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS
- Publication number 20240395296
- Publication date Nov 28, 2024
- SK HYNIX INC.
- Hyun Seung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
DATA TRANSMISSION USING DELAYED TIMING SIGNALS
- Publication number 20240372542
- Publication date Nov 7, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY SYSTEM USING ASYMMETRIC SOURCE-SYNCHRONOUS CLOCKING
- Publication number 20240345618
- Publication date Oct 17, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSE BASED MULTI-LEVEL CELL PROGRAMMING
- Publication number 20240347081
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Hernan A. Castro
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING
- Publication number 20240345971
- Publication date Oct 17, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY...
- Publication number 20240339137
- Publication date Oct 10, 2024
- Rambus Inc.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Application
DATA STROBE LATCHING CIRCUIT AND ADJUSTING METHOD FOR ADJUSTING INT...
- Publication number 20240331751
- Publication date Oct 3, 2024
- NANYA TECHNOLOGY CORPORATION
- Shu-Wei Yang
- G11 - INFORMATION STORAGE
Information Patent Application
ERROR CORRECTION CODE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING...
- Publication number 20240321383
- Publication date Sep 26, 2024
- SK HYNIX INC.
- Seon Woo HWANG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT
- Publication number 20240289047
- Publication date Aug 29, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR SYSTEM FOR PERFORMING A DATA ALIGNMENT OPERATION
- Publication number 20240282352
- Publication date Aug 22, 2024
- SK HYNIX INC.
- Hyun Seung KIM
- G11 - INFORMATION STORAGE
Information Patent Application
ELECTRONIC DEVICE, MEMORY DEVICE, AND WRITE LEVELING METHOD THEREOF
- Publication number 20240265955
- Publication date Aug 8, 2024
- NANYA TECHNOLOGY CORPORATION
- Shun-Ke WU
- G11 - INFORMATION STORAGE

Input synchronization

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Clock mode determination in a memory system

Memory controller operable in data loop-back mode

Apparatuses for timing control in write path

Non-volatile memory device, controller and memory system

Equalizer for removing inter symbol interference of data signal by...

Semiconductor device

Die disablement

Offset calibration training method for adjusting data receiver offs...

Pulse generator, error check and scrub (ECS) circuit and memory

Memory device with reset voltage control

Memory controller performing training to improve communication and...

Duty cycle adjuster optimization training algorithm to minimize the...

Extended address interface activate sequence using mode register write

Data receiving circuit, data receiving system and memory device

Memory system including an interface circuit connecting a controlle...

Semiconductor memory devices having efficient serializers therein f...

Memory system using asymmetric source-synchronous clocking

Hierarchical bank group timing

Memory component with input/output data rate alignment

Memory component having internal read-modify-write operation

Memory device for supporting command bus training mode and method o...

Storage device and operating method with multiple channels

Semiconductor device with adjustment of phase of data signal and cl...

Pipe latch circuit, operating method thereof, and semiconductor mem...

Off-chip driving device and driving capability enhancement method t...

Command processing circuit and data processing circuit

Internal and external data transfer for stacked memory dies

Method and apparatus for detecting margins of data signal and stora...

Semiconductor device for performing data alignment operation

Dynamic random access memory speed bin compatibility

Patents Applicationslast 30 patents

MEMORY MODULE WITH LOCAL SYNCHRONIZATION

SEMICONDUCTOR DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

SEMICONDUCTOR MEMORY DEVICES HAVING EFFICIENT SERIALIZERS THEREIN F...

MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...

MEMORY DEVICE FOR SUPPORTING COMMAND BUS TRAINING MODE AND METHOD O...

METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM

MEMORY SYSTEM AND METHOD OF CONTROLLING A MEMORY CHIP

METHOD AND APPARATUS FOR OPERATING IN-MEMORY COMPUTING ARCHITECTURE...

MEMORY DEVICE, METHOD OF OPERATING THE MEMORY DEVICE, AND MEMORY SY...

LOW-POWER SOURCE-SYNCHRONOUS SIGNALING

DYNAMIC RANDOM ACCESS MEMORY SPEED BIN COMPATIBILITY

SEMICONDUCTOR DEVICE FOR PERFORMING DATA ALIGNMENT OPERATION

MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING

INTERFACE CIRCUIT FOR CONVERTING A SERIAL DATA STREAM TO A PARALLEL...

MODIFICATION OF A COMMAND TIMING PATTERN

SIGNAL RECEIVER WITH SKEW-TOLERANT STROBE GATING

Synchronous Input Buffer Control Using a Ripple Counter

MEMORY CONTROLLER WITH TRANSACTION-QUEUE-DEPENDENT POWER MODES

MEMORY SYSTEM PERFORMING HIERARCHICAL DUTY CYCLE ADJUSTER TRAINING...

SEMICONDUCTOR DEVICES RELATED TO DATA INPUT AND OUTPUT OPERATIONS

DATA TRANSMISSION USING DELAYED TIMING SIGNALS

MEMORY SYSTEM USING ASYMMETRIC SOURCE-SYNCHRONOUS CLOCKING

PULSE BASED MULTI-LEVEL CELL PROGRAMMING

SEMICONDUCTOR MEMORY SYSTEMS WITH ON-DIE DATA BUFFERING

DRAM INTERFACE MODE WITH IMPROVED CHANNEL INTEGRITY AND EFFICIENCY...

DATA STROBE LATCHING CIRCUIT AND ADJUSTING METHOD FOR ADJUSTING INT...

ERROR CORRECTION CODE CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING...

MEMORY COMPONENT WITH INPUT/OUTPUT DATA RATE ALIGNMENT

SEMICONDUCTOR SYSTEM FOR PERFORMING A DATA ALIGNMENT OPERATION

ELECTRONIC DEVICE, MEMORY DEVICE, AND WRITE LEVELING METHOD THEREOF