Arrangements for writing information into, or reading information out from, a digital store

GPHYSICS G11Information storage G11CSTATIC STORES

G11C7/00Arrangements for writing information into, or reading information out from, a digital store

G11C7/005with combined beam-and individual cell access G11C7/02with means for avoiding parasitic signals G11C7/04with means for avoiding disturbances due to temperature effects G11C7/06Sense amplifiers Associated circuits G11C7/062Differential amplifiers of non-latching type G11C7/065Differential amplifiers of latching type G11C7/067Single-ended amplifiers G11C7/08Control thereof G11C7/10Input/output (I/0) data interface arrangements G11C7/1003Interface circuits for daisy chain or ring bus memory arrangements G11C7/1006Data managing G11C7/1009Data masking during input/output G11C7/1012Data reordering during input/output G11C7/1015Read-write modes for single port memories G11C7/1018Serial bit line access mode G11C7/1021Page serial bit line access mode G11C7/1024Extended data output [EDO] mode G11C7/1027Static column decode serial bit line access mode G11C7/103using serially addressed read-write data registers G11C7/1033using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages G11C7/1036using data shift registers G11C7/1039using pipelining techniques, i.e. using latches between functional memory parts G11C7/1042using interleaving techniques G11C7/1045Read-write mode select circuits G11C7/1048Data bus control circuits G11C7/1051Data output circuits G11C7/1054Optical output buffers G11C7/1057Data output buffers G11C7/106Data output latches G11C7/1063Control signal output circuits G11C7/1066Output synchronization G11C7/1069I/O lines read out arrangements G11C7/1072for memories with random access ports synchronised on clock signal pulse trains G11C7/1075for multiport memories each having random access ports and serial ports G11C7/1078Data input circuits G11C7/1081Optical input buffers G11C7/1084Data input buffers G11C7/1087Data input latches G11C7/109Control signal input circuits G11C7/1093Input synchronization G11C7/1096Write circuits G11C7/12Bit line control circuits G11C7/14Dummy cell management Sense reference voltage generators G11C7/16Storage of analogue signals in digital stores using an arrangement comprising analogue/digital (A/D) converters, digital memories and digital/analogue (D/A) converters G11C7/18Bit line organisation Bit line lay-out G11C7/20Memory initialisation circuits G11C7/22Read-write (R-W) timing or clocking circuits Read-write (R-W) control signal generators or management G11C7/222Clock generating, synchronizing or distributing circuits within memory device G11C7/225Clock input buffers G11C7/227Timing of memory operations based on dummy memory elements or replica circuits G11C7/24Memory cell safety or protection circuits