Instructions to perform operations on packed data

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G06F9/30036

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/30036Instructions to perform operations on packed data

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Instructions to perform operations on packed data

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Retimer with host-interactive data logging engine

Entering protected pipeline mode with clearing

Generalized acceleration of matrix multiply accumulate operations

Look up table with data element promotion

Initialization of parameters for machine-learned transformer neural...

Instructions and logic to provide SIMD SM4 cryptographic block ciph...

Implicit fence for write messages

Systems and methods for hardware gather optimization

Memory protection for vector operations

Systems, methods, and apparatuses for dot production operations

Task synchronization for accelerated deep learning

Stalling issue queue entries until consecutive allocated entries ar...

Deep vision processor

Apparatus and method for performing a stable and short latency sort...

High-performance multi-literal matching algorithm

Vector reverse

Bit-parallel vector composability for neural acceleration

Systems and methods for performing 16-bit floating-point matrix dot...

Register based SIMD lookup table operations

Streaming engine with stream metadata saving for context switching

Sparse optimizations for a matrix accelerator architecture

Branch prediction using hypervectors

Fine-grained image recognition method and apparatus using graph str...

Systems and methods to store a tile register pair to memory

Bundling and dynamic allocation of register blocks for vector instr...

Stream data unit with multiple head registers

Register addressing information for data transfer instruction

Microprocessor with odd and even register sets

Operation fusion for instructions bridging execution unit types

Instructions for fused multiply-add operations with variable precis...

Patents Applicationslast 30 patents

DATA PROCESSING

MEMORY PROTECTION FOR GATHER-SCATTER OPERATIONS

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

TECHNIQUE FOR HANDLING DATA ELEMENTS STORED IN AN ARRAY STORAGE

TECHNIQUE FOR HANDLING DATA ELEMENTS STORED IN AN ARRAY STORAGE

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

CONSOLIDATION OF INTERRUPT LOST EVENTS IN MULTI-LEVEL INTERRUPT SYSTEM

LOOPING INSTRUCTION

RE-USING PROCESSING ELEMENTS OF AN ARTIFICIAL INTELLIGENCE PROCESSOR

TECHNIQUE FOR PERFORMING MEMORY ACCESS OPERATIONS

INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS

Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...

DATA INITIALIZATION TECHNIQUES

SUB-VECTOR-SUPPORTING INSTRUCTION FOR SCALABLE VECTOR INSTRUCTION S...

VECTOR PROCESSOR STORAGE

Group Thread Dispatch for Graph Streaming Processor

INTERRUPTIBLE AND RESTARTABLE MATRIX MULTIPLICATION INSTRUCTIONS, P...

PERSISTENT STORAGE DEVICE MANAGEMENT

MEMORY DEVICE AND METHOD WITH PROCESSING-IN-MEMORY BLOCK

PROVIDING ADDITIONAL OPERATIONS FOR A FUNCTIONAL UNIT OF A PROCESSO...

VECTOR TRANSFORMATION IN PARALLEL WITH ARITHMETIC OPERATION

TECHNIQUES FOR PERFORMING NON-VECTOR MICRO-OPERATIONS ON VECTOR HAR...

Implicit Global Pointer Relative Addressing for Global Memory Access

METHOD OF STORING REGISTER DATA ELEMENTS TO INTERLEAVE WITH DATA EL...

SYSTEMS AND METHODS FOR FEDERATED COMPUTER PROCESSING ARCHITECTURE...

SYSTEMS, METHODS, AND APPARATUSES FOR HETEROGENEOUS COMPUTING

MULTI-VARIATE STRIDED READ OPERATIONS FOR ACCESSING MATRIX OPERANDS

Routing an Edge of an Operation Unit Graph on a Reconfigurable Proc...

DUAL PIPELINE PARALLEL SYSTOLIC ARRAY

IN-CORE IMPLEMENTATION OF ADVANCED REDUCED INSTRUCTION SET COMPUTER...