Instructions to perform operations on packed data

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G06F9/30036

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/30036Instructions to perform operations on packed data

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Instructions to perform operations on packed data

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Machine learning architecture support for block sparsity

Instructions to convert from FP16 to BF8

Controlling the number of powered vector lanes via a register field

Hardware accelerator for execution of instruction set of recurrent...

Coalescing adjacent gather/scatter operations

Lock-free unordered in-place compaction

Methods, systems, and devices for an encrypted and obfuscated algor...

Apparatuses, methods, and systems for instructions for matrix multi...

Programmable accelerator for data-dependent, irregular operations

Methods and apparatus for performing diversity matrix operations wi...

Flexible instruction set architecture supporting varying frequencies

Data processing apparatus and related products

Dynamic precision for neural network compute operations

Register file for systolic array

Sparse SIMD cross-lane processing unit

Streaming processor architecture

Streaming engine with separately selectable element and group dupli...

Butterfly network on load data return

Vector instruction cracking after scalar dispatch

Permuting in a matrix-vector processor

Method and device for selecting entry of queue in out-of-order proc...

Neural network training with acceleration

Sorting the nodes of an operation unit graph for implementation in...

Base plus offset addressing for load/store messages

Retimer with host-interactive data logging engine

Entering protected pipeline mode with clearing

Generalized acceleration of matrix multiply accumulate operations

Look up table with data element promotion

Initialization of parameters for machine-learned transformer neural...

Implicit fence for write messages

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR EFFICIENT DATA MOVEMENT IN VECTOR PROCESSORS

Vector Processor Architectures

LOW LATENCY MATRIX MULTIPLY UNIT

REGISTER ACCESS VIA A READ PORT

LOW LATENCY MATRIX MULTIPLY UNIT

NEURAL NETWORK COMPUTE TILE

TASK EXECUTION METHOD FOR LARGE MODEL, ELECTRONIC DEVICE, AND STORA...

STREAMING ENGINE WITH MULTI DIMENSIONAL CIRCULAR ADDRESSING SELECTA...

INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECIS...

BFLOAT16 FUSED MULTIPLY INSTRUCTIONS

SPARSE OPTIMIZATIONS FOR A MATRIX ACCELERATOR ARCHITECTURE

RESOURCE SELECTION

POWER/AREA EFFICIENT ACCELERATION OF PROCESSOR-BASED ARTIFICIAL NEU...

VECTOR MEMORY LOADS RETURN TO CACHE

SYSTEMS AND METHODS FOR PERFORMING MATRIX COMPRESS AND DECOMPRESS I...

SYSTEMS AND METHODS FOR DATA PLACEMENT FOR IN-MEMORY-COMPUTE

DATA PROCESSING

MEMORY PROTECTION FOR GATHER-SCATTER OPERATIONS

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

TECHNIQUE FOR HANDLING DATA ELEMENTS STORED IN AN ARRAY STORAGE

TECHNIQUE FOR HANDLING DATA ELEMENTS STORED IN AN ARRAY STORAGE

ARCHITECTURE FOR BLOCK SPARSE OPERATIONS ON A SYSTOLIC ARRAY

CONSOLIDATION OF INTERRUPT LOST EVENTS IN MULTI-LEVEL INTERRUPT SYSTEM

LOOPING INSTRUCTION

RE-USING PROCESSING ELEMENTS OF AN ARTIFICIAL INTELLIGENCE PROCESSOR

TECHNIQUE FOR PERFORMING MEMORY ACCESS OPERATIONS

INSERTING PREDEFINED PAD VALUES INTO A STREAM OF VECTORS

Forming Constant Extensions in the Same Execute Packet in a VLIW Pr...

DATA INITIALIZATION TECHNIQUES

SUB-VECTOR-SUPPORTING INSTRUCTION FOR SCALABLE VECTOR INSTRUCTION S...