Instructions to perform operations on packed data

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/30036Instructions to perform operations on packed data

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Instructions to perform operations on packed data

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Fast multiple core method and system for chaining isogeny computations

Software compilation for networked processing system

Supporting 8-bit floating point format operands in a computing arch...

Software to industrial device interface

Vector population count determination via comparison iterations in...

System and method for processing between a plurality of quantum con...

Data initialization techniques

Systems and methods to load a tile register pair

Two address translations from a single table look-aside buffer read

Systems and methods for data placement for in-memory-compute

Group thread dispatch for graph streaming processor

Single function to perform combined matrix multiplication and bias...

Apparatus and method for ray tracing instruction processing and exe...

Vector processor storage

Data shards for distributed processing

Persistent storage device management

BFLOAT16 fused multiply instructions

Block data load with transpose into memory

Multi-variate strided read operations for accessing matrix operands

Performing matrix multiplication in a streaming processor

Embedded processor supporting fixed-function kernels

Methods and apparatus for providing mask register optimization for...

Enhanced input of machine-learning accelerator activations

Family of processors of different types configured for executing a...

Methods and circuits of spatial alignment

Out-of-order vector iota calculations

Apparatus and method for conjugate transpose and multiply

Instructions and logic to perform floating point and integer operat...

Load/store unit for a tensor engine and methods for loading or stor...

Method of storing register data elements to interleave with data el...

Patents Applicationslast 30 patents

INSTRUCTION ENCODING TO IMPLEMENT INCREASED REGISTER CAPACITY PER T...

APPARATUSES AND METHODS FOR IN-MEMORY OPERATIONS

COMPUTER-READABLE RECORDING MEDIUM STORING ARITHMETIC PROGRAM, ARIT...

TASK EXECUTION IN A SIMD PROCESSING UNIT WITH PARALLEL GROUPS OF PR...

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SYSTEMS, APPARATUSES, AND METHODS FOR CHAINED FUSED MULTIPLY ADD

RANDOM SPARSITY HANDLING IN A SYSTOLIC ARRAY

VECTOR FLOATING-POINT CLASSIFICATION

APPARATUS AND METHOD FOR COMPLEX MATRIX TRANSPOSE AND MULTIPLY

VECTOR SHUFFLING METHOD, PROCESSOR AND ELECTRONIC DEVICE

PADDING IN A STREAM OF MATRIX ELEMENTS

METHODS AND APPARATUS FOR PERFORMING MATRIX TRANSFORMATIONS WITHIN...

ZERO-CLEARING SCALAR MOVES

INSTRUCTION SET ARCHITECTURE FOR IN-MEMORY COMPUTING

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

TECHNIQUES FOR CONTROLLING VECTOR PROCESSING OPERATIONS

VECTOR DATAFLOW ARCHITECTURE FOR EMBEDDED SYSTEMS

BIT MATRIX MULTIPLICATION

STREAMING ENGINE WITH DEFERRED EXCEPTION REPORTING

BINARY CONVOLUTION INSTRUCTIONS FOR BINARY NEURAL NETWORK COMPUTATIONS

SUPPORT FOR LESS THAN 512-BIT OPERAND PROCESSING

MULTI-TILE MEMORY MANAGEMENT

SYSTEMS, METHODS, AND APPARATUSES FOR TILE LOAD

SYSTEMS, APPARATUSES, AND METHODS FOR ADDITION OF PARTIAL PRODUCTS

PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS TO ATOMICALLY STORE...

VECTOR COMPUTATIONAL UNIT

MATRIX OPERATION OPTIMIZATION MECHANISM

SCALABLE SPARSE MATRIX MULTIPLY ACCELERATION USING SYSTOLIC ARRAYS...

VECTOR FRIENDLY INSTRUCTION FORMAT AND EXECUTION THEREOF

METHOD AND APPARATUS FOR VECTOR PERMUTATION