Instructions to perform operations on packed data

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G06F9/30036

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

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G06F9/30036Instructions to perform operations on packed data

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Instructions to perform operations on packed data

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Sparse SIMD cross-lane processing unit

Graphics processing unit and central processing unit cooperative va...

Systems for performing instructions to quickly convert and use tile...

Graphics processors and graphics processing units having dot produc...

Dynamic memory reconfiguration

Computing resource management with fast sorting using vector instru...

Carry chain for SIMD operations

Re-using processing elements of an artificial intelligence processor

Replicate partition instruction

Data element rearrangement, processors, methods, systems, and instr...

Machine instructions for decoding acceleration including fuse input...

Registers in vector processors to store addresses for accessing vec...

Genome sequence alignment system and method

Vector reduction processor

Retimer with host-interactive data logging engine

Compiler-driven storage allocation of runtime values

Laser-based methods, devices and systems for quantum classification...

Intelligent data protection

Vector reductions using shared scratchpad memory

Using a vector processor to configure a direct memory access system...

Method and apparatus for data-ready memory operations

Assistance for hardware prefetch in cache access

Stream data unit with multiple head registers

Distributed representations of computing processes and events

Parameter vector value proposal apparatus, parameter vector value p...

Vector SIMD VLIW data path architecture

Method and apparatus for dual multiplication units in a data path

Streaming engine with flexible streaming engine template supporting...

Creating equipment control sequences from constraint data

Debugging of accelerator circuit for mathematical operations using...

Patents Applicationslast 30 patents

SYSTEMS AND METHODS FOR EXECUTING A FUSED MULTIPLY-ADD INSTRUCTION...

INSTRUCTIONS FOR FUSED MULTIPLY-ADD OPERATIONS WITH VARIABLE PRECIS...

SYSTEMS AND METHODS FOR PERFORMING 16-BIT FLOATING-POINT MATRIX DOT...

INSTRUCTION SET ARCHITECTURE FOR A VECTOR COMPUTATIONAL UNIT

SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILE...

PROCESSING COMPLEX PACKED TENSORS USING INTEGRATED CIRCUIT OF REAL...

Vector Instruction Cracking After Scalar Dispatch

DATA PROCESSING METHOD AND APPARATUS, AND RELATED PRODUCT

METHODS AND APPARATUS FOR PROVIDING MASK REGISTER OPTIMIZATION FOR...

MATRIX MULTIPLICATION UNIT WITH FLEXIBLE PRECISION OPERATIONS

TECHNOLOGIES FOR DYNAMICALLY MANAGING RESOURCES IN DISAGGREGATED AC...

VECTOR PROCESSING UNIT WITH PROGRAMMABLE MULTICYCLE SHUFFLE UNIT

PROCESSING GROUPS OF DATA IN PARALLEL

LOCK-FREE UNORDERED IN-PLACE COMPACTION

PROGRAMMABLE COMPUTE ENGINE HAVING TRANSPOSE OPERATIONS

FREQUENCY SCALING FOR PER-CORE ACCELERATOR ASSIGNMENTS

SYSTEMS, METHODS, AND APPARATUS FOR TILE CONFIGURATION

TRUNCATION FLOATING-POINT CONVERSION TO INTEGER WITH SATURATION

SYSTEMS FOR PERFORMING INSTRUCTIONS TO QUICKLY CONVERT AND USE TILE...

SYSTEM AND METHOD FOR DIVIDE-AND-CONQUER CHECKPOINTING

VECTOR MULTIPLY-ADD/SUBTRACT WITH INTERMEDIATE ROUNDING

METHOD AND APPARATUS FOR MATRIX COMPUTATION USING DATA CONVERSION I...

Nonlinear, decentralized Processing Unit and Related Systems or Met...

SPECIAL-PURPOSE DIGITAL-COMPUTE HARDWARE FOR EFFICIENT ELEMENT-WISE...

SYSTEMS AND METHODS FOR UPDATING MEMORY SIDE CACHES IN A MULTI-GPU...

INSTRUCTION BASED CONTROL OF MEMORY ATTRIBUTES

Methods and Apparatus for Performing Diversity Matrix Operations Wi...

ACCELERATOR ARCHITECTURE ON A PROGRAMMABLE PLATFORM

APPARATUSES, METHODS, AND SYSTEMS FOR INSTRUCTIONS OF A MATRIX OPER...

HARDWARE ENHANCEMENTS FOR MATRIX LOAD/STORE INSTRUCTIONS