Micro-instruction selection not based on processing results

Industry

CPC
G06F9/268

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F9/00Arrangements for programme control

Current Industry

G06F9/268Micro-instruction selection not based on processing results

Industries

Patents Grantslast 30 patents

Information Patent Grant
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- Microsoft Technology Licensing, LLC
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Live firmware update switchover
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- Sira Parasurama Rao
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- Prashant Dewan
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Generation and use of memory access instruction order encodings
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- Microsoft Technology Licensing, LLC
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Information Patent Grant
Scheduler for amp architecture with closed loop performance and the...
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- Apple Inc.
- Jeremy C. Andrus
- G06 - COMPUTING CALCULATING COUNTING
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Memory devices, systems, and methods for updating firmware with sin...
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Hardware processors and methods for extended microcode patching and...
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- CAPITAL ONE SERVICES, LLC
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Scheduler for amp architecture using a closed loop performance and...
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Information Patent Grant
Controlling apparatus for industrial products
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Information Patent Grant
Closed loop performance controller work interval instance propagation
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Information Patent Grant
Block-based processor core composition register
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Information Patent Grant
Scheduling of work interval objects in an AMP architecture using a...
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- Apple Inc.
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Information Patent Grant
Distinct system registers for logical processors
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- Issue date May 25, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
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Information Patent Grant
Scheduler for amp architecture using a closed loop performance and...
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- Apple Inc.
- Jeremy C. Andrus
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Information Patent Grant
Dense read encoding for dataflow ISA
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- Issue date Mar 2, 2021
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduler for AMP architecture with closed loop performance control...
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- Issue date Jan 5, 2021
- Apple Inc.
- Jeremy C. Andrus
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Register read/write ordering
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- Issue date Dec 22, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debug support for block-based processor
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- Issue date Sep 15, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
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Information Patent Grant
Block-based processor including topology and control registers to i...
- Patent number 10,768,936
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- Microsoft Technology Licensing, LLC
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Information Patent Grant
Systems and methods of parallel and distributed processing of datas...
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- Issue date Aug 4, 2020
- CAPITAL ONE SERVICES, LLC
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- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetching instruction blocks
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- Issue date Jul 21, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Initiating instruction block execution using a register access inst...
- Patent number 10,678,544
- Issue date Jun 9, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduler for amp architecture using a closed loop performance cont...
- Patent number 10,599,481
- Issue date Mar 24, 2020
- Apple Inc.
- Constantin Pistol
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hint instruction for managing transactional aborts in transactional...
- Patent number 10,565,003
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Fadi Y. Busaba
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Broadcast channel architectures for block-based processors
- Patent number 10,452,399
- Issue date Oct 22, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multimodal targets in a block-based processor
- Patent number 10,445,097
- Issue date Oct 15, 2019
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scheduler for AMP architecture with closed loop performance controller
- Patent number 10,417,054
- Issue date Sep 17, 2019
- Apple Inc.
- Jeremy C. Andrus
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

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- TEXAS INSTRUMENTS INCORPORATED
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LIVE FIRMWARE UPDATE SWITCHOVER
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APPARATUS AND METHOD FOR SECURE, EFFICIENT MICROCODE PATCHING
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PROGRAMMABLE CONTROLLER
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- Telefonaktiebolaget LM Ericsson (publ)
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Device and Method for a Frequency Modulated Signal
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- Publication date Mar 3, 2022
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SCHEDULER FOR AMP ARCHITECTURE WITH CLOSED LOOP PERFORMANCE AND THE...
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SYSTEMS AND METHODS OF PARALLEL AND DISTRIBUTED PROCESSING
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INFORMATION PROCESSING SYSTEM AND RELAY DEVICE
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- FUJITSU CLIENT COMPUTING LIMITED
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HINT INSTRUCTION FOR MANAGING TRANSACTIONAL ABORTS IN TRANSACTIONAL...
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SCHEDULER FOR AMP ARCHITECTURE USING A CLOSED LOOP PERFORMANCE AND...
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SCHEDULER FOR AMP ARCHITECTURE WITH CLOSED LOOP PERFORMANCE CONTROLLER
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MULTI-NULLIFICATION
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- Publication date Nov 15, 2018
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APPARATUS AND METHOD FOR SYSTEM PHYSICAL ADDRESS TO MEMORY MODULE A...
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APPARATUS AND METHOD FOR REAL-TIME MICROCODE PATCH
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APPARATUS AND METHOD FOR FAST ONE-TO-MANY MICROCODE PATCH
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WIRELESS DATA COMMUNICATIONS USING FIFO FOR SYNCHRONIZATION MEMORY
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MICROCODE PATCHING SYSTEM AND METHOD
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Wireless data communications using FIFO for synchronization memory
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Integrated circuit with memory and method of configuring a memory
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System on a chip integrated circuit, processing system and methods...
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- Publication date Apr 12, 2007
- Antonio Torrini
- G06 - COMPUTING CALCULATING COUNTING

Micro-instruction selection not based on processing results

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Implicit program order

Apparatus, a method and a computer program for video coding and dec...

Accelerator controller for inserting template microcode instruction...

Live firmware update switchover

Apparatus and method for secure, efficient microcode patching

Generation and use of memory access instruction order encodings

Scheduler for amp architecture with closed loop performance and the...

Memory devices, systems, and methods for updating firmware with sin...

Hardware processors and methods for extended microcode patching and...

Systems and methods of parallel and distributed processing of datas...

Scheduler for amp architecture using a closed loop performance and...

Controlling apparatus for industrial products

Closed loop performance controller work interval instance propagation

Block-based processor core composition register

Scheduling of work interval objects in an AMP architecture using a...

Distinct system registers for logical processors

Scheduler for amp architecture using a closed loop performance and...

Dense read encoding for dataflow ISA

Scheduler for AMP architecture with closed loop performance control...

Register read/write ordering

Debug support for block-based processor

Block-based processor including topology and control registers to i...

Systems and methods of parallel and distributed processing of datas...

Prefetching instruction blocks

Initiating instruction block execution using a register access inst...

Scheduler for amp architecture using a closed loop performance cont...

Hint instruction for managing transactional aborts in transactional...

Broadcast channel architectures for block-based processors

Multimodal targets in a block-based processor

Scheduler for AMP architecture with closed loop performance controller

Patents Applicationslast 30 patents

LIVE FIRMWARE UPDATE SWITCHOVER

LIVE FIRMWARE UPDATE SWITCHOVER

APPARATUS AND METHOD FOR SECURE, EFFICIENT MICROCODE PATCHING

APPARATUS AND METHOD FOR SECURE, EFFICIENT MICROCODE PATCHING

PROGRAMMABLE CONTROLLER

Device and Method for a Frequency Modulated Signal

SCHEDULER FOR AMP ARCHITECTURE WITH CLOSED LOOP PERFORMANCE AND THE...

SYSTEMS AND METHODS OF PARALLEL AND DISTRIBUTED PROCESSING

INFORMATION PROCESSING SYSTEM AND RELAY DEVICE

HINT INSTRUCTION FOR MANAGING TRANSACTIONAL ABORTS IN TRANSACTIONAL...

SCHEDULER FOR AMP ARCHITECTURE USING A CLOSED LOOP PERFORMANCE AND...

SCHEDULER FOR AMP ARCHITECTURE WITH CLOSED LOOP PERFORMANCE CONTROLLER

SCHEDULER FOR AMP ARCHITECTURE USING A CLOSED LOOP PERFORMANCE CONT...

MULTI-NULLIFICATION

APPARATUS AND METHOD FOR SYSTEM PHYSICAL ADDRESS TO MEMORY MODULE A...

INSTRUCTION SET ARCHITECTURES FOR FINE-GRAINED HETEROGENEOUS PROCES...

DEBUG SUPPORT FOR BLOCK-BASED PROCESSOR

APPARATUS AND METHOD TO PRECLUDE X86 SPECIAL BUS CYCLE LOAD REPLAYS...

HINT INSTRUCTION FOR MANAGING TRANSACTIONAL ABORTS IN TRANSACTIONAL...

APPARATUS AND METHOD FOR UPDATING SET OF LIMITED ACCESS MODEL SPECI...

MICROCODE PATCH EXPANSION MECHANISM

APPARATUS AND METHOD FOR REAL-TIME MICROCODE PATCH

APPARATUS AND METHOD FOR FAST MICROCODE PATCH FROM MEMORY

ON-CHIP MEMORY PROVIDING FOR MICROCODE PATCH OVERLAY AND CONSTANT U...

APPARATUS AND METHOD FOR FAST ONE-TO-MANY MICROCODE PATCH

WIRELESS DATA COMMUNICATIONS USING FIFO FOR SYNCHRONIZATION MEMORY

MICROCODE PATCHING SYSTEM AND METHOD

Wireless data communications using FIFO for synchronization memory

Integrated circuit with memory and method of configuring a memory

System on a chip integrated circuit, processing system and methods...