Patent Application
20090031121
This application is related to the following co-pending U.S. patent applications, each of which has a common assignee and common inventors.
1. Field of the Invention
This invention relates in general to the field of microelectronics, and more particularly to an apparatus and method for performing microcode patches in a microprocessor.
2. Description of the Related Art
Present day microprocessors are designed to execute many instructions per clock cycle and provide many features to maximize the number of instructions that are executed during any given clock cycle. A clock cycle is generally considered to be that interval of time which is allocated for each of the pipeline stages in the microprocessor to perform the processing work that is required in order to forward results to the next pipeline stage. And present day microprocessors comprise many pipeline stages, a number of which are configured in parallel, to allow for simultaneous, or concurrent processing tasks, thus enabling multiple instructions to be executed in parallel. A core clock signal is provided to each of the pipeline stages in order to synchronize instruction execution in each of the stages. The core clock signal is often a multiple in frequency of a bus clock signal which is provided from an external clock generator circuit.
As one skilled in the art will appreciate, the major stages of a present day pipeline microprocessor may be divided into those associated with fetching instructions (i.e., fetch stage logic) from memory, translating the instructions (i.e., translate stage logic) into associated sequences of micro instructions that are unique to (i.e., “native to”) the specific microprocessor, executing (i.e., execution stage logic) the associated sequences of micro instructions, and writing (e.g., write back stage logic) the results of the executions to designated locations.
The aforementioned fetch and translate stages are described within the context of a present day complex instruction set computer (CISC) that employs macro instructions, such as are exhibited by the ubiquitous x86 instruction set architecture (ISA). A single macro instruction is employed to specify a number of lower-level hardware operations, and thus it is well understood in the art that a macro instruction which has been fetched from memory (e.g., external system memory or cache memory) must first be converted into a corresponding sequence of micro instructions (also known as “native instructions”) that each specify one or more of the lower-level operations. Following this conversion, the micro instructions are dispatched to various execution stage units for execution, often in parallel, whereby results are generated or the specified lower-level operations are performed.
Consequently, significant attention in the art has been devoted to developing very fast and efficient mechanisms for converting macro instructions into associated micro instruction sequences and for optimally dispatching micro instructions to execution stage resources. A number of different approaches exist for performing the conversion operations, but most of the approaches typically can be characterized by a combination of direct conversion (i.e., “translation”) by hardware and indexed storage in a read-only memory (ROM). Direct translation resources are often referred to as translators, decoders, translate logic, and the like, and indexed storage resources are referred to as microcode ROM or micro instruction ROM.
For example, a given macro instruction that specifies a very simple operation may only undergo direct translation by a translator, and will be converted into perhaps one or two associated micro instructions, while another macro instruction that specifies a very complex operation (e.g., a trigonometric function) may be translated into a single micro instruction that specifies an address in the microcode ROM (i.e., a. “microcode ROM entry point”) where a sequence consisting of hundreds of sequential micro instructions is stored, and where each of the micro instructions in the sequence prescribes a lower-level operation that is required to perform the complex operation.
As one skilled in the art will appreciate, it is the complex sequences of micro instructions that are stored in the microcode ROM which are more prone to error. As new microprocessors are designed and fabricated, it is incumbent upon system architects to provide techniques that allow these errors to be detected and corrected in a manner that minimizes the overall impact of the change. Techniques for detecting these errors prior to placing a part into mass production would perhaps sacrifice instruction throughput and speed of a given part for a wide degree of flexibility in the lab or debug environment. For example, it is often advantageous to provide mechanisms for simulating and testing the effects of microcode changes in the lab on a new design prior to committing these changes to silicon. Alternatively, correction of microcode errors in a fabricated part would seek to prioritize the speed and throughput of the part over flexibility in terms of options provided for making the corrections. In addition, if microcode errors are detected following shipment of parts, it is also desirable to provide techniques for distributing the corrections to end users in a way that the end users can implement the corrections in the field. Such corrections are commonly called patches, microcode patches, field ECs (i.e., “engineering change”), and other like terms.
A desirable approach for effecting microcode patches is to simply substitute, or replace, a given microcode instruction with one or more substitute microcode instructions. Accordingly, when the given microcode instruction is accessed in the microcode ROM, it is detected and its corresponding replacement microcode instructions are then substituted therefor. In theory, this approach is straightforward. But in practice, providing mechanisms for microcode patches is very complex because of a requirement that the throughput of a part not be disadvantageous affected in its operating environment.
In U.S. Pat. No. 6,438,664, McGrath et al. discuss the advantages and disadvantages of numerous microcode patch approaches to include fetching the replacement microcode from external memory at the instant when the offending microcode is encountered and fetching it prior to encountering the offending microcode. When fetched prior to encountering the offending microcode, the replacement microcode is stored in a volatile location and is substituted for the offending microcode when required. McGrath et al. additionally provide an amount of random access memory (RAM) in a processor for implementing microcode patches. The RAM is loaded with patches from external memory during operation of the processor and when a microcode line is accessed from the microcode ROM for which a patch is enabled, the patch is then fetched from the RAM and is executed instead of the microcode line. McGrath teaches several match registers within which are stored microcode ROM addresses which have associated patches in RAM. When a matching address is found, control is then passed to the RAM for substitution. McGrath et al. further note that while this approach is advantageous, it is also limiting in that switching control from the microcode ROM to the RAM causes a two-cycle bubble in the pipeline. That is, microcode patches according to the technique disclosed by McGrath et al. are provided at the cost of performance and throughput.
Consequently, it is desirable to provide an apparatus and method for executing a microcode patch that does not introduce delay into the pipeline stages of a microprocessor. It is furthermore desirable to provide a mechanism for performing real-time microcode substitutions where a replacement micro instruction is substituted for a micro instruction in microcode ROM without impacting performance of the microprocessor.
It is also desirable to provide a technique for implementing microcode patches that replace a single microcode ROM instruction with more than one substitute micro instruction, that is, a one-to-many microcode patch, where no additional delay is introduced as a result of accessing the microcode patch.
It is furthermore desirable to provide a flexible mechanism for accessing microcode patches which are stored in external memory that minimizes the impact to the microprocessor design for accessing the patches, and that allows for interlacing of macro and micro instructions in the substitute code. Such a mechanism would be very advantageous for use during debug of a microprocessor design and for simulation of proposed microcode routines corresponding to complex operations.
Additionally, it is desirable to provide a technique for loading microcode patches into a microprocessor from an external source that does not require execution of instructions by the microprocessor.
The present invention, among other applications, is directed to solving the above-noted problems and addresses other problems, disadvantages, and limitations of the prior art. The present invention provides a superior technique for performing microcode patches which is both fast and flexible. In one embodiment, an apparatus for performing a real-time microcode patch is provided. The apparatus includes a patch array and a mux. The patch array receives a microcode ROM address and determines that the microcode ROM address matches one of a plurality of entries within the patch array. When the microcode ROM address matches, the patch array outputs a corresponding patch instruction and asserts a hit signal. The mux receives the patch instruction from the patch array and a micro instruction corresponding to the microcode ROM address from a microcode ROM. The mux provides the micro instruction or the corresponding patch instruction to an instruction register based upon the state of the hit signal.
One aspect of the present invention contemplates an apparatus within a translate stage of a microprocessor, for implementing a microcode patch corresponding to a micro instruction stored in microcode ROM. The apparatus has a plurality of entries within an associative array, and a mux. The associative array receives a microcode ROM address corresponding to the micro instruction. One of the plurality of entries matches the microcode ROM address, and the one of the plurality of entries provides a patch instruction. The associative array asserts a hit signal responsive to reception of the microcode ROM address. The mux is coupled to the associative array and the microcode ROM. The mux receives the patch instruction and the micro instruction, and provides the micro instruction or the patch instruction to an instruction register based upon the state of the hit signal.
Another aspect of the present invention comprehends a method for performing a real-time microcode patch. The method includes: within a translate stage of a microprocessor, concurrently providing a microcode ROM address to a microcode ROM and to a patch array; determining that the microcode ROM address matches one of a plurality of entries within the patch array, outputting a corresponding patch instruction, and asserting a hit signal; and responsive to assertion of the hit signal, routing the corresponding patch instruction to an instruction register for execution.
These and other objects, features, and advantages of the present invention will become better understood with regard to the following description, and accompanying drawings where:
The following description is presented to enable one of ordinary skill in the art to make and use the present invention as provided within the context of a particular application and its requirements. Various modifications to the preferred embodiment will, however, be apparent to one skilled in the art, and the general principles defined herein may be applied to other embodiments. Therefore, the present invention is not intended to be limited to the particular embodiments shown and described herein, but is to be accorded the widest scope consistent with the principles and novel features herein disclosed.
In view of the above background discussion on mechanisms for making microcode patches within a present day microprocessor, a discussion highlighting the limitations of these mechanisms will be provided with reference to
Turning to
The address bus ADDR receive a microcode address from a next address register 109, whose input is coupled to the output of a mux 107. One of four mux inputs are selected as the mux output. The mux inputs are an incremented address that is generated by an address incrementer 104, a next entry point address, a branch target address, and a patch address. The address incrementer 104 increments a previous microcode address provided on bus ADDR to enable indexing of a micro instruction in a next sequential microcode address location, such as may be employed in sequences of micro instructions. The branch target address is provided from a branch target field of the instruction currently in the instruction register 110 to enable branches in microcode ROM 105 to be performed. The next entry point is the location in microcode ROM 105 containing micro instructions corresponding to a following micro instruction sequence. And the patch address is the location in microcode RAM 106 of a substitute micro instruction to replace an existing micro instruction stored in microcode ROM 105. An address sequencer 108 is coupled to the instruction register 110 and generates a select bus value which directs the mux 107 to select one of its four inputs. The address sequencer 108 determines what type of micro instruction is in the instruction register 110. If the micro instruction has a following micro instruction stored in microcode ROM 105 or RAM 106, then SEL is configured to direct the mux 107 to select the incremented address input. If the micro instruction is a branch instruction, then SEL is configured to direct the mux 107 to provide the branch target address to the next address register 109. If the micro instruction is the last micro instruction in a micro instruction sequence, then the address sequencer 108 directs the mux 107 via SEL to provide the next entry point address to the next address register. Typically, the next entry point address is generated by a direct translator (not shown) that has translated a following macro instruction. For clarity, interaction with the translator is not depicted.
The mechanism 100 also depicts eight match registers 102, each of which is coupled to a comparator 103. In addition, the comparator 103 receives the microcode address ADDR which is provided from the next address register 108. The comparator 103 outputs a select bus SEL[7:0] that selects one of eight entries in a look-up table 101 and which is also coupled to the address sequencer 108 to indicate that a microcode address has been detected for which a patch is implemented. Each of the eight entries in the look-up table 101 is a microcode patch address provided on bus PATCH ADDR as an input to the mux 107.
The configuration is
The configuration of
The present invention overcomes the above noted limitations by providing a microcode patch apparatus and method that does not introduce any additional pipeline delay as a result of accessing the patch, thus enabling one-to-one and one-to-many patches to be implemented without impacting processor throughput. The present invention also provides a flexible mechanism for implementing patches which can be tailored to provide for pure performance at the expense of flexibility, slight performance impact with greater flexibility, or maximum flexibility for purposes of simulation and debug. The present invention will now be discussed with reference to
Turning now to
The macro instructions are distributed to bypass logic 220, an instruction length decoder 211, a translator 212, and a control ROM 213. The control ROM 213 includes provisions for indexing and sequencing micro instructions from an internal microcode ROM as described above, and for performing one-to-one and one-to-many microcode patches in real time, as will be described in more detail below with reference to
The translation stage 200 according to the present invention is configured to perform the functions and operations as described above. The translation stage 200 comprises digital logic, analog logic, circuits, devices, or machine specific instructions, or a combination of digital logic, analog logic, circuits, devices, or machine specific instructions, or equivalent elements that are employed to perform the aforementioned functions and operations according to the present invention. The elements employed to perform the functions and operations within the translation stage 200 may be shared with other circuits, microcode, etc., that are employed to perform other functions and operations within the microprocessor. According to the scope of the present application, machine specific instructions is a term employed to refer to one or more machine specific instructions. A machine specific instruction is an instruction at the level that a unit executes. For example, machine specific instructions are directly executed by a reduced instruction set computer (RISC) microprocessor. For a complex instruction set computer (CISC) microprocessor such as an x86-compatible microprocessor, x86 instructions are translated into associated machine specific instructions, and the associated machine specific instructions are directly executed by a unit or units within the CISC microprocessor.
In a normal operating mode, macro instructions from an application program are fetched from external memory by the fetch stage and are provided over the macro instruction bus 201. Because macro instructions typically do not conform to a fixed length standard, the length decoder 211 evaluates the byte stream over the bus 201 to determine the length in bytes of each macro instruction. In one embodiment, the length in bytes of each macro instruction is provided to the translator 212 via a length bus LEN. The translator 212 accordingly retrieves the number of indicated bytes from the macro instruction bus 201. If a retrieved macro instruction is to be directly translated by the translator 212, then the translator 212 performs the translation of the macro instruction into associated native instructions. The native instructions are then provided from the translator 212 to the mux 214. If the retrieved macro instruction is to be decoded by the control ROM 413, then the translator 212 generates a corresponding microcode ROM entry point address and directs the control ROM 213 to retrieve the micro instructions from the microcode ROM therein by providing the entry point address to the control ROM 213 via a handoff bus HO. The control ROM 213 subsequently fetches the corresponding micro instructions from its internal microcode ROM and provides these micro instructions to the mux 214. Hence, in normal operating mode, the translator 212 or the control ROM 213 sources micro instructions to the native instruction bus 215 via the mux 214.
In one embodiment, the translate stage logic 200 is configured to access a machine specific register 202 that includes a bypass mode enable BE bit 203. The machine specific register 202 is not architecturally visible to the application programmer, but can be written through special procedures via an encrypted interface. For purposes of this application, it is sufficient to note that asserting the BE bit 203 places the microprocessor in a translator bypass mode and deasserting the BE bit 203 restores the microprocessor to normal operating mode.
During normal operation, a mode detector 221 within the bypass logic 220 monitors the state of the BE bit 203 and instructions appearing over the bus 201. If the BE bit 203 is asserted, then the mode detector 221 asserts BYPASS EN 224, thus enabling native instructions to be routed from the native instruction router 223 through the mux 214 to the native instruction bus 215 as well as native instructions which are provided by the translator 212 and control ROM 213. In one embodiment, DISABLE 222 inhibits the translator 212 and the control ROM 213 from performing instruction translation functions for a corresponding macro instruction that is fetched from the macro instruction bus 201. Consequently, when the translation stage 200 is operating in normal operating mode (i.e., the BE bit 203 is deasserted), the bypass logic 220 deasserts the bypass enable signal 224, thus disabling the native instruction router 223, and directing the mux 214 to select native instructions from either the translator 212 or the control ROM 213 for execution. When the translation stage 200 is placed in bypass mode (i.e., the BE bit 203 is asserted), then the bypass logic 220 asserts the bypass enable signal 224, thus enabling the native instruction router 223 and the mode detector 221.
In bypass mode, the mode detector controls the state of DISABLE 222. When DISABLE is deasserted, then the native instruction router 223 is disabled and the translator 212, and control ROM 213 operate as in normal mode. Macro instructions are fetched from the macro instruction bus 201 and are translated or retrieved by the control ROM 213. In this mode, however, a programmer may interlace native instructions within a macro instruction flow stored in memory by encapsulating the native instructions in a special “wrapper” macro instruction which is detected by the mode detector 221. In one embodiment, the wrapper macro instruction is an unused or invalid macro instruction which would otherwise cause an exception. Advantageously then, a debugger may place the microprocessor according to the present invention into a native bypass mode by setting the BE bit 203, but may continue to use all the macro instructions within the particular ISA. And to support debug or simulation functions, the programmer may employ the wrapper macro instruction to embed a native instruction therein, thus enabling programmable access to native resources which would not otherwise be made available. For instance, many native resources (e.g., temporary storage registers, counters, state indicators, etc.) within a microprocessor according to the present invention are employed during the execution of macro instructions, but are not accessible. Yet when the microprocessor is in bypass mode, the native instructions that provide access to these native resources may be interlaced among the macro instructions via use of the wrapper instruction.
In bypass mode, the mode detector 221 monitors instructions retrieved from the macro instruction bus 201. When a wrapper instruction is detected, the mode detector asserts DISABLE, thus enabling the native instruction router 223 and disabling the translator 212 and control ROM 213. When enabled, the native instruction router 223 strips the native instruction from within the wrapper macro instruction and routes the native instruction to the mux 214, and thus to the native instruction bus 215. In one embodiment, all native instructions are of a fixed number of bits. In a specific embodiment, native instructions are 38 bits. In one embodiment, the native instructions provided via the wrapper instruction, and those provided via the translator 212 and control ROM 213 as well, comprise an encoding of one or more machine specific instructions, which are subsequently translated into the one or more machine specific instructions by a machine specific translator (“microtranslator”), that is coupled to the native instruction bus 215. The machine specific instructions are provided by the microtranslator (not shown) to subsequent pipeline stages for execution. A more traditional embodiment contemplates native instructions provided via the wrapper instruction, translator 212, and control ROM 213 which are directly provided to subsequent pipeline stages for execution.
Now turning to
The one-to-one patch apparatus 300 includes a microcode ROM 305. In one embodiment, the microcode ROM has 20,480 (0x5000) 38-bit entries, and is disposed within a 32K-location microcode address space. Other embodiments are also contemplated. The microcode address space is accessed by a microcode address bus ADDR and the microcode ROM 305 provides micro instruction sequences as indexed by the value of ADDR to a mux 313. The output of the mux 313 is coupled to an instruction register 310. The instruction register 310 provides micro instructions to subsequent stages (not shown) in the microprocessor for execution. In one embodiment, the micro instructions are a plurality of machine specific instructions which have been encoded into a 38-bit entity. In this embodiment, contents of the instruction register 310 are provided to a microtranslator (not shown) for decoding of the encoded entities into machine specific instruction and for dispatch of the machine specific instructions to functional units in the pipeline.
The address bus ADDR receives a microcode address from a next address register 309, whose input is coupled to the output of a mux 307. One of three mux inputs are selected as the mux output. The mux inputs are an incremented address INC ADDR that is generated by an address incrementer 304, a next entry point address NEXT ENTRY POINT, and a branch target address BR TGT. The address incrementer 304 increments a previous microcode ROM address provided on bus ADDR to enable indexing of a micro instruction in a next sequential microcode address location, such as may be employed in sequences of micro instructions. The branch target address is provided from a branch target field of a micro instruction currently in the instruction register 310 to enable branches in microcode ROM 305 to be performed. These types of branches are also referred to as microcode branches. The next entry point is the location in the microcode ROM 305 containing micro instructions corresponding to a following micro instruction sequence such as may be associated with a next macro instruction. In one embodiment, the next entry point is provided to the patch apparatus via a handoff bus from a translator according to the present invention, such as the translator 212 and handoff bus 216 discussed above with reference to
The microcode patch apparatus 300 also includes a patch array 312 that is coupled to the microcode address bus ADDR, and which generates a patch instruction output PATCH INSTRUCTION and a hit output HIT. In one embodiment, the patch array 312 is a fast associative array providing for lookup of up to 32 entries based upon the value of ADDR. In another embodiment the patch array 312 comprises a content-addressable memory (CAM) comprising 32 entries. As one skilled in the art will appreciate, a CAM is configured to be supplied with a data entity input (i.e., the contents of the next address register 309 in this embodiment) and then performs an extremely fast search of its entire contents (i.e., 32 entries) to determine if there is an entry corresponding to the provided input. If so, then the CAM outputs an associated piece of data. According to the present invention, the associated piece of data is a patch instruction corresponding to the provided address. The patch instruction is output to the mux 313 and signal HIT is asserted. HIT is coupled to a select input of the mux 313. When HIT is not asserted, the mux 313 is directed to select the microcode ROM output. When HIT is asserted, the mux 313 is directed to select the patch instruction for routing to the instruction register 310 rather than the micro instruction output by the microcode ROM 305.
Consequently, the accessing of micro instructions corresponding to the supplied microcode ROM address on ADDR is performed by the patch array 312 concurrent with access in the microcode ROM 305, and the microcode patch instruction is provided to the mux 313 in parallel with the output of the microcode ROM 303. Because the patch array 312 is accessed in parallel with the microcode ROM 305, no additional delay is incurred when a one-to-one microcode patch according to the present invention is performed.
The patch apparatus 300 includes a patch loader 311 which is coupled to the patch array 312 via a load bus LOAD and which is operatively coupled to system memory 332 and BIOS ROM 333 via known techniques. The patch loader 311 is coupled to a reset signal RESET, a patch fuse F 322 within a fuse array 321, and is capable of accessing a patch bit P 324 within a machine specific register 323. The patch loader 311 is employed to load the contents of the patch array 312 with patch data 334 located in BIOS 333 or with patch data 332 located in system memory 331, as directed. In one embodiment, following reset or power-up, instructions within the BIOS 333 are executed to direct the patch loader 311 to check the state of the fuse 322, if the fuse 322 is in a state (e.g., not blown or blown) that indicates the patch data 334 should be loaded, then the patch loader 311 is configured to retrieve the patch data 334 from the BIOS ROM 333 and the patch loader 311 loads the patch array 312. In another embodiment, the state of the fuse 322, as detected by instructions in BIOS 333 upon power-up or reset, directs the patch loader 311 to retrieve the patch data from a designated patch data location 332 in system memory 331. In an embodiment that provides for implementation of patches prior to execution of instructions in the BIOS 333, the apparatus 300 is configured to evaluate the state of the fuse 322 following reset, but prior to fetching of instructions from the BIOS 333. If the fuse 322 state indicates that a patch is to be loaded, then the patch loader 311 fetches the patch data 334 from the designated area in the BIOS ROM 333 and loads the data into the patch array 312. After the patch has been loaded, instructions are fetched from BIOS 333 for booting of the microprocessor. This embodiment is advantageous in situations where instructions within the BIOS 333 require a patch in order to properly boot the microprocessor. The embodiment is furthermore advantageous for patching initialization constants and register values which must be at a specified state in order for BIOS 333 to boot the microprocessor properly. In another embodiment, the patch loader 311 monitors the state of the patch bit 324 in the machine specific register 323. In this embodiment, the machine specific register 323 is not architecturally visible, but can be written through special procedures. For example, one embodiment comprehends the capability to write to the register 321 via an encrypted interface that employs privileged instructions. For purposes of this application, it is sufficient to note that when the P bit 324 is asserted, the patch loader 311 is directed to retrieve the patch data 332 from system memory 331 and to load the patch array 312 with patch addresses and patch instructions.
Advantageously, and in contrast to present day microcode patch techniques, the apparatus 300 according to the present invention enables microcode patches to be loaded during power-up/reset, or as a result of executing privileged sequences of instructions. In addition, the present invention overcomes the current limitations in the art by providing a technique whereby patches that have been loaded are substituted on a one-for-one basis in real-time. No additional delay is incurred in the pipeline when microcode patches according to the present invention are executed. Consequently, the apparatus 300 of
Now referring to
At decision block 402, an evaluation is made to determine if a patch fuse 322 within a fuse array 321 in the microprocessor has been blown. If not, then flow proceeds to block 404. If the fuse 322 has been blown, thus indicating that patch data should be loaded into the patch array 312, then flow proceeds to block 403.
At block 403, a patch loader 311 retrieves the patch data from a designated patch data location 334 in BIOS memory 333 and loads the patch data into the patch array 312. Flow then proceeds to block 404.
At block 404, fetch stage logic begins fetching instructions for execution from BIOS 333 to configure and initialize the microprocessor and processing system. As instructions are executed, flow then proceeds to block 405.
At block 405, instructions within the program flow are successively fetched and executed by the microprocessor. Flow then proceeds to decision block 406
At decision block 406, an evaluation is made to determine if a patch field 324 within a machine specific register 323 has been set to a state that indicates a patch should be loaded into the patch array 312. If the patch field 324 indicates that a patch should not be loaded, then flow proceeds to block 408. If the patch field 324 indicates that a patch should be loaded, then flow proceeds to block 407.
At block 407, the patch loader 311 retrieves the patch data from a patch data location 332 in system memory 331 and loads the patch data into the patch array 312. Flow then proceeds to block 408.
At block 408, instruction fetch and execution by the microprocessor is continued. Macro instructions are directly translated into micro instructions and/or associated micro instructions are retrieved from microcode ROM 305. The addresses of locations in microcode ROM 305 are provided to the patch array 312 in parallel with provision of the addresses to the microcode ROM 305. Flow then proceeds to decision block 409.
At decision block 409, an evaluation is made to determine if a microcode address provided to the patch array 312 matches an address which was loaded. If not then flow proceeds to block 411. If an address does hit in the array 312, then flow proceeds to block 410.
At block 410, the patch array 312 outputs the patch instruction corresponding to the matched address and asserts signal HIT, thus directing the mux 313 to place the patch instruction into the instruction register 310 rather than the micro instruction retrieved from the microcode ROM 305. Flow then proceeds to block 411.
At block 411, instruction fetch and execution by the microprocessor is continued and flow proceeds to block 405.
The discussion with reference to
Turning to
The one-to-many patch apparatus 500 includes a microcode ROM 505. In one embodiment, the microcode ROM 505 has 20,480 (0x500) 38-bit entries, and is disposed within a 32K-location microcode address space. Other embodiments are also contemplated. The apparatus 500 also includes a microcode patch RAM 551 that occupies a portion of the unused locations in the microcode address space. In one embodiment, the microcode patch RAM 551 comprises 256 38-bit entries and occupies the upper 256 locations (i.e., locations 0x7F00 through 0x7FFF) in the microcode address space. The microcode address space, including both ROM 505 and RAM 551, is accessed by a microcode address bus ADDR and the microcode ROM 505 or microcode RAM 551, as appropriate, provides micro instruction sequences as indexed by the value of ADDR to a mux 513. The output of the mux 513 is coupled to an instruction register 510. The instruction register 510 provides micro instructions to subsequent stages (not shown) in the microprocessor for execution. In one embodiment, the micro instructions are a plurality of machine specific instructions which have been encoded into a 38-bit entity. In this embodiment, contents of the instruction register 510 are provided to a microtranslator (not shown) for decoding and dispatch to functional units.
The address bus ADDR receives a microcode address from a next address register 509, whose input is coupled to the output of a mux 507. One of three mux inputs are selected as the mux output. The mux inputs are an incremented address INC ADDR that is generated by an address incrementer 504, a next entry point address NEXT ENTRY POINT, and a branch target address BR TGT. The address incrementer 504 increments a previous microcode space address provided on bus ADDR to enable indexing of a micro instruction in a next sequential microcode address location, such as may be employed in sequences of micro instructions. The branch target address is provided from a branch target field of a micro instruction currently in the instruction register 510 to enable branches in microcode ROM 505 and/or microcode RAM 551 to be performed. The next entry point is the location in the microcode ROM 505 or microcode RAM 551 containing micro instructions corresponding to a following micro instruction sequence such as may be associated with a next macro instruction. In one embodiment, the next entry point NEXT ENTRY POINT is provided to the patch apparatus 500 via a handoff bus from a translator according to the present invention, such as the translator 212 and handoff bus 216 discussed with reference to
Like the one-to-one patch apparatus 300 described above with reference to
The patch RAM 551 is a volatile and loadable set of locations within the microcode address space, which are employed to provide for one-to-many microcode patches. When a microcode patch is required that comprises a plurality of micro instructions to replace a single micro instruction that is stored at a particular address in the microcode ROM 505, the replacement plurality of micro instructions is stored, as described below, in a replacement location in RAM 551, where the first micro instruction in the replacement plurality of micro instruction is stored in a first location in the RAM 551, and where a microcode branch instruction, having the first location in the RAM 551 as a branch target address, is loaded into the patch array 512 as data corresponding to the particular address. Consequently, when the particular address of the micro instruction to be patched is supplied on bus ADDR, it is also concurrently supplied to the patch array 512. And while the microcode ROM 505 contents are accessed, the stored microcode branch instruction is provided by the patch array 512 to the mux 513 in parallel with the output of the microcode ROM 505. Since the contents of ADDR resulted in a match in the patch array 512, signal HIT is asserted, and the microcode branch instruction retrieved from the patch array 512 is routed through the mux 513 to the instruction register 510, at no additional delay. The address sequencer 508 notes that a microcode branch instruction is within the instruction register 510 and the branch target address, designating said first location in the patch RAM 551, is input to the mux 507. Thus, the address sequencer 508 directs the mux 507 via SEL to select the branch target address, which is then supplied on ADDR to the microcode address space, and which selects said first location in the microcode RAM 551, that is, the location containing the first micro instruction in the one-to-many microcode patch. Subsequent micro instructions in the patch are accessed from the RAM 551 via incremented addresses provided by the address incrementer 504 until a final micro instruction in the patch sequence is fetched and detected by the address sequencer 508, which responds by directing the mux 507 to select the next entry point. In addition, the patch that is loaded into the RAM 551 may also include a micro instruction that causes a branch back to a location in the microcode ROM 505.
The patch apparatus 500 includes a patch loader 511 that is coupled to the patch array 512 via a load bus LOAD and to the patch RAM 551 via a load RAM bus LOADRM, and which is operatively coupled to system memory 532 and BIOS ROM 533 via known techniques. The patch loader 511 is coupled to a reset signal RESET, a patch fuse F 522 within a fuse array 521, and is capable of accessing a patch bit P 524 within a machine specific register 523. The patch loader 511 is employed to load the contents of the patch array 512 and the patch RAM 551 with patch data 534 located in BIOS 533 or with patch data 532 located in system memory 531, as directed.
Operationally, loading of the patch array 512 and patch RAM 551 are performed in substantially the same manner as the patch array 312 is loaded within the apparatus 300 of
Consequently, the apparatus 500 according to the present invention enables one-to-many microcode patches to be loaded during power-up/reset, or during the execution of instructions which are not typically architecturally provided for, and provides for accessing the one-to-many microcode patch in a manner significantly faster than present day techniques. The apparatus 500 of
Now referring to
At decision block 602, an evaluation is made to determine if a patch fuse 522 within a fuse array 521 in the microprocessor has been blown. If not, then flow proceeds to block 604. If the fuse 522 has been blown, thus indicating that patch data should be loaded into the patch array 512 and patch RAM 551, then flow proceeds to block 603.
At block 603, a patch loader 511 retrieves the patch data from a designated patch data location 534 in BIOS 533 and loads the patch data into the patch array 512 and patch RAM 551. The patch data comprises a microcode branch instruction which is loaded into the patch array 512, where the target address for the microcode branch instruction is a location in the patch RAM 551 for the first micro instruction in the one-to-many microcode patch. The patch data also comprises the one-to-many microcode patch, which is loaded by the patch loader 511 into the patch RAM 551 at the target location. Flow then proceeds to block 604.
At block 604, fetch stage logic begins fetching instructions for execution from BIOS 533 to configure and initialize the microprocessor and processing system. As instructions are executed, flow then proceeds to block 605.
At block 605, instructions within the program flow are successively fetched and executed by the microprocessor. Flow then proceeds to decision block 606.
At decision block 606, an evaluation is made to determine if a patch field 524 within a machine specific register 523 has been set to a state that indicates a patch should be loaded into the patch array 512 and patch RAM 551. If the patch field 524 indicates that a patch should not be loaded, then flow proceeds to block 608. If the patch field 524 indicates that a patch should be loaded, then flow proceeds to block 607.
At block 607, the patch loader 511 retrieves the patch data from a patch data location 332 in system memory 533 and loads the patch data into the patch array 512 and patch RAM 551 as described above with reference to block 604. Flow then proceeds to block 608.
At block 608, instruction fetch and execution by the microprocessor is continued. Macro instructions are directly translated into micro instructions and/or associated micro instructions are retrieved from microcode ROM 505. The addresses of locations in microcode ROM 505 are provided to the patch array 512 in parallel with provision of the addresses to the microcode ROM 505. Flow then proceeds to decision block 609.
At decision block 609, an evaluation is made to determine if a microcode address provided to the patch array 512 matches an address which was loaded. If not then flow proceeds to block 613. If an address does hit in the array 512, then flow proceeds to block 610.
At block 610, the patch array 512 outputs a substitute instruction corresponding to the matched address and asserts signal HIT, thus directing the mux 513 to place the substitute instruction into the instruction register 510 rather than the micro instruction retrieved from the microcode ROM 505. Flow then proceeds to decision block 611.
At decision block 611, an evaluation is made to determine if the substitute instruction in the instruction register 510 is a microcode branch instruction having a target address in the patch RAM 551. If so, the block proceeds to block 612. If not, then How proceeds to block 613.
At block 612, the microcode branch is performed by providing the branch target address of the microcode branch instruction to bus ADDR, and the location in the patch RAM 551 having the first micro instruction in the one-to-many patch is retrieved. Flow then proceeds to block 613
At block 613, instruction fetch and execution by the microprocessor is continued and flow proceeds to block 605.
Now that the performance of one-to-one and one-to-many microcode patches according to the present invention has been described, attention is now directed to
Turning to
In addition to elements common to the apparatus 500 of
The apparatus 700 additionally shows an enable bypass sequence of micro instructions 752 loaded within the patch RAM 751. The enable bypass sequence 752 is employed by the translate stage to store the context of an immediately preceding macro instruction that is translated and executed prior to entering translator bypass mode. The context is stored in a save context array 754. In one embodiment, the save context array 754 is one or more machine specific registers. Exemplary context information includes the address of the immediately preceding macro instruction, its next sequential instruction pointer, etc. It is required that sufficient information associated with the immediately preceding macro instruction be stored in the save context array 754 so that execution of the normal macro instruction program flow can be restored upon termination of translator bypass mode. For restoring the normal macro instruction flow, a restore context sequence of micro instructions 753 is loaded into the patch RAM 753. To terminate translator bypass mode, a microcode branch instruction is executed in the bypass code 735 that has a branch target address specifying the location of the restore context microcode sequence 753. In one embodiment, the restore context sequence may be permanently stored in the microcode ROM 705 instead of loaded into the patch RAM 751.
In operation, the patch array 712 and patch RAM 751 are loaded as described above. A microcode branch instruction is loaded into the patch array 712 at the microcode ROM address of the micro instruction which is to be replaced, simulated, tested, etc. The microcode branch instruction in the patch array 712 includes a branch target address of a first micro instruction in the enable bypass sequence 752 which is loaded in the patch RAM 751. Hence, when the address of the micro instruction to be replaced is provided on ADDR, the patch array 712 causes the microcode branch instruction to be issued and executed, thus directing flow to the enable bypass sequence 752 in the patch RAM 751. The enable bypass sequence 752 comprises micro instructions that direct the interrupt/execution/switch logic 755 to assert the BE bit 729, thus indicating to translation logic 200, as described with reference to
While the microprocessor is in translator bypass mode, interrupts and other task control transfer events (hereinafter collectively referred to as “interrupts”) are signaled to the int/exc/swtch logic 755 via known mechanisms. As part of processing an interrupt, the state of bit BE 729 in the register 727 is checked to determine if the microprocessor is in native bypass mode. If so, this state is saved prior to processing the interrupt by asserting bit BO 730 in the flags register 728. It is required that the flags register 728 be an architectural register within the microprocessor whose state is preserved during task control transfers and whose state is restored upon control returns. In an x86 embodiment, the flags register 728 comprises the EFLAGS register in an x86-compatible microprocessor and bit BO 730 comprises bit 31 of the EFLAGS register. If an interrupt occurs when bit BE 729 is asserted (indicating that bypass mode is enabled), then the int/exc/swtch logic 755 asserts the BO bit 730 in the flags register 728 prior to processing the interrupt. In addition, bit BE 729 is cleared, thereby disabling native bypass mode. Should a wrapper macro instruction be encountered within an interrupt service routine or other application to which control has been passed prior to returning from the interrupt, then the instruction translation stage 200 will interpret the wrapper macro instruction according to architectural specifications of the controlling ISA, which in one embodiment comprises causing an exception. In this manner, application programs can employ interlaced native instructions without causing problems for operating system modules that service these events or for other application programs to which program control is transferred.
Upon return from an interrupting event to an application program that employs native bypass mode, the int/exc/swtch logic 755 checks the state of the restored BO bit 730 in the flags register 728. If the bit 730 indicates that native bypass mode was previously enabled, then bit BE 729 is set to re-enable bypass mode. Control is then returned to the application program and subsequent macro instructions (including wrapper instructions) are again executed. The status of the BO bit 730 can also be checked by the application program that employs native bypass mode to determine if an interrupt has occurred that may have changed the state or contents of any native resource that was being used prior to the interrupt occurring. Since native resources are not architecturally specified to persist through interrupting events, an interrupt handler or other application program to which program control, was transferred may have changed the state of a native resource currently being used by the application program that employs bypass mode. In an alternative embodiment, the flags register 728 comprises a native register within the microprocessor whose contents are cleared by execution of a native instruction within a program flow while in native bypass mode. According to the alternative embodiment, the int/exc/swtch logic 755 sets the value of this native register 728 to a non-zero value upon return from interrupt, thereby providing a means whereby the native bypass application can determine if an interrupt has occurred. In a further embodiment, the flags register 728 comprises both an architectural flags register having a BO bit 730 and a native register that operate as described above to provide two indications to a native bypass application that an interrupt has occurred.
As noted above, translator bypass mode is terminated by executing a microcode branch to the restore context sequence 753. In one embodiment, the restore context sequence directs the translate stage to reload the macro instruction context stored in the save context array 754 and which directs the interrupt/execution/switch logic 755 to deassert bit BE 729, thus placing the translate stage 200 back in normal operating mode. A final microcode instruction in the restore context sequence 753 is executed indicates to the address sequencer 708 that a final micro instruction in a sequence has been executed and which results in a next entry point being provided to the mux 707 which corresponds to a macro instruction following the one whose context was saved prior to entering translator bypass mode. An alternative embodiment is contemplated as well where the he enable bypass sequence 752 comprises micro instructions that direct the interrupt/execution/switch logic 755 to completely disable interrupts during translator bypass mode operations. According to this embodiment, the only operations that need to be performed in order to preserve context is to save the current interrupt mask, mask the interrupts during translator bypass mode, and then restore the interrupt mask prior to returning to normal operating mode.
Now turning to
The native instruction field 802 comprises one or more micro instructions which are to be executed. In one embodiment, one micro instruction is embedded within the native instruction field 802. In another embodiment, a 38-bit encoding of three micro instructions is embedded within the native instruction field 802. In a third embodiment, a plurality of micro instructions to be sequentially executed are provided in the native instruction field 802.
Referring to
When the last wrapper instruction 904 is provided to the translate stage, bypass logic strips the native instruction from within, which is a microcode branch to a first location in the context restore sequence 753 stored within the patch RAM 751. Accordingly, program flow branches to the restore sequence 753, which restores the context for normal operation and terminates translator bypass mode.
Those skilled in the art should appreciate that they can readily use the disclosed conception and specific embodiments as a basis for designing or modifying other structures for carrying out the same purposes of the present invention, and that various changes, substitutions and alterations can be made herein without departing from the scope of the invention as defined by the appended claims.
