Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Industry

CPC
G11C2216/22

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups

Current Industry

G11C2216/22Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Industries

Patents Grantslast 30 patents

Information Patent Grant
Memory device and memory system including the same
- Patent number 11,733,921
- Issue date Aug 22, 2023
- SK hynix Inc.
- Won Jae Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared error check and correct logic for multiple data banks
- Patent number 11,646,092
- Issue date May 9, 2023
- Micron Technology, Inc.
- Susumu Takahashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for configuring array columns and rows for acc...
- Patent number 11,373,707
- Issue date Jun 28, 2022
- Silicon Storage Technology, Inc.
- Hieu Van Tran
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system for detecting erased page including memory cells with...
- Patent number 11,163,646
- Issue date Nov 2, 2021
- SK Hynix Inc.
- Yeong Dong Gim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory with multi-plane mixed sub-block programming
- Patent number 11,101,001
- Issue date Aug 24, 2021
- SanDisk Technologies LLC
- Henry Chin
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent read and reconfigured write operations in a memory device
- Patent number 11,094,375
- Issue date Aug 17, 2021
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with bit line controlled multi-plane mixed sub-...
- Patent number 11,087,849
- Issue date Aug 10, 2021
- SanDisk Technologies LLC
- Henry Chin
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized scan interval
- Patent number 11,056,156
- Issue date Jul 6, 2021
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Read-once memory
- Patent number 11,049,567
- Issue date Jun 29, 2021
- Proton World International N.V.
- Michael Peeters
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Shared error check and correct logic for multiple data banks
- Patent number 10,957,413
- Issue date Mar 23, 2021
- Micron Technology, Inc.
- Susumu Takahashi
- G11 - INFORMATION STORAGE
Information Patent Grant
Independent NAND memory operations by plane
- Patent number 10,877,696
- Issue date Dec 29, 2020
- Intel Corporation
- Yogesh B. Wakchaure
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent read and reconfigured write operations in a memory device
- Patent number 10,636,480
- Issue date Apr 28, 2020
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized scan interval
- Patent number 10,573,357
- Issue date Feb 25, 2020
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 10,468,094
- Issue date Nov 5, 2019
- TOSHIBA MEMORY CORPORATION
- Hayao Kasai
- G11 - INFORMATION STORAGE
Information Patent Grant
Optimized scan interval
- Patent number 10,446,197
- Issue date Oct 15, 2019
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Hybrid flash memory structure
- Patent number 10,403,342
- Issue date Sep 3, 2019
- Aspiring Sky Co. Limited
- Zhijiong Luo
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for configuring array columns and rows for acc...
- Patent number 10,340,010
- Issue date Jul 2, 2019
- Silicon Storage Technology, Inc.
- Hieu Van Tran
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for configuring array columns and rows for acc...
- Patent number 10,269,432
- Issue date Apr 23, 2019
- Silicon Storage Technology, Inc.
- Hieu Van Tran
- G11 - INFORMATION STORAGE
Information Patent Grant
Interrupted write operation in a serial interface memory with a por...
- Patent number 10,248,592
- Issue date Apr 2, 2019
- Micron Technology, Inc.
- Graziano Mirichigni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system for accessing memory dies during program operations a...
- Patent number 10,048,873
- Issue date Aug 14, 2018
- SK Hynix Inc.
- Seok-Hoon Jung
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent memory operations
- Patent number 9,600,414
- Issue date Mar 21, 2017
- Micron Technology, Inc.
- Luca Porzio
- G11 - INFORMATION STORAGE
Information Patent Grant
Interrupted write memory operation in a serial interface memory wit...
- Patent number 9,442,867
- Issue date Sep 13, 2016
- Micron Technology, Inc.
- Graziano Mirichigni
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device, memory system and method of operating...
- Patent number 9,311,257
- Issue date Apr 12, 2016
- SK hynix Inc.
- Sang Hyun Song
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent operation of plural flash memories
- Patent number 9,047,956
- Issue date Jun 2, 2015
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Tien-Chun Yang
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor apparatus
- Patent number 8,976,567
- Issue date Mar 10, 2015
- SK Hynix Inc.
- Dong Keun Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
NAND-based hybrid NVM design that integrates NAND and NOR in 1-die...
- Patent number 8,775,719
- Issue date Jul 8, 2014
- APlus Flash Technology, Inc.
- Peter W. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Monolithic read-while-write flash memory device
- Patent number 8,706,949
- Issue date Apr 22, 2014
- Sandisk IL Ltd.
- Dana Gross
- G11 - INFORMATION STORAGE
Information Patent Grant
Concurrent memory operations
- Patent number 8,700,879
- Issue date Apr 15, 2014
- Micron Technology, Inc.
- Luca Porzio
- G11 - INFORMATION STORAGE
Information Patent Grant
Interruption of write memory operations to provide faster read acce...
- Patent number 8,645,637
- Issue date Feb 4, 2014
- Micron Technology, Inc.
- Graziano Mirichigni
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device for concurrent and pipelined memory operations
- Patent number 8,645,617
- Issue date Feb 4, 2014
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
- Publication number 20220129197
- Publication date Apr 28, 2022
- SK HYNIX INC.
- Won Jae CHOI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SHARED ERROR CHECK AND CORRECT LOGIC FOR MULTIPLE DATA BANKS
- Publication number 20210183462
- Publication date Jun 17, 2021
- Micron Technology, Inc.
- Susumu Takahashi
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR CONCURRENT PROGRAMMING
- Publication number 20210134369
- Publication date May 6, 2021
- SANDISK TECHNOLOGIES LLC
- Zhiping Zhang
- G11 - INFORMATION STORAGE
Information Patent Application
READ-ONCE MEMORY
- Publication number 20200185037
- Publication date Jun 11, 2020
- Proton World International N.V.
- Michael PEETERS
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
OPTIMIZED SCAN INTERVAL
- Publication number 20200160894
- Publication date May 21, 2020
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
SHARED ERROR CHECK AND CORRECT LOGIC FOR MULTIPLE DATA BANKS
- Publication number 20200135291
- Publication date Apr 30, 2020
- Micron Technology, Inc.
- Susumu Takahashi
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND OPERATION METHOD THEREOF
- Publication number 20200050515
- Publication date Feb 13, 2020
- SK HYNIX INC.
- Yeong Dong GIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-VOLATILE MEMORY WITH MULTI-PLANE MIXED SUB-BLOCK PROGRAMMING
- Publication number 20190348127
- Publication date Nov 14, 2019
- SANDISK TECHNOLOGIES LLC
- Henry Chin
- G11 - INFORMATION STORAGE
Information Patent Application
NON-VOLATILE MEMORY WITH BIT LINE CONTROLLED MULTI-PLANE MIXED SUB-...
- Publication number 20190348129
- Publication date Nov 14, 2019
- SANDISK TECHNOLOGIES LLC
- Henry Chin
- G11 - INFORMATION STORAGE
Information Patent Application
Method And Apparatus For Configuring Array Columns And Rows For Acc...
- Publication number 20190272876
- Publication date Sep 5, 2019
- Silicon Storage Technology, Inc.
- Hieu Van Tran
- G11 - INFORMATION STORAGE
Information Patent Application
OPTIMIZED SCAN INTERVAL
- Publication number 20190122705
- Publication date Apr 25, 2019
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
OPTIMIZED SCAN INTERVAL
- Publication number 20190066739
- Publication date Feb 28, 2019
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE
- Publication number 20180166130
- Publication date Jun 14, 2018
- Adesto Technologies Corporation
- Gideon Intrater
- G11 - INFORMATION STORAGE
Information Patent Application
VOLATILE MEMORY ARCHITECUTRE IN NON-VOLATILE MEMORY DEVICES AND REL...
- Publication number 20180158527
- Publication date Jun 7, 2018
- Micron Technology, Inc.
- Emanuele Confalonieri
- G11 - INFORMATION STORAGE
Information Patent Application
Concurrent Read And Write Memory Operations In A Serial Interface M...
- Publication number 20140250249
- Publication date Sep 4, 2014
- Micron Technology, Inc.
- Graziano Mirichigni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT MEMORY OPERATIONS
- Publication number 20140229702
- Publication date Aug 14, 2014
- Micron Technology Inc.
- LUCA PORZIO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR APPARATUS
- Publication number 20140050021
- Publication date Feb 20, 2014
- SK HYNIX INC.
- Dong Keun KIM
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENT OPERATION OF PLURAL FLASH MEMORIES
- Publication number 20140003141
- Publication date Jan 2, 2014
- Taiwan Semiconductor Manufacturing Co., LTD
- Tien-Chun YANG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20130100739
- Publication date Apr 25, 2013
- RENESAS ELECTRONICS CORPORATION
- Hiroaki TANIZAKI
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENT OPERATION OF PLURAL FLASH MEMORIES
- Publication number 20130064017
- Publication date Mar 14, 2013
- Taiwan Semiconductor Manufacturing Co., LTD
- Tien-Chun YANG
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENT MEMORY OPERATIONS
- Publication number 20130054905
- Publication date Feb 28, 2013
- Micron Technology, Inc.
- Luca Porzio
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT OPERATION OF PLURAL FLASH MEMORIES
- Publication number 20120163086
- Publication date Jun 28, 2012
- Taiwan Semiconductor Manufacturing Co., LTD
- Tien-Chung Yang
- G11 - INFORMATION STORAGE
Information Patent Application
CONCURRENT READ AND WRITE MEMORY OPERATIONS IN A SERIAL INTERFACE M...
- Publication number 20120124317
- Publication date May 17, 2012
- Micron Technology, Inc.
- Graziano Mirichigni
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Non-Volatile Memory With Improved Sensing By Reducing Source Line C...
- Publication number 20120113715
- Publication date May 10, 2012
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Application
FLEXIBLE MEMORY OPERATIONS IN NAND FLASH DEVICES
- Publication number 20120113721
- Publication date May 10, 2012
- MOSAID TECHNOLOGIES INCORPORATED
- Jin-Ki KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multiple Plane, Non-Volatile Memory With Synchronized Control
- Publication number 20120020161
- Publication date Jan 26, 2012
- RAMBUS INC.
- Brent Steven Haukness
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERLEAVED MEMORY PROGRAM AND VERIFY METHOD, DEVICE AND SYSTEM
- Publication number 20120002474
- Publication date Jan 5, 2012
- ROUND ROCK RESEARCH, LLC
- Daniel H. Doyle
- G11 - INFORMATION STORAGE
Information Patent Application
REDUNDANT DATA STORAGE FOR UNIFORM READ LATENCY
- Publication number 20110258362
- Publication date Oct 20, 2011
- Moray McLaren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Non-Volatile Memory Device For Concurrent And Pipelined Memory Oper...
- Publication number 20110208905
- Publication date Aug 25, 2011
- RAMBUS INC.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
Non-Volatile Memory With Improved Sensing By Reducing Source Line C...
- Publication number 20110075480
- Publication date Mar 31, 2011
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE

Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory device and memory system including the same

Shared error check and correct logic for multiple data banks

Method and apparatus for configuring array columns and rows for acc...

Memory system for detecting erased page including memory cells with...

Non-volatile memory with multi-plane mixed sub-block programming

Concurrent read and reconfigured write operations in a memory device

Non-volatile memory with bit line controlled multi-plane mixed sub-...

Optimized scan interval

Read-once memory

Shared error check and correct logic for multiple data banks

Independent NAND memory operations by plane

Concurrent read and reconfigured write operations in a memory device

Optimized scan interval

Semiconductor memory device

Optimized scan interval

Hybrid flash memory structure

Method and apparatus for configuring array columns and rows for acc...

Method and apparatus for configuring array columns and rows for acc...

Interrupted write operation in a serial interface memory with a por...

Memory system for accessing memory dies during program operations a...

Concurrent memory operations

Interrupted write memory operation in a serial interface memory wit...

Semiconductor memory device, memory system and method of operating...

Concurrent operation of plural flash memories

Semiconductor apparatus

NAND-based hybrid NVM design that integrates NAND and NOR in 1-die...

Monolithic read-while-write flash memory device

Concurrent memory operations

Interruption of write memory operations to provide faster read acce...

Memory device for concurrent and pipelined memory operations

Patents Applicationslast 30 patents

MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

SHARED ERROR CHECK AND CORRECT LOGIC FOR MULTIPLE DATA BANKS

METHOD FOR CONCURRENT PROGRAMMING

READ-ONCE MEMORY

OPTIMIZED SCAN INTERVAL

SHARED ERROR CHECK AND CORRECT LOGIC FOR MULTIPLE DATA BANKS

MEMORY SYSTEM AND OPERATION METHOD THEREOF

NON-VOLATILE MEMORY WITH MULTI-PLANE MIXED SUB-BLOCK PROGRAMMING

NON-VOLATILE MEMORY WITH BIT LINE CONTROLLED MULTI-PLANE MIXED SUB-...

Method And Apparatus For Configuring Array Columns And Rows For Acc...

OPTIMIZED SCAN INTERVAL

OPTIMIZED SCAN INTERVAL

CONCURRENT READ AND RECONFIGURED WRITE OPERATIONS IN A MEMORY DEVICE

VOLATILE MEMORY ARCHITECUTRE IN NON-VOLATILE MEMORY DEVICES AND REL...

Concurrent Read And Write Memory Operations In A Serial Interface M...

CONCURRENT MEMORY OPERATIONS

SEMICONDUCTOR APPARATUS

CONCURRENT OPERATION OF PLURAL FLASH MEMORIES

SEMICONDUCTOR DEVICE

CONCURRENT OPERATION OF PLURAL FLASH MEMORIES

CONCURRENT MEMORY OPERATIONS

CONCURRENT OPERATION OF PLURAL FLASH MEMORIES

CONCURRENT READ AND WRITE MEMORY OPERATIONS IN A SERIAL INTERFACE M...

Non-Volatile Memory With Improved Sensing By Reducing Source Line C...

FLEXIBLE MEMORY OPERATIONS IN NAND FLASH DEVICES

Multiple Plane, Non-Volatile Memory With Synchronized Control

INTERLEAVED MEMORY PROGRAM AND VERIFY METHOD, DEVICE AND SYSTEM

REDUNDANT DATA STORAGE FOR UNIFORM READ LATENCY

Non-Volatile Memory Device For Concurrent And Pipelined Memory Oper...

Non-Volatile Memory With Improved Sensing By Reducing Source Line C...