TREA

Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups

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  • CPC
  • G11C2216/00
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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES

Current Industry

G11C2216/00Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups

Sub Industries

G11C2216/02Structural aspects of erasable programmable read-only memories G11C2216/04Nonvolatile memory cell provided with a separate control gate for erasing the cells G11C2216/06Floating gate cells in which the floating gate consists of multiple isolated silicon islands G11C2216/08Nonvolatile memory wherein data storage is accomplished by storing relatively few electrons in the storage layer G11C2216/10Floating gate memory cells with a single polysilicon layer G11C2216/12Reading and writing aspects of erasable programmable read-only memories G11C2216/14Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory G11C2216/16Flash programming of all the cells in an array, sector or block simultaneously G11C2216/18Flash erasure of all the cells in an array, sector or block simultaneously G11C2216/20Suspension of programming or erasing cells in an array in order to read other cells in it G11C2216/22Nonvolatile memory in which reading can be carried out from one memory bank or array whilst a word or sector in another bank or array is being erased or programmed simultaneously G11C2216/24Nonvolatile memory in which programming can be carried out in one memory bank or array whilst a word or sector in another bank or array is being erased simultaneously G11C2216/26Floating gate memory which is adapted to be one-time programmable [OTP] G11C2216/28Floating gate memory programmed by reverse programming G11C2216/30Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data
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