Overlapped cache accessing

Industry

CPC
G06F12/0855

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Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/0855Overlapped cache accessing

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing commands in a sequential write required zone model
- Patent number 12,253,949
- Issue date Mar 18, 2025
- SanDisk Technologies, Inc.
- Rotem Sela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore, multibank, fully concurrent coherence controller
- Patent number 12,223,165
- Issue date Feb 11, 2025
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache blocking for dispatches
- Patent number 12,189,534
- Issue date Jan 7, 2025
- Advanced Micro Devices, Inc.
- Saurabh Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Creating secure pipeline cache objects using differential privacy t...
- Patent number 12,182,902
- Issue date Dec 31, 2024
- Google LLC
- Robert Fraser
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Opportunistic late depth testing to prevent stalling for overlappin...
- Patent number 12,182,023
- Issue date Dec 31, 2024
- Intel Corporation
- Saikat Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual network pre-arbitration for deadlock avoidance and enhanced...
- Patent number 12,182,398
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 12,159,030
- Issue date Dec 3, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 12,141,601
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache for coherent system
- Patent number 12,141,435
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load-store pipeline selection for vectors
- Patent number 12,086,067
- Issue date Sep 10, 2024
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive credit-based replenishment threshold used for transaction...
- Patent number 12,079,471
- Issue date Sep 3, 2024
- Texas Instruments Incorporated
- Daniel Brad Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to facilitate read-modify-write support in a...
- Patent number 12,072,814
- Issue date Aug 27, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo-random way selection
- Patent number 12,045,644
- Issue date Jul 23, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline arbitration
- Patent number 12,014,206
- Issue date Jun 18, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with write miss merging
- Patent number 12,007,907
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache that supports draining write-miss entries
- Patent number 12,001,345
- Issue date Jun 4, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load-store unit dual tags and replays
- Patent number 11,983,538
- Issue date May 14, 2024
- Cadence Design Systems, Inc.
- Robert T. Golla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce read-modify-write cycles for non-al...
- Patent number 11,940,929
- Issue date Mar 26, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMING INSTRUCTION FETCH PIPELINE SYNCHRONIZATION (IFPS) IN PRO...
- Publication number 20250130953
- Publication date Apr 24, 2025
- Ampere Computing LLC
- Bret Leslie Toll
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20250094044
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE CACHE FOR COHERENT SYSTEM
- Publication number 20250060873
- Publication date Feb 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL COHERENCE OPERATIONS
- Publication number 20250028551
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERRUPTING MEMORY ACCESS DURING BACKGROUND OPERATIONS ON A MEMORY...
- Publication number 20250013572
- Publication date Jan 9, 2025
- QUALCOMM Incorporated
- Sonali JABREVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSING COMMANDS IN A SEQUENTIAL WRITE REQUIRED ZONE MODEL
- Publication number 20240378151
- Publication date Nov 14, 2024
- Western Digital Technologies, Inc.
- Rotem Sela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Side Cache Request Handling
- Publication number 20240378152
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-RANDOM WAY SELECTION
- Publication number 20240345868
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE ARBITRATION
- Publication number 20240281278
- Publication date Aug 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RECALL PENDING CACHE LINE EVICTION
- Publication number 20240248846
- Publication date Jul 25, 2024
- Micron Technology, Inc.
- Dean E. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...
- Publication number 20240232100
- Publication date Jul 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE DEVICE AND OPERATION METHOD THEREOF
- Publication number 20240232087
- Publication date Jul 11, 2024
- SK HYNIX INC.
- Seon Ju LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECTOR CACHE FOR COMPRESSION
- Publication number 20240232094
- Publication date Jul 11, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE
- Publication number 20240193098
- Publication date Jun 13, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
- Publication number 20240184446
- Publication date Jun 6, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER WITH CACHING AND NON-CACHING MODES
- Publication number 20240152385
- Publication date May 9, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20240143516
- Publication date May 2, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION
- Publication number 20240104026
- Publication date Mar 28, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING

Overlapped cache accessing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Write merging on stores with different privilege levels

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for multi-banked victim cache with dual datapath

Processing commands in a sequential write required zone model

Multicore, multibank, fully concurrent coherence controller

Atomic compare and swap in a coherent cache system

Aggressive write flush scheme for a victim cache

Methods and apparatus to reduce bank pressure using aggressive writ...

Cache blocking for dispatches

Fully pipelined read-modify-write support

Creating secure pipeline cache objects using differential privacy t...

Opportunistic late depth testing to prevent stalling for overlappin...

Methods and apparatus for allocation in a victim cache system

Virtual network pre-arbitration for deadlock avoidance and enhanced...

Multicore shared cache operation engine

Methods and apparatus for read-modify-write support in multi-banked...

Global coherence operations

Victim cache with dynamic allocation of entries

Atomic operations and histogram operations in a cache pipeline

Configurable cache for coherent system

Methods and apparatus for eviction in dual datapath victim cache sy...

Load-store pipeline selection for vectors

Adaptive credit-based replenishment threshold used for transaction...

Methods and apparatus to facilitate read-modify-write support in a...

Pseudo-random way selection

Pipeline arbitration

Victim cache with write miss merging

Victim cache that supports draining write-miss entries

Load-store unit dual tags and replays

Methods and apparatus to reduce read-modify-write cycles for non-al...

Patents Applicationslast 30 patents

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

PERFORMING INSTRUCTION FETCH PIPELINE SYNCHRONIZATION (IFPS) IN PRO...

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

MULTICORE SHARED CACHE OPERATION ENGINE

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

CONFIGURABLE CACHE FOR COHERENT SYSTEM

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

GLOBAL COHERENCE OPERATIONS

INTERRUPTING MEMORY ACCESS DURING BACKGROUND OPERATIONS ON A MEMORY...

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

PROCESSING COMMANDS IN A SEQUENTIAL WRITE REQUIRED ZONE MODEL

Memory Side Cache Request Handling

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

PSEUDO-RANDOM WAY SELECTION

VICTIM CACHE WITH WRITE MISS MERGING

PIPELINE ARBITRATION

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

RECALL PENDING CACHE LINE EVICTION

METHODS AND APPARATUS TO REDUCE READ-MODIFY-WRITE CYCLES FOR NON-AL...

STORAGE DEVICE AND OPERATION METHOD THEREOF

SECTOR CACHE FOR COMPRESSION

METHODS AND APPARATUS TO FACILITATE ATOMIC OPERATIONS IN VICTIM CACHE

MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS

CONTROLLER WITH CACHING AND NON-CACHING MODES

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

HYBRID VICTIM CACHE AND WRITE MISS BUFFER WITH FENCE OPERATION