Preventing false-lock or pseudo-lock of the PLL

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H03L2207/14

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HELECTRICITY H03Electronic circuits H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES H03L2207/00Indexing scheme relating to automatic control of frequency or phase and to synchronisation

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H03L2207/14Preventing false-lock or pseudo-lock of the PLL

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Patents Grantslast 30 patents

Information Patent Grant
Semiconductor integrated circuit and receiver device
- Patent number 11,552,643
- Issue date Jan 10, 2023
- Kioxia Corporation
- Fumihiko Tachibana
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low-power, low-noise millimeter wavelength frequency synthesizer
- Patent number 10,992,303
- Issue date Apr 27, 2021
- The Regents of the University of California
- Hao Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Phase locked loop with sub-harmonic locking prevention functionality
- Patent number 9,559,707
- Issue date Jan 31, 2017
- LATTICE SEMICONDUCTOR CORPORATION
- Kexin Luo
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable slew rate phase locked loop
- Patent number 9,350,362
- Issue date May 24, 2016
- Thomas & Betts International, LLC
- Justin Walraven
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
Integrated circuit with calibrated pulling effect correction
- Patent number 9,007,131
- Issue date Apr 14, 2015
- Broadcom Corporation
- Ahmad Mirzaei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Clock data recovery with out-of-lock detection
- Patent number 8,929,500
- Issue date Jan 6, 2015
- Texas Instruments Incorporated
- Tonmoy S. Mukherjee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
VCO control circuit and method thereof, fast locking PLL and method...
- Patent number 8,629,728
- Issue date Jan 14, 2014
- MStar Semiconductor, Inc.
- Yao-Chi Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
CDR circuit
- Patent number 8,570,078
- Issue date Oct 29, 2013
- Kabushiki Kaisha Toshiba
- Kiyohito Sato
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Delay locked loop
- Patent number 8,368,446
- Issue date Feb 5, 2013
- Hynix Semiconductor Inc.
- Jae-Min Jang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock loss detection circuit for PLL clock switchover
- Patent number 8,350,596
- Issue date Jan 8, 2013
- Altera Corporation
- Lip Kai Soh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock generating circuit, semiconductor device including the same,...
- Patent number 8,344,773
- Issue date Jan 1, 2013
- Elpida Memory, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for the controlled delay of an input signal
- Patent number 8,264,261
- Issue date Sep 11, 2012
- Infineon Technologies AG
- Werner Grollitsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor integrated circuit device
- Patent number 8,179,733
- Issue date May 15, 2012
- Renesas Electronics Corporation
- Yuichi Okuda
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock generating circuit, semiconductor device including the same,...
- Patent number 8,130,015
- Issue date Mar 6, 2012
- Elpida Memory, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Delay locked loop circuit
- Patent number 8,120,396
- Issue date Feb 21, 2012
- Canon Kabushiki Kaisha
- Masaaki Iwane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor integrated circuit device
- Patent number 7,936,621
- Issue date May 3, 2011
- Renesas Electronics Corporation
- Yuichi Okuda
- G11 - INFORMATION STORAGE
Information Patent Grant
False frequency lock detector
- Patent number 7,936,853
- Issue date May 3, 2011
- Applied Micro Circuits Corporation
- Simon Pang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Semiconductor integrated circuit device
- Patent number 7,602,665
- Issue date Oct 13, 2009
- Renesas Technology Corp.
- Yuichi Okuda
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit device
- Patent number 7,411,805
- Issue date Aug 12, 2008
- Renesas Technology Corp.
- Yuichi Okuda
- G11 - INFORMATION STORAGE
Information Patent Grant
Data de-skew method and system
- Patent number 7,406,616
- Issue date Jul 29, 2008
- Vitesse Semiconductor Corporation
- Norm Hendrickson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Erroneous phase lock detection circuit
- Patent number 7,397,881
- Issue date Jul 8, 2008
- Fujitsu Limited
- Daisuke Yamazaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
False lock detection circuit and false lock detection method, PLL c...
- Patent number 7,366,269
- Issue date Apr 29, 2008
- Sony Corporation
- Hiroki Ishida
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay locked loop with selectable delay
- Patent number 7,323,915
- Issue date Jan 29, 2008
- Honeywell International, Inc.
- Jon E. Josephson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Reset-free delay-locked loop
- Patent number 7,298,191
- Issue date Nov 20, 2007
- Infineon Technologies AG
- Hai Jie Wu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
System and method for lock detection of a phase-locked loop circuit
- Patent number 7,268,629
- Issue date Sep 11, 2007
- Kabushiki Kaisha Toshiba
- Satoru Takase
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Delay locked loop harmonic detector and associated method
- Patent number 7,170,323
- Issue date Jan 30, 2007
- Pixelworks, Inc.
- Robert Greenberg
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Processor core clock generation circuits
- Patent number 7,134,036
- Issue date Nov 7, 2006
- Sun Microsystems, Inc.
- Xiujun Guan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fast detection of incorrect sampling in an oversampling clock and d...
- Patent number 7,085,970
- Issue date Aug 1, 2006
- International Business Machines Corporation
- Gareth J. Nicholls
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor integrated circuit device
- Patent number 7,072,242
- Issue date Jul 4, 2006
- Renesas Technology Corp.
- Yuichi Okuda
- G11 - INFORMATION STORAGE
Information Patent Grant
Interlaced delay-locked loops for controlling memory-circuit timing
- Patent number 7,042,265
- Issue date May 9, 2006
- Micron Technology, Inc.
- Ronnie M. Harrison
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
PROGRAMMABLE SLEW RATE PHASE LOCKED LOOP
- Publication number 20150097602
- Publication date Apr 9, 2015
- Thomas & Betts International, LLC
- Justin Walraven
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT WITH CALIBRATED PULLING EFFECT CORRECTION
- Publication number 20140191811
- Publication date Jul 10, 2014
- BROADCOM CORPORATION
- Ahmad Mirzaei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTEGRATED CIRCUIT WITH CALIBRATED PULLING EFFECT CORRECTION
- Publication number 20140191812
- Publication date Jul 10, 2014
- BROADCOM CORPORATION
- Ahmad Mirzaei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTEGRATED CIRCUIT WITH CALIBRATED PULLING EFFECT CORRECTION
- Publication number 20140191815
- Publication date Jul 10, 2014
- BROADCOM CORPORATION
- Ahmad Mirzaei
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SYNCHRONIZING CIRCUIT AND CLOCK DATA RECOVERY CIRCUIT INCLUDING THE...
- Publication number 20140118040
- Publication date May 1, 2014
- LAPIS SEMICONDUCTOR CO., LTD.
- Akira NAKAYAMA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock Data Recovery With Out-Of-Lock Detection
- Publication number 20130188762
- Publication date Jul 25, 2013
- TEXAS INSTRUMENTS INCORPORATED
- Tonmoy S. Mukherjee
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CDR CIRCUIT
- Publication number 20130076411
- Publication date Mar 28, 2013
- Kabushiki Kaisha Toshiba
- Kiyohito Sato
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
DELAY LOCKED LOOP
- Publication number 20120268180
- Publication date Oct 25, 2012
- Jae-Min Jang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK GENERATING CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME,...
- Publication number 20120134223
- Publication date May 31, 2012
- Elpida Memory, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
- Publication number 20110182127
- Publication date Jul 28, 2011
- Renesas Electronics Corporation
- YUICHI OKUDA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
VCO Control Circuit and Method Thereof, Fast Locking PLL and Method...
- Publication number 20110080196
- Publication date Apr 7, 2011
- Mstar Semiconductor, Inc.
- Yao-Chi Wang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Method and Apparatus for the Controlled Delay of an Input Signal
- Publication number 20110074480
- Publication date Mar 31, 2011
- INFINEON TECHNOLOGIES AG
- Werner Grollitsch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Clock generating circuit, semiconductor device including the same,...
- Publication number 20110057697
- Publication date Mar 10, 2011
- Elpida Memory, Inc.
- Kazutaka Miyano
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DELAY LOCKED LOOP CIRCUIT
- Publication number 20110032009
- Publication date Feb 10, 2011
- Canon Kabushiki Kaisha
- Masaaki Iwane
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
- Publication number 20100027369
- Publication date Feb 4, 2010
- RENESAS TECHNOLOGY CORP.
- Yuichi Okuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
False frequency lock detector
- Publication number 20090122935
- Publication date May 14, 2009
- Simon Pang
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
- Publication number 20080273404
- Publication date Nov 6, 2008
- RENESAS TECHNOLOGY CORP.
- Yuichi Okuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Delay locked loop with selectable delay
- Publication number 20070164800
- Publication date Jul 19, 2007
- Honeywell International Inc.
- Jon E. Josephson
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for lock detection of a phase-locked loop circuit
- Publication number 20060267642
- Publication date Nov 30, 2006
- Satoru Takase
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Reset-free delay-locked loop
- Publication number 20060132205
- Publication date Jun 22, 2006
- Infineon Technologies AG
- Hai Jie Wu
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Data de-skew method and system
- Publication number 20060129869
- Publication date Jun 15, 2006
- Vitesse Semiconductor Corporation
- Norm Hendrickson
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Semiconductor integrated circuit device
- Publication number 20060087909
- Publication date Apr 27, 2006
- RENESAS TECHNOLOGY CORP.
- Yuichi Okuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
False lock detection circuit and false lock detection method, PLL c...
- Publication number 20050238129
- Publication date Oct 27, 2005
- SONY CORPORATION
- Hiroki Ishida
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Erroneous phase lock detection circuit
- Publication number 20050123087
- Publication date Jun 9, 2005
- FUJITSU LIMITED
- Daisuke Yamazaki
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dummy delay line based DLL and method for clocking in pipeline ADC
- Publication number 20050110671
- Publication date May 26, 2005
- Chun Chieh Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor integrated circuit device
- Publication number 20050052944
- Publication date Mar 10, 2005
- RENESAS TECHNOLOGY CORP.
- Yuichi Okuda
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Interlaced delay-locked loolps for controlling memory-circuit timing
- Publication number 20050007157
- Publication date Jan 13, 2005
- Micron Technology, Inc.
- Ronnie M. Harrison
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
DLL circuit and camcorder using DLL circuit
- Publication number 20040239389
- Publication date Dec 2, 2004
- Canon Kabushiki Kaisha
- Yasushi Matsuno
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Harmonic correction in phase-locked loops
- Publication number 20040090890
- Publication date May 13, 2004
- Daniel Y. Abramovitch
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Semiconductor integrated circuit
- Publication number 20040036087
- Publication date Feb 26, 2004
- Junichi Okamura
- H03 - BASIC ELECTRONIC CIRCUITRY

Preventing false-lock or pseudo-lock of the PLL

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Semiconductor integrated circuit and receiver device

Low-power, low-noise millimeter wavelength frequency synthesizer

Phase locked loop with sub-harmonic locking prevention functionality

Programmable slew rate phase locked loop

Integrated circuit with calibrated pulling effect correction

Clock data recovery with out-of-lock detection

VCO control circuit and method thereof, fast locking PLL and method...

CDR circuit

Delay locked loop

Clock loss detection circuit for PLL clock switchover

Clock generating circuit, semiconductor device including the same,...

Method and apparatus for the controlled delay of an input signal

Semiconductor integrated circuit device

Clock generating circuit, semiconductor device including the same,...

Delay locked loop circuit

Semiconductor integrated circuit device

False frequency lock detector

Semiconductor integrated circuit device

Semiconductor integrated circuit device

Data de-skew method and system

Erroneous phase lock detection circuit

False lock detection circuit and false lock detection method, PLL c...

Delay locked loop with selectable delay

Reset-free delay-locked loop

System and method for lock detection of a phase-locked loop circuit

Delay locked loop harmonic detector and associated method

Processor core clock generation circuits

Fast detection of incorrect sampling in an oversampling clock and d...

Semiconductor integrated circuit device

Interlaced delay-locked loops for controlling memory-circuit timing

Patents Applicationslast 30 patents

PROGRAMMABLE SLEW RATE PHASE LOCKED LOOP

INTEGRATED CIRCUIT WITH CALIBRATED PULLING EFFECT CORRECTION

INTEGRATED CIRCUIT WITH CALIBRATED PULLING EFFECT CORRECTION

INTEGRATED CIRCUIT WITH CALIBRATED PULLING EFFECT CORRECTION

SYNCHRONIZING CIRCUIT AND CLOCK DATA RECOVERY CIRCUIT INCLUDING THE...

Clock Data Recovery With Out-Of-Lock Detection

CDR CIRCUIT

DELAY LOCKED LOOP

CLOCK GENERATING CIRCUIT, SEMICONDUCTOR DEVICE INCLUDING THE SAME,...

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

VCO Control Circuit and Method Thereof, Fast Locking PLL and Method...

Method and Apparatus for the Controlled Delay of an Input Signal

Clock generating circuit, semiconductor device including the same,...

DELAY LOCKED LOOP CIRCUIT

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

False frequency lock detector

SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE

Delay locked loop with selectable delay

System and method for lock detection of a phase-locked loop circuit

Reset-free delay-locked loop

Data de-skew method and system

Semiconductor integrated circuit device

False lock detection circuit and false lock detection method, PLL c...

Erroneous phase lock detection circuit

Dummy delay line based DLL and method for clocking in pipeline ADC

Semiconductor integrated circuit device

Interlaced delay-locked loolps for controlling memory-circuit timing

DLL circuit and camcorder using DLL circuit

Harmonic correction in phase-locked loops

Semiconductor integrated circuit