1. Technical Field
This Specification pertains generally to data communication receivers, and more specifically to recovering clock and data from a received data communication signal.
2. Related Art
In telecommunication and other data communication systems it is common to a transmit data with the associated clock embedded with the data. At the receive end, clock-data recovery (CDR) circuits extract the embedded clock information from received data, generating a recovered clock that is frequency and phase aligned to the embedded clock corresponding to the data transmission frequency. The recovered clock is then used to recover the transmitted/received data as retimed data that is frequency and phase aligned to the transmitted data.
CDR circuits commonly use a phase and frequency detector (PFD) to recover a clock aligned in frequency and phase to the embedded clock: a frequency acquisition loop includes a frequency detector (FD) that acquires a frequency close to the frequency of the embedded clock, and a phase tracking loop includes a phase detector (PD) that then phase aligns the recovered clock to the (frequency aligned) embedded clock. The recovered clock is used to generate recovered data from the received data, locked to the recovered clock which is aligned in frequency and phase to the embedded clock.
In some applications, the CDR includes a reference clock in the frequency acquisition loop, while for other applications, the CDR architecture is reference-less and only the position of the data edges is known.
Particularly (but not exclusively) for reference-less CDR designs, some mechanism for detecting an out-of-lock condition, including false lock, is advantageous. In false lock, the CDR circuit “locks” to a frequency different than the frequency of the transmitted data. In response to out-of-lock detection, the CDR can initiate a frequency/phase acquisition cycle to acquire true lock.
This Specification discloses and claims methods and apparatus for clock-data recovery with out-of-lock (including false lock) detection, such as used in telecommunication and other data communication applications. The Detailed Description and Figures set forth example embodiments that illustrate various aspects and technical features of the invention defined by the Claims.
Aspects and technical features of the claimed invention used at the receive end of a communications link to recover clock and data from a received data signal an embedded clock, include: (a) performing frequency and phase acquisition cycles to generate, from the received data signal, a recovered clock signal corresponding in frequency and phase to the embedded clock; (b) generating, from the received data signal and the recovered clock signal, a retimed/recovered data signal with positive and negative edges retimed by a predetermined amount relative to corresponding positive and negative edges of the received data signal; (c) sampling the recovered data signal with positive and negative edges of the received data signal, and generating an edge detection signal indicating for at least some of the samples whether a corresponding edge of the recovered data signal is detected; and (d) signaling an out-of-lock condition if the edge detection signal indicates failure to detect a predetermined number of edges of the recovered data signal (referred to as missed edges). In example embodiments, the edge detection signal is generated either (a) by detecting the occurrence of missed edges, or (b) by counting the number of missed edges.
Other aspects and technical features of the invention disclosed and claimed in this Specification will be apparent to those skilled in the art from the Description, Figures and Claims.
This Detailed Description, together with the Figures, discloses example embodiments, and example applications, illustrating various aspects and technical features of the invention claimed in this Specification. However, these example embodiments and example applications, are illustrative only and should not be construed to limit the scope of the invention disclosed in this Specification, which is defined by the Claims. Other embodiments and applications will be apparent to those skilled in the art from the Description, Figures and Claims. Known circuits, functions and operations are not described in detail to avoid unnecessarily obscuring the principles and features of the claimed invention.
In brief overview, this Specification discloses and claims methods and apparatus for clock-data recovery with out-of-lock detection for use at the receive end of a communication link in data is transmitted an embedded clock. In an example methodology, out-of-lock detection is accomplished by (a) recovering from a received data signal a recovered clock corresponding in frequency an phase to the embedded clock, (b) recovering from the received data signal a retimed/recovered data signal using the recovered clock, with positive and negative edges retimed by a predetermined amount, (b) detecting an out-of-lock condition by sampling the retimed/recovered data with the positive and negative edges of the received data, and signaling an out-of-lock condition based on a failure of such sampling to detect corresponding edges of the retimed/recovered data signal (i.e., missed edges).
In an example embodiment of an architecture for clock-data recovery with out-of-lock detection, clock-data recovery circuitry is configured (a) to perform frequency and phase acquisition cycles, and generate a recovered clock signal corresponding in frequency and phase to the embedded clock; and (b) to generate from the received data signal and the recovered clock signal, a retimed/recovered data signal with positive and negative edges retimed by a predetermined amount relative to corresponding positive and negative edges of the received data signal. Edge detection circuitry is configured to sample the retimed/recovered data signal with positive and negative edges of the received data signal, and generate an edge detection signal indicating for at least some of the samples whether a corresponding edge of the recovered data signal is detected. Out-of-lock detection circuitry is configured to signal an out-of-lock condition if the edge detection signal indicates failure to detect a predetermined number of edges of the recovered data signal (i.e., missed edges).
In another example embodiment, the edge detection circuitry is configured to generate the edge detection signal based on (a) sampling the recovered data signal with the non-inverted received data signal to sample with positive edges, and with an inverted received data signal to sample with negative edges, generating the edge detection signal based on the results of sampling with at least some of the positive and negative edges of the received data signal. In alternate example embodiments, the edge detection circuitry is configured to generate the edge detection signal based on either (a) the occurrence of missed edges, or (b) counting the number of missed edges. In another example embodiment, the retimed/recovered data signal is generated with positive and negative edges retimed by substantially 0.5 unit interval relative to the corresponding positive and negative edges of the received data signal.
In accordance with conventional clock-data recovery, the example reference-less CDR 100 includes a phase/frequency detector (PFD) 101 for clock recovery and a data retimer 111 for recovering/retiming data. The received data signal is input to PFD 101, which generates a recovered clock, and to retimer 111 which recovers and retimes data based on the recovered clock. As described further in connection with
Implementations for the PFD 101 and retimer 111 are a design choice, the design details of which are not required to enable practicing the invention claimed and disclosed in this Specification. For the example embodiment, PFD 101 is conventionally configured for frequency and phase acquisition cycles, including a frequency detector 104 and a phase detector (PD) 103, which establish nested frequency and phase acquisition loops that control an UP/DN charge pump 105. The charge pump provides a frequency tuning voltage through a loop filter 107 to a VCO (voltage controlled oscillator) 109. VCO 109 outputs a recovered clock that in true lock will be frequency and phase locked to the clock embedded with the received data.
In operation, CDR/PFD 101 initiates a frequency/phase acquisition cycle in which FD 104 and the frequency acquisition loop adjust the VOC frequency to the frequency of the embedded clock. At the end of the frequency acquisition cycle, FD 104 may be shut down, and CDR/PFD 101 initiates a phase acquisition/alignment cycle with PD 103 and the phase acquisition loop adjusting VOC phase to align with the phase of the embedded clock. When true lock is acquired, the recovered clock output from VCO 109 will be aligned in frequency and phase with the received data (i.e., the clock embedded in the received data).
Retimer 111 recovers data from the received data synchronized to the recovered clock provided by the clock recovery PFD 101. Retimer 111 operates conventionally to retime the recovered data, in effect retiming the positive/negative edges of the retimed/recovered data signal by a predetermined amount relative to the corresponding edges of the received data. Retiming operation is described further in connection with
The example CDR architecture includes an out-of-lock detector 120. Out-of-lock detector 120 detects out-of-lock conditions, including false lock, by sampling the retimed/recovered data with the positive and negative edges of the received data. An out-of-lock condition is detected based on a failure of received data sampling to detect corresponding edges of the retimed/recovered data, which are referred to as missed edges. As used in this Specification, unless otherwise indicated by the context, an out-of-lock condition includes false lock in which the PFD “locks” to a frequency different than the frequency of the embedded clock, requiring initiation of a frequency/phase acquisition cycle to acquire true lock.
For both example embodiments, out-of-lock detector 120 includes D flip-flops (DFF) 201 and 203. Retimed/recovered data from retimer 111 is the data input to both DFFs-DFF 201 is clocked by the positive edge of the received data, and DFF 203 is clocked by the inverted received data corresponding to the negative edge. That is, the DFFs operate to sample the retimed/recovered data with the positive and negative edges of the received data (respectively DFF 201 and 203), capturing the state of the retimed/recovered data signal at the positive and negative edges of the received data signal.
The output of DFF 201 and the inverted output of DFF 203 constitute edge detection signals respectively for the positive and negative edges of the retimed/recovered data signal. These edge detection signals are used to detect an out-of-lock condition corresponding to the detection (by received data sampling) of missed edges in generating the retimed/recovered data based on the recovered clock (thereby indicating a failure to achieve true lock).
Jitter tolerance is a CDR parameter indicating maximum input jitter for a specified bit error rate (BER), commonly specified in terms of a unit interval (UI) which is one clock period (or bit period). One UI of jitter tolerance results in the recovered data being 0.5 UI away from the received data edges.
For the example embodiments, the retimer retimes the positive/negative edges of the retimed/recovered data by substantially 0.5 UI. That is, the positive/negative edges of the retimed/recovered data are shifted substantially 0.5 UI relative to the positive/negative sampling edges of the received data.
As a result, the positive/negative sampling edges of the received data are positioned substantially in the center of the bit period of the retimed/recovered data. In true lock, as illustrated by the
If an out-of-lock condition (including false lock) occurs, the retimed/recovered data will not lock to the received data (i.e., frequency/phase alignment has not achieved true lock between the embedded and recovered clocks), and the recovered clock will “walk” across the retimed/received data. That is, the edge detection signals (from DFFs 201/203) will indicate missed edges of the retimed/recovered data based on a failure or received data sampling to detect corresponding edges of the retimed/recovered data.
Particularly for false lock conditions, referring also to the example CDR architecture in
Referring to
For the example embodiment in
At the end of the CDR acquisition cycle, an out-of-lock detection cycle is initiated (
If an out-of-lock condition is not detected (
If an out-of-lock condition occurs (
The example embodiments of apparatus and methods for implementing the out-of-lock detection as disclosed in this Specification are described in the context of a reference-less CDR/PFD architecture, although the disclosed out-of-lock detection methodology is adaptable to different, including reference-based, CDR architectures. In addition, the out-of-lock detection methodology is operable to detect out-of-lock conditions in the presence of ambient jitter. Out-of-lock detection will include false lock detection. Advantageously, during true lock, the output of the detector is constant so that memory requirements are minimized.
While this Specification has disclosed certain example embodiments and generally associated methods, the principles and features of the claimed invention may be implemented in or with any suitably arranged device or system, and various design choices are possible without departing from the scope of the invention as defined by the Claims. Accordingly, the above description of exemplary embodiments does not define or constrain the scope of the invention, which shall be defined by the following Claims.
Priority is hereby claimed under USC §119(e) to U.S. Provisional Application 61/590,097, filed Jan. 24, 2012).
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Number | Date | Country | |
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20130188762 A1 | Jul 2013 | US |
Number | Date | Country | |
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61590097 | Jan 2012 | US |