Providing cache or TLB in specific location of a processing system

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures

Current Industry

G06F2212/30Providing cache or TLB in specific location of a processing system

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Memory system managing counters
- Patent number 12,229,412
- Issue date Feb 18, 2025
- Kioxia Corporation
- Kazuhiro Fukutomi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore, multibank, fully concurrent coherence controller
- Patent number 12,223,165
- Issue date Feb 11, 2025
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid memory module
- Patent number 12,213,548
- Issue date Feb 4, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,182,035
- Issue date Dec 31, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual network pre-arbitration for deadlock avoidance and enhanced...
- Patent number 12,182,398
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 12,159,030
- Issue date Dec 3, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for shared virtual memory to manage data coher...
- Patent number 12,147,346
- Issue date Nov 19, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache for coherent system
- Patent number 12,141,435
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning sparse computation mechanism
- Patent number 12,141,891
- Issue date Nov 12, 2024
- Intel Corporation
- Eriko Nurvitadhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,124,383
- Issue date Oct 22, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data aggregation processing apparatus and method, and storage medium
- Patent number 12,118,004
- Issue date Oct 15, 2024
- YUSUR TECHNOLOGY CO., LTD.
- Guihai Yan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quasi-volatile system-level memory
- Patent number 12,105,650
- Issue date Oct 1, 2024
- SUNRISE MEMORY CORPORATION
- Robert D. Norman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-side page activity recorder
- Patent number 12,093,189
- Issue date Sep 17, 2024
- Amazon Technologies, Inc.
- Ali Ghassan Saidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive credit-based replenishment threshold used for transaction...
- Patent number 12,079,471
- Issue date Sep 3, 2024
- Texas Instruments Incorporated
- Daniel Brad Wu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURABLE CACHE FOR COHERENT SYSTEM
- Publication number 20250060873
- Publication date Feb 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...
- Publication number 20250061060
- Publication date Feb 20, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPPORTUNISTIC CLEANING OF COHERENCE DIRECTORIES TO REDUCE CACHE-COH...
- Publication number 20250053513
- Publication date Feb 13, 2025
- Samsung Electronics Co., Ltd.
- Samantika Subramaniam Sury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGEMENT-SUBSYSTEM-BASED SOFTWARE RAID CONFIGURATION SYSTEM
- Publication number 20250044984
- Publication date Feb 6, 2025
- Dell Products L.P.
- Nikhith Ganigarakoppal Kantharaju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR STORING AND ACCESSING A DATA OPERAND IN A MEMORY UNIT
- Publication number 20250036571
- Publication date Jan 30, 2025
- BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACIÓN
- John D. DAVIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TELEMETRY-CAPABLE MEMORY SUB-SYSTEM
- Publication number 20240427701
- Publication date Dec 26, 2024
- Micron Technology, Inc.
- David Andrew Roberts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable System on a Chip
- Publication number 20240411695
- Publication date Dec 12, 2024
- Apple Inc.
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUASI-VOLATILE SYSTEM-LEVEL MEMORY
- Publication number 20240411711
- Publication date Dec 12, 2024
- Sunrise Memory Corporation
- Robert D. Norman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA MIGRATION USING TRANSACTION ORDER IN SOLID STATE DRIVES
- Publication number 20240411457
- Publication date Dec 12, 2024
- Dell Products L.P.
- Seungmin Oh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPRESSION TECHNIQUES
- Publication number 20240403259
- Publication date Dec 5, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable System on a Chip
- Publication number 20240370371
- Publication date Nov 7, 2024
- Apple Inc.
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURATION INDEPENDENT SURFACE LAYOUT FOR DATA PROCESSING
- Publication number 20240311298
- Publication date Sep 19, 2024
- Intel Corporation
- Guadalupe J. Garcia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING METHOD AND APPARATUS, AND CACHE, PROCESSOR AND ELEC...
- Publication number 20240289275
- Publication date Aug 29, 2024
- HYGON INFORMATION TECHNOLOGY CO., LTD.
- Haifeng ZHAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PHOTOGRAPHING METHOD AND RELATED APPARATUS
- Publication number 20240273029
- Publication date Aug 15, 2024
- Honor Device Co., Ltd.
- Jirun XU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES
- Publication number 20240264952
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR DATA ACCESS AND SHARING
- Publication number 20240256483
- Publication date Aug 1, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-MODE TIERED MEMORY CACHE CONTROLLER
- Publication number 20240256446
- Publication date Aug 1, 2024
- VMware LLC
- Andreas Georg Nowatzyk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE
- Publication number 20240256464
- Publication date Aug 1, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Bipin Prasad Heremagalur Ramaprasad
- G06 - COMPUTING CALCULATING COUNTING

Providing cache or TLB in specific location of a processing system

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Memory system managing counters

Multicore, multibank, fully concurrent coherence controller

Hybrid memory module

Atomic compare and swap in a coherent cache system

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Graphics processor data access and sharing

Methods and apparatus to reduce bank pressure using aggressive writ...

Fully pipelined read-modify-write support

Multi-tile memory management

Methods and apparatus for allocation in a victim cache system

Systems and methods for cache optimization

Virtual network pre-arbitration for deadlock avoidance and enhanced...

Multicore shared cache operation engine

Cache structure and utilization

Methods and apparatus for read-modify-write support in multi-banked...

Method and apparatus for shared virtual memory to manage data coher...

Victim cache with dynamic allocation of entries

Systolic disaggregation within a matrix accelerator architecture

Atomic operations and histogram operations in a cache pipeline

Configurable cache for coherent system

Machine learning sparse computation mechanism

Systems and methods for cache optimization

Data aggregation processing apparatus and method, and storage medium

Methods and apparatus for eviction in dual datapath victim cache sy...

Quasi-volatile system-level memory

Multi-tile memory management

Compression techniques

Memory-side page activity recorder

Adaptive credit-based replenishment threshold used for transaction...

Patents Applicationslast 30 patents

CONFIGURABLE CACHE FOR COHERENT SYSTEM

METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...

OPPORTUNISTIC CLEANING OF COHERENCE DIRECTORIES TO REDUCE CACHE-COH...

MANAGEMENT-SUBSYSTEM-BASED SOFTWARE RAID CONFIGURATION SYSTEM

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

METHOD FOR STORING AND ACCESSING A DATA OPERAND IN A MEMORY UNIT

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

MULTI-TILE MEMORY MANAGEMENT

TELEMETRY-CAPABLE MEMORY SUB-SYSTEM

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

CACHE STRUCTURE AND UTILIZATION

Scalable System on a Chip

QUASI-VOLATILE SYSTEM-LEVEL MEMORY

DATA MIGRATION USING TRANSACTION ORDER IN SOLID STATE DRIVES

COMPRESSION TECHNIQUES

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

Scalable System on a Chip

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

CONFIGURATION INDEPENDENT SURFACE LAYOUT FOR DATA PROCESSING

VICTIM CACHE WITH WRITE MISS MERGING

DATA PROCESSING METHOD AND APPARATUS, AND CACHE, PROCESSOR AND ELEC...

PHOTOGRAPHING METHOD AND RELATED APPARATUS

VICTIM CACHE THAT SUPPORTS DRAINING WRITE-MISS ENTRIES

GRAPHICS PROCESSOR DATA ACCESS AND SHARING

MULTI-MODE TIERED MEMORY CACHE CONTROLLER

PREFETCH KILL AND REVIVAL IN AN INSTRUCTION CACHE