Providing cache or TLB in specific location of a processing system

Industry

CPC
G06F2212/30

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2212/00Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures

Current Industry

G06F2212/30Providing cache or TLB in specific location of a processing system

Industries

Patents Grantslast 30 patents

Information Patent Grant
Architectural support for persistent applications
- Patent number 12,298,897
- Issue date May 13, 2025
- National Technology & Engineering Solutions of Sandia, LLC
- Mazen Alwadi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write merging on stores with different privilege levels
- Patent number 12,292,839
- Issue date May 6, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Photographing method and related apparatus
- Patent number 12,292,835
- Issue date May 6, 2025
- HONOR DEVICE CO., LTD.
- Jirun Xu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and apparatuses for precise last branch record ev...
- Patent number 12,288,072
- Issue date Apr 29, 2025
- Jonathan Combs
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid victim cache and write miss buffer with fence operation
- Patent number 12,265,477
- Issue date Apr 1, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for multi-banked victim cache with dual datapath
- Patent number 12,259,826
- Issue date Mar 25, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for managing data bias in a graphics processin...
- Patent number 12,260,470
- Issue date Mar 25, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data initialization techniques
- Patent number 12,242,414
- Issue date Mar 4, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system managing counters
- Patent number 12,229,412
- Issue date Feb 18, 2025
- Kioxia Corporation
- Kazuhiro Fukutomi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore, multibank, fully concurrent coherence controller
- Patent number 12,223,165
- Issue date Feb 11, 2025
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid memory module
- Patent number 12,213,548
- Issue date Feb 4, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic compare and swap in a coherent cache system
- Patent number 12,216,591
- Issue date Feb 4, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for improving cache efficiency and utilization
- Patent number 12,210,477
- Issue date Jan 28, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Aggressive write flush scheme for a victim cache
- Patent number 12,210,463
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Graphics processor data access and sharing
- Patent number 12,204,487
- Issue date Jan 21, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to reduce bank pressure using aggressive writ...
- Patent number 12,197,347
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fully pipelined read-modify-write support
- Patent number 12,189,540
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,182,062
- Issue date Dec 31, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for allocation in a victim cache system
- Patent number 12,182,038
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,182,035
- Issue date Dec 31, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual network pre-arbitration for deadlock avoidance and enhanced...
- Patent number 12,182,398
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 12,159,030
- Issue date Dec 3, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache structure and utilization
- Patent number 12,153,541
- Issue date Nov 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for shared virtual memory to manage data coher...
- Patent number 12,147,346
- Issue date Nov 19, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache for coherent system
- Patent number 12,141,435
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning sparse computation mechanism
- Patent number 12,141,891
- Issue date Nov 12, 2024
- Intel Corporation
- Eriko Nurvitadhi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DATA INITIALIZATION TECHNIQUES
- Publication number 20250156371
- Publication date May 15, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE
- Publication number 20250139019
- Publication date May 1, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM
- Publication number 20250117340
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250117356
- Publication date Apr 10, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM
- Publication number 20250117341
- Publication date Apr 10, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACHINE LEARNING SPARSE COMPUTATION MECHANISM
- Publication number 20250117873
- Publication date Apr 10, 2025
- Intel Corporation
- Eriko Nurvitadhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PRE-FETCHING ADDRESS TRANSLATION FOR COMPUTATION OFFLOADING
- Publication number 20250117337
- Publication date Apr 10, 2025
- Samsung Electronics Co., Ltd.
- Aditya Madhusudan DESHPANDE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ACCELERATION UNIT WITH MODULAR ARCHITECTURE
- Publication number 20250117352
- Publication date Apr 10, 2025
- Alan D. Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION
- Publication number 20250103548
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20250103546
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR CACHE OPTIMIZATION
- Publication number 20250103511
- Publication date Mar 27, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE
- Publication number 20250103547
- Publication date Mar 27, 2025
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Coherency Control for Compressed Graphics Data
- Publication number 20250104181
- Publication date Mar 27, 2025
- Apple Inc.
- Karthik Ramani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FULLY PIPELINED READ-MODIFY-WRITE SUPPORT
- Publication number 20250094359
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20250094044
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...
- Publication number 20250094358
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE CACHE FOR COHERENT SYSTEM
- Publication number 20250060873
- Publication date Feb 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...
- Publication number 20250061060
- Publication date Feb 20, 2025
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPPORTUNISTIC CLEANING OF COHERENCE DIRECTORIES TO REDUCE CACHE-COH...
- Publication number 20250053513
- Publication date Feb 13, 2025
- Samsung Electronics Co., Ltd.
- Samantika Subramaniam Sury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGEMENT-SUBSYSTEM-BASED SOFTWARE RAID CONFIGURATION SYSTEM
- Publication number 20250044984
- Publication date Feb 6, 2025
- Dell Products L.P.
- Nikhith Ganigarakoppal Kantharaju
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...
- Publication number 20250036573
- Publication date Jan 30, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR STORING AND ACCESSING A DATA OPERAND IN A MEMORY UNIT
- Publication number 20250036571
- Publication date Jan 30, 2025
- BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACIÓN
- John D. DAVIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY
- Publication number 20250028675
- Publication date Jan 23, 2025
- Intel Corporation
- JOYDEEP RAY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES
- Publication number 20250028652
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE
- Publication number 20250028651
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE MEMORY MANAGEMENT
- Publication number 20250004981
- Publication date Jan 2, 2025
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TELEMETRY-CAPABLE MEMORY SUB-SYSTEM
- Publication number 20240427701
- Publication date Dec 26, 2024
- Micron Technology, Inc.
- David Andrew Roberts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...
- Publication number 20240419607
- Publication date Dec 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE STRUCTURE AND UTILIZATION
- Publication number 20240411717
- Publication date Dec 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable System on a Chip
- Publication number 20240411695
- Publication date Dec 12, 2024
- Apple Inc.
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING

Providing cache or TLB in specific location of a processing system

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Architectural support for persistent applications

Write merging on stores with different privilege levels

Photographing method and related apparatus

Methods, systems, and apparatuses for precise last branch record ev...

Hybrid victim cache and write miss buffer with fence operation

Methods and apparatus for multi-banked victim cache with dual datapath

Apparatus and method for managing data bias in a graphics processin...

Data initialization techniques

Memory system managing counters

Multicore, multibank, fully concurrent coherence controller

Hybrid memory module

Atomic compare and swap in a coherent cache system

Systems and methods for improving cache efficiency and utilization

Aggressive write flush scheme for a victim cache

Graphics processor data access and sharing

Methods and apparatus to reduce bank pressure using aggressive writ...

Fully pipelined read-modify-write support

Multi-tile memory management

Methods and apparatus for allocation in a victim cache system

Systems and methods for cache optimization

Virtual network pre-arbitration for deadlock avoidance and enhanced...

Multicore shared cache operation engine

Cache structure and utilization

Methods and apparatus for read-modify-write support in multi-banked...

Method and apparatus for shared virtual memory to manage data coher...

Victim cache with dynamic allocation of entries

Systolic disaggregation within a matrix accelerator architecture

Atomic operations and histogram operations in a cache pipeline

Configurable cache for coherent system

Machine learning sparse computation mechanism

Patents Applicationslast 30 patents

DATA INITIALIZATION TECHNIQUES

AGGRESSIVE WRITE FLUSH SCHEME FOR A VICTIM CACHE

ATOMIC COMPARE AND SWAP IN A COHERENT CACHE SYSTEM

MULTI-TILE MEMORY MANAGEMENT

METHODS AND APPARATUS FOR ALLOCATION IN A VICTIM CACHE SYSTEM

MACHINE LEARNING SPARSE COMPUTATION MECHANISM

PRE-FETCHING ADDRESS TRANSLATION FOR COMPUTATION OFFLOADING

ACCELERATION UNIT WITH MODULAR ARCHITECTURE

SYSTEMS AND METHODS FOR IMPROVING CACHE EFFICIENCY AND UTILIZATION

CACHE STRUCTURE AND UTILIZATION

SYSTEMS AND METHODS FOR CACHE OPTIMIZATION

SYSTOLIC DISAGGREGATION WITHIN A MATRIX ACCELERATOR ARCHITECTURE

Coherency Control for Compressed Graphics Data

FULLY PIPELINED READ-MODIFY-WRITE SUPPORT

MULTICORE SHARED CACHE OPERATION ENGINE

METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRIT...

CONFIGURABLE CACHE FOR COHERENT SYSTEM

METHOD AND APPARATUS FOR SHARED VIRTUAL MEMORY TO MANAGE DATA COHER...

OPPORTUNISTIC CLEANING OF COHERENCE DIRECTORIES TO REDUCE CACHE-COH...

MANAGEMENT-SUBSYSTEM-BASED SOFTWARE RAID CONFIGURATION SYSTEM

METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED...

METHOD FOR STORING AND ACCESSING A DATA OPERAND IN A MEMORY UNIT

GRAPHICS PROCESSOR OPERATION SCHEDULING FOR DETERMINISTIC LATENCY

VICTIM CACHE WITH DYNAMIC ALLOCATION OF ENTRIES

ATOMIC OPERATIONS AND HISTOGRAM OPERATIONS IN A CACHE PIPELINE

MULTI-TILE MEMORY MANAGEMENT

TELEMETRY-CAPABLE MEMORY SUB-SYSTEM

METHODS AND APPARATUS FOR EVICTION IN DUAL DATAPATH VICTIM CACHE SY...

CACHE STRUCTURE AND UTILIZATION

Scalable System on a Chip