Replacement control

Industry

CPC
G06F12/12

This industry / category may be too specific. Please go to a parent level for more data

Parent Industries

GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

Current Industry

G06F12/12Replacement control

Industries

Patents Grantslast 30 patents

Information Patent Grant
Heterogenous-latency memory optimization
- Patent number 12,147,351
- Issue date Nov 19, 2024
- RAMBUS INC.
- Evan Lawrence Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for read-modify-write support in multi-banked...
- Patent number 12,147,353
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor and operation thereof to revoke cache memory states utili...
- Patent number 12,147,349
- Issue date Nov 19, 2024
- Korea University Research and Business Foundation
- Taeweon Suh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelized scrubbing transactions
- Patent number 12,147,301
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- David Matthew Thompson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 12,141,601
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Victim cache with dynamic allocation of entries
- Patent number 12,141,078
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systolic disaggregation within a matrix accelerator architecture
- Patent number 12,141,094
- Issue date Nov 12, 2024
- Intel Corporation
- Prasoonkumar Surti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Firmware management of least recently used memory for cache hint op...
- Patent number 12,141,077
- Issue date Nov 12, 2024
- SK Hynix NAND Product Solutions Corp.
- Sriram Natarajan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Atomic operations and histogram operations in a cache pipeline
- Patent number 12,141,079
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for prefetching data into a cache
- Patent number 12,135,649
- Issue date Nov 5, 2024
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonvolatile physical memory with DRAM cache
- Patent number 12,135,645
- Issue date Nov 5, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Saving track metadata format information for tracks demoted from ca...
- Patent number 12,135,655
- Issue date Nov 5, 2024
- International Business Machines Corporation
- Kyler A. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for dynamic bypassing of last lev...
- Patent number 12,130,739
- Issue date Oct 29, 2024
- Intel Corporation
- Ayan Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and systems for storage, retrieval, and visualization of si...
- Patent number 12,130,753
- Issue date Oct 29, 2024
- Boston Scientific Neuromodulation Corporation
- Rosana Esteller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Data storage device and method for handling write commands in zoned...
- Patent number 12,124,377
- Issue date Oct 22, 2024
- SanDisk Technologies, Inc.
- Rotem Sela
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for cache optimization
- Patent number 12,124,383
- Issue date Oct 22, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic inclusive last level cache
- Patent number 12,111,762
- Issue date Oct 8, 2024
- Intel Corporation
- Ayan Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus for eviction in dual datapath victim cache sy...
- Patent number 12,105,640
- Issue date Oct 1, 2024
- Texas Instruments Incorporated
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instance based active data storage management
- Patent number 12,105,637
- Issue date Oct 1, 2024
- EMC IP Holding Company LLC
- Owen Martin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for cache insertion and cache eviction in a cache system th...
- Patent number 12,105,639
- Issue date Oct 1, 2024
- Dell Products L.P.
- Keyur B. Desai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Re-reference interval prediction (RRIP) with pseudo-LRU supplementa...
- Patent number 12,099,451
- Issue date Sep 24, 2024
- Advanced Micro Devices, Inc.
- Paul J. Moyer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-tile memory management
- Patent number 12,099,461
- Issue date Sep 24, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compression techniques
- Patent number 12,093,210
- Issue date Sep 17, 2024
- Intel Corporation
- Abhishek R. Appu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Stream oriented writing for improving sequential write and read per...
- Patent number 12,093,548
- Issue date Sep 17, 2024
- Western Digital Technologies, Inc.
- Sridhar Prudviraj Gunda
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor-based system for allocating cache lines to a higher-level...
- Patent number 12,093,184
- Issue date Sep 17, 2024
- QUALCOMM Incorporated
- Ramkumar Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Prefetch-adaptive intelligent cache replacement policy for high per...
- Patent number 12,093,188
- Issue date Sep 17, 2024
- Beijing University of Technology
- Juan Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-side page activity recorder
- Patent number 12,093,189
- Issue date Sep 17, 2024
- Amazon Technologies, Inc.
- Ali Ghassan Saidi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory management method to determine a frequently accessed page an...
- Patent number 12,086,069
- Issue date Sep 10, 2024
- Huawei Technologies Co., Ltd.
- Changlong Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Block device interface using non-volatile pinned memory
- Patent number 12,086,070
- Issue date Sep 10, 2024
- Daedalus Cloud LLC
- Stuart John Inglis
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY MODULE, MEMORY SYSTEM INCLUDING MEMORY MODULE, AND METHOD OF...
- Publication number 20240385968
- Publication date Nov 21, 2024
- SK HYNIX INC.
- Sung Woo HYUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address Range Based Memory Hints for Prefetcher, Cache and Memory C...
- Publication number 20240385966
- Publication date Nov 21, 2024
- Google LLC
- Xinliang David Li
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE, MEMORY SYSTEM INCLUDING MEMORY MODULE, AND METHOD OF...
- Publication number 20240385967
- Publication date Nov 21, 2024
- SK HYNIX INC.
- Sung Woo HYUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MODULE, MEMORY SYSTEM INCLUDING MEMORY MODULE, AND METHOD OF...
- Publication number 20240385969
- Publication date Nov 21, 2024
- SK HYNIX INC.
- Sung Woo HYUN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUERY PROCESSING FOR DISK BASED HYBRID TRANSACTIONAL ANALYTICAL PRO...
- Publication number 20240378205
- Publication date Nov 14, 2024
- SAP SE
- Ivan Schreter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY-BASED SYSTEM-LEVEL CACHE MANAGEMENT METHOD AND ASSOCIATED EL...
- Publication number 20240370379
- Publication date Nov 7, 2024
- MEDIATEK INC.
- Chun-Ming Su
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BLOCK DEVICE INTERFACE USING NON-VOLATILE PINNED MEMORY
- Publication number 20240370377
- Publication date Nov 7, 2024
- Daedalus Cloud LLC
- Stuart John INGLIS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...
- Publication number 20240370380
- Publication date Nov 7, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen Bhoria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable System on a Chip
- Publication number 20240370371
- Publication date Nov 7, 2024
- Apple Inc.
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...
- Publication number 20240362180
- Publication date Oct 31, 2024
- Intel Corporation
- Subramaniam Maiyuran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Quantum Cache
- Publication number 20240354614
- Publication date Oct 24, 2024
- Qubit Moving and Storage, LLC
- Gary Vacon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-RANDOM WAY SELECTION
- Publication number 20240345868
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-tile Memory Management for Detecting Cross Tile Access Provid...
- Publication number 20240345990
- Publication date Oct 17, 2024
- Intel Corporation
- Lakshminarayanan Striramassarma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STORAGE DEVICE CACHING UPDATE TARGET DATA UNIT WHILE ENTERING DOWN-...
- Publication number 20240345740
- Publication date Oct 17, 2024
- SK HYNIX INC.
- Byoung Min JIN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Detecting Modifications To Recently Stored Data
- Publication number 20240345955
- Publication date Oct 17, 2024
- PURE STORAGE, INC.
- Ronald Karr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-FIRST IN, FIRST OUT (FIFO) TAG LINE REPLACEMENT
- Publication number 20240338325
- Publication date Oct 10, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Sureshkumar Govindaraj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL MEMORY SYSTEM
- Publication number 20240338324
- Publication date Oct 10, 2024
- Samsung Electronics Co., LTD
- Heekwon PARK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE LINE SUBSCRIPTION
- Publication number 20240338323
- Publication date Oct 10, 2024
- ARM Limited
- Eric Ola Harald LILJEDAHL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY CONTROLLER CRYPTOGRAPHIC DATA QUANTIZATION USING A CACHE
- Publication number 20240333473
- Publication date Oct 3, 2024
- Xilinx, Inc.
- Abbas MORSHED
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS
- Publication number 20240320184
- Publication date Sep 26, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Deduplicating Data Based On Recently Reading The Data
- Publication number 20240320150
- Publication date Sep 26, 2024
- PURE STORAGE, INC.
- Ethan L. Miller
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HANDLING NON-CORRECTABLE ERRORS
- Publication number 20240311235
- Publication date Sep 19, 2024
- TEXAS INSTRUMENTS INCORPORATED
- David Matthew THOMPSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MANAGEMENT
- Publication number 20240302958
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Horia C. Simionescu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MANAGEMENT USING EVICTION PRIORITY BASED ON MEMORY REUSE
- Publication number 20240303203
- Publication date Sep 12, 2024
- NVIDIA Corporation
- Noam Dor Korem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE AND METHOD FOR SCHEDULING BLOCK REQUEST
- Publication number 20240303196
- Publication date Sep 12, 2024
- SAMCUNG ELECTRONICS CO, LTD
- Ho Bin LEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ADAPTIVE CACHE CONFIGURATION
- Publication number 20240303204
- Publication date Sep 12, 2024
- Samsung Electronics Co., Ltd.
- Sahand Salamat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VICTIM CACHE WITH WRITE MISS MERGING
- Publication number 20240296129
- Publication date Sep 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Naveen BHORIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAPPING DESCRIPTORS FOR READ OPERATIONS
- Publication number 20240296116
- Publication date Sep 5, 2024
- Micron Technology, Inc.
- Xing Hui Duan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA PROCESSING METHOD AND APPARATUS, AND CACHE, PROCESSOR AND ELEC...
- Publication number 20240289275
- Publication date Aug 29, 2024
- HYGON INFORMATION TECHNOLOGY CO., LTD.
- Haifeng ZHAI
- G06 - COMPUTING CALCULATING COUNTING

Replacement control

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Heterogenous-latency memory optimization

Methods and apparatus for read-modify-write support in multi-banked...

Processor and operation thereof to revoke cache memory states utili...

Parallelized scrubbing transactions

Global coherence operations

Victim cache with dynamic allocation of entries

Systolic disaggregation within a matrix accelerator architecture

Firmware management of least recently used memory for cache hint op...

Atomic operations and histogram operations in a cache pipeline

System for prefetching data into a cache

Nonvolatile physical memory with DRAM cache

Cache coherence shared state suppression

Saving track metadata format information for tracks demoted from ca...

Apparatuses, methods, and systems for dynamic bypassing of last lev...

Methods and systems for storage, retrieval, and visualization of si...

Data storage device and method for handling write commands in zoned...

Systems and methods for cache optimization

Dynamic inclusive last level cache

Methods and apparatus for eviction in dual datapath victim cache sy...

Instance based active data storage management

Methods for cache insertion and cache eviction in a cache system th...

Re-reference interval prediction (RRIP) with pseudo-LRU supplementa...

Multi-tile memory management

Compression techniques

Stream oriented writing for improving sequential write and read per...

Processor-based system for allocating cache lines to a higher-level...

Prefetch-adaptive intelligent cache replacement policy for high per...

Memory-side page activity recorder

Memory management method to determine a frequently accessed page an...

Block device interface using non-volatile pinned memory

Patents Applicationslast 30 patents

MEMORY MODULE, MEMORY SYSTEM INCLUDING MEMORY MODULE, AND METHOD OF...

Address Range Based Memory Hints for Prefetcher, Cache and Memory C...

MEMORY MODULE, MEMORY SYSTEM INCLUDING MEMORY MODULE, AND METHOD OF...

MEMORY MODULE, MEMORY SYSTEM INCLUDING MEMORY MODULE, AND METHOD OF...

QUERY PROCESSING FOR DISK BASED HYBRID TRANSACTIONAL ANALYTICAL PRO...

MEMORY-BASED SYSTEM-LEVEL CACHE MANAGEMENT METHOD AND ASSOCIATED EL...

BLOCK DEVICE INTERFACE USING NON-VOLATILE PINNED MEMORY

METHODS AND APPARATUS TO FACILITATE READ-MODIFY-WRITE SUPPORT IN A...

Scalable System on a Chip

GRAPHICS PROCESSORS AND GRAPHICS PROCESSING UNITS HAVING DOT PRODUC...

Quantum Cache

PSEUDO-RANDOM WAY SELECTION

Multi-tile Memory Management for Detecting Cross Tile Access Provid...

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

STORAGE DEVICE CACHING UPDATE TARGET DATA UNIT WHILE ENTERING DOWN-...

Detecting Modifications To Recently Stored Data

PSEUDO-FIRST IN, FIRST OUT (FIFO) TAG LINE REPLACEMENT

HIERARCHICAL MEMORY SYSTEM

CACHE LINE SUBSCRIPTION

MEMORY CONTROLLER CRYPTOGRAPHIC DATA QUANTIZATION USING A CACHE

MULTI-TILE ARCHITECTURE FOR GRAPHICS OPERATIONS

Deduplicating Data Based On Recently Reading The Data

HANDLING NON-CORRECTABLE ERRORS

MEMORY MANAGEMENT

CACHE MANAGEMENT USING EVICTION PRIORITY BASED ON MEMORY REUSE

MEMORY DEVICE AND METHOD FOR SCHEDULING BLOCK REQUEST

SYSTEMS AND METHODS FOR ADAPTIVE CACHE CONFIGURATION

VICTIM CACHE WITH WRITE MISS MERGING

MAPPING DESCRIPTORS FOR READ OPERATIONS

DATA PROCESSING METHOD AND APPARATUS, AND CACHE, PROCESSOR AND ELEC...