Serial access Scan testing

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GPHYSICS G11Information storage G11CSTATIC STORES G11C29/00Checking stores for correct operation; Subsequent repair Testing stores during standby or offline operation

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G11C29/32Serial access Scan testing

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Patents Grantslast 30 patents

Information Patent Grant
Tamper detection and prevention in computer systems having one-time...
- Patent number 12,299,183
- Issue date May 13, 2025
- Meta Platforms Technologies, LLC
- Sudhir Satpathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable scan chain architecture for multi-port memory
- Patent number 12,300,338
- Issue date May 13, 2025
- ARM Limited
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory repair system and method
- Patent number 12,300,337
- Issue date May 13, 2025
- QUALCOMM Incorporated
- Hong Dai
- G11 - INFORMATION STORAGE
Information Patent Grant
Block family error avoidance bin designs addressing error correctio...
- Patent number 12,277,984
- Issue date Apr 15, 2025
- Micron Technology, Inc.
- Guang Hu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with serial and parallel testing structure for sensin...
- Patent number 12,254,938
- Issue date Mar 18, 2025
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Grant
At-speed test of functional memory interface logic in devices
- Patent number 12,243,603
- Issue date Mar 4, 2025
- Texas Instruments Incorporated
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device with design for test functionality
- Patent number 12,217,811
- Issue date Feb 4, 2025
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit having test circuitry for memory sub-systems
- Patent number 12,181,522
- Issue date Dec 31, 2024
- NXP USA, INC.
- Alexander Hoefler
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan test in a single-wire bus circuit
- Patent number 12,092,689
- Issue date Sep 17, 2024
- Qorvo US, Inc.
- Alexander Wayne Hietala
- G11 - INFORMATION STORAGE
Information Patent Grant
Virtualized scan chain testing in a random access memory (RAM) array
- Patent number 12,087,383
- Issue date Sep 10, 2024
- Ampere Computing LLC
- David Hoff
- G11 - INFORMATION STORAGE
Information Patent Grant
JTAG registers with concurrent inputs
- Patent number 12,072,380
- Issue date Aug 27, 2024
- Antonino Mondello
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Threshold logic gates using flash transistors
- Patent number 12,057,831
- Issue date Aug 6, 2024
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods for scan chain stitching
- Patent number 12,007,440
- Issue date Jun 11, 2024
- Cadence Design Systems, Inc.
- Puneet Arora
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single “A” latch with an array of “B” latches
- Patent number 11,961,575
- Issue date Apr 16, 2024
- SambaNova Systems, Inc.
- Thomas A. Ziaja
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device, memory test circuit and memory test method thereof h...
- Patent number 11,935,611
- Issue date Mar 19, 2024
- Realtek Semiconductor Corporation
- Sheng-Lin Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory component for deployment in a dynamic stripe width memory sy...
- Patent number 11,862,236
- Issue date Jan 2, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with design for test functionality
- Patent number 11,848,066
- Issue date Dec 19, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
System including hierarchical memory modules having different types...
- Patent number 11,823,757
- Issue date Nov 21, 2023
- RAMBUS INC.
- Craig Hampel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test system for executing built-in self-test in deployment for auto...
- Patent number 11,810,632
- Issue date Nov 7, 2023
- NVIDIA Corporation
- Anitha Kalva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit for testing memory
- Patent number 11,776,648
- Issue date Oct 3, 2023
- Realtek Semiconductor Corporation
- Sheng-Lin Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Delay fault testing of pseudo static controls
- Patent number 11,768,726
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Aravinda Acharya
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module with reduced ECC overhead and memory system
- Patent number 11,756,646
- Issue date Sep 12, 2023
- Samsung Electronics Co., Ltd.
- Taekwoon Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device architecture coupled to a system-on-chip
- Patent number 11,749,369
- Issue date Sep 5, 2023
- Micron Technology, Inc.
- Antonino Mondello
- G11 - INFORMATION STORAGE
Information Patent Grant
Scan synchronous-write-through testing architectures for a memory d...
- Patent number 11,734,142
- Issue date Aug 22, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd
- Ming-Hung Chang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with analog measurement mode features
- Patent number 11,728,002
- Issue date Aug 15, 2023
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Grant
Changing scan frequency of a probabilistic data integrity scan base...
- Patent number 11,694,758
- Issue date Jul 4, 2023
- Micron Technology, Inc.
- Saeed Sharifi Tehrani
- G11 - INFORMATION STORAGE
Information Patent Grant
Digital circuit testing and analysis module, system and method thereof
- Patent number 11,688,482
- Issue date Jun 27, 2023
- Numascale AS
- Thibaut Palfer-Sollier
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device having micro-bumps and test method thereof
- Patent number 11,568,950
- Issue date Jan 31, 2023
- SK hynix Inc.
- Youngjun Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Probabilistic data integrity scan with dynamic scan frequency
- Patent number 11,545,229
- Issue date Jan 3, 2023
- Micron Technology, Inc.
- Saeed Sharifi Tehrani
- G11 - INFORMATION STORAGE
Information Patent Grant
Scalable infield scan coverage for multi-chip module for functional...
- Patent number 11,506,702
- Issue date Nov 22, 2022
- Intel Corporation
- Asad Azam
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND TEST...
- Publication number 20250166721
- Publication date May 22, 2025
- Samsung Electronics Co., Ltd.
- Yongha PARK
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE
- Publication number 20250014665
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Ivo Thomas Wambeke
- G11 - INFORMATION STORAGE
Information Patent Application
AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN
- Publication number 20240363187
- Publication date Oct 31, 2024
- STMicroelectronics International N.V.
- Praveen Kumar VERMA
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN TEST IN A SINGLE-WIRE BUS CIRCUIT
- Publication number 20240345162
- Publication date Oct 17, 2024
- Qorvo US, Inc.
- Alexander Wayne Hietala
- G11 - INFORMATION STORAGE
Information Patent Application
Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier O...
- Publication number 20240321376
- Publication date Sep 26, 2024
- QUALCOMM Incorporated
- Debarghya DUTTA
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND CO...
- Publication number 20240295604
- Publication date Sep 5, 2024
- STMicroelectronics International N.V.
- Gianluca TORTORA
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20240249791
- Publication date Jul 25, 2024
- SambaNova Systems, Inc.
- Thomas ZIAJA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BIT COUNTING CIRCUITS AND MEMORY DEVICES INCLUDING THE SAME
- Publication number 20240233852
- Publication date Jul 11, 2024
- Samsung Electronics Co., Ltd.
- Makoto Hirano
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY
- Publication number 20240170087
- Publication date May 23, 2024
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Application
AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES
- Publication number 20240120016
- Publication date Apr 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Devanathan Varadarajan
- G11 - INFORMATION STORAGE
Information Patent Application
AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...
- Publication number 20240112748
- Publication date Apr 4, 2024
- STMicroelectronics International N.V.
- Tanuj KUMAR
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY REPAIR SYSTEM AND METHOD
- Publication number 20240087662
- Publication date Mar 14, 2024
- QUALCOMM Incorporated
- HONG DAI
- G11 - INFORMATION STORAGE
Information Patent Application
BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTIO...
- Publication number 20240071547
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Guang Hu
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION
- Publication number 20240071549
- Publication date Feb 29, 2024
- Micron Technology, Inc.
- Sujeet Ayyapureddi
- G11 - INFORMATION STORAGE
Information Patent Application
VIRTUALIZED SCAN CHAIN TESTING IN A RANDOM ACCESS MEMORY (RAM) ARRAY
- Publication number 20240006012
- Publication date Jan 4, 2024
- Ampere Computing LLC
- David Hoff
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE
- Publication number 20230410930
- Publication date Dec 21, 2023
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Application
Configurable Scan Chain Architecture for Multi-Port Memory
- Publication number 20230402122
- Publication date Dec 14, 2023
- Andy Wangkun Chen
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SUB-SYSTEM THRESHOLD VOLTAGE MODIFICATION OPERATIONS
- Publication number 20230395176
- Publication date Dec 7, 2023
- Micron Technology, Inc.
- Jian Huang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM
- Publication number 20230386597
- Publication date Nov 30, 2023
- Samsung Electronics Co., LTD
- TAEKWOON KIM
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY D...
- Publication number 20230342272
- Publication date Oct 26, 2023
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ming-Hung CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY
- Publication number 20230317192
- Publication date Oct 5, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Application
CHANGING SCAN FREQUENCY OF A PROBABILISTIC DATA INTEGRITY SCAN BASE...
- Publication number 20230039624
- Publication date Feb 9, 2023
- Micron Technology, Inc.
- Saeed Sharifi Tehrani
- G11 - INFORMATION STORAGE
Information Patent Application
Memory device, memory test circuit and memory test method thereof h...
- Publication number 20230031828
- Publication date Feb 2, 2023
- REALTEK SEMICONDUCTOR CORPORATION
- SHENG-LIN LIN
- G11 - INFORMATION STORAGE
Information Patent Application
SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES
- Publication number 20230005560
- Publication date Jan 5, 2023
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE ARCHITECTURE COUPLED TO A SYSTEM-ON-CHIP
- Publication number 20230005561
- Publication date Jan 5, 2023
- Micron Technology, Inc.
- Antonino Mondello
- G11 - INFORMATION STORAGE
Information Patent Application
Test System For Executing Built-In Self-Test In Deployment For Auto...
- Publication number 20220399069
- Publication date Dec 15, 2022
- NVIDIA Corporation
- Anitha Kalva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE WITH ANALOG MEASUREMENT MODE FEATURES
- Publication number 20220293203
- Publication date Sep 15, 2022
- Micron Technology, Inc.
- Alberto Troia
- G11 - INFORMATION STORAGE
Information Patent Application
THRESHOLD LOGIC GATES USING FLASH TRANSISTORS
- Publication number 20220263508
- Publication date Aug 18, 2022
- Arizona Board of Regents on behalf of Arizona State University
- Sarma Vrudhula
- G11 - INFORMATION STORAGE
Information Patent Application
SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY D...
- Publication number 20220171688
- Publication date Jun 2, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Ming-Hung CHANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND CIRCUIT FOR ROW SCANNABLE LATCH ARRAY
- Publication number 20220139477
- Publication date May 5, 2022
- SambaNova Systems, Inc.
- Thomas A. ZIAJA
- G11 - INFORMATION STORAGE

Serial access Scan testing

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Tamper detection and prevention in computer systems having one-time...

Configurable scan chain architecture for multi-port memory

Memory repair system and method

Block family error avoidance bin designs addressing error correctio...

Memory device with serial and parallel testing structure for sensin...

At-speed test of functional memory interface logic in devices

Programmable logic device with design for test functionality

Integrated circuit having test circuitry for memory sub-systems

Scan test in a single-wire bus circuit

Virtualized scan chain testing in a random access memory (RAM) array

JTAG registers with concurrent inputs

Threshold logic gates using flash transistors

Systems and methods for scan chain stitching

Single “A” latch with an array of “B” latches

Memory device, memory test circuit and memory test method thereof h...

Memory component for deployment in a dynamic stripe width memory sy...

Programmable logic device with design for test functionality

System including hierarchical memory modules having different types...

Test system for executing built-in self-test in deployment for auto...

Circuit for testing memory

Delay fault testing of pseudo static controls

Memory module with reduced ECC overhead and memory system

Memory device architecture coupled to a system-on-chip

Scan synchronous-write-through testing architectures for a memory d...

Memory device with analog measurement mode features

Changing scan frequency of a probabilistic data integrity scan base...

Digital circuit testing and analysis module, system and method thereof

Semiconductor device having micro-bumps and test method thereof

Probabilistic data integrity scan with dynamic scan frequency

Scalable infield scan coverage for multi-chip module for functional...

Patents Applicationslast 30 patents

NONVOLATILE MEMORY DEVICE, STORAGE DEVICE HAVING THE SAME, AND TEST...

TRIPLE VIA CHAIN FOR ADVANCED INTERCONNECT IN A MEMORY DEVICE

AREA SAVING HIGH COVERAGE FAST DIAGNOSIS MEMORY SCAN DESIGN

SCAN TEST IN A SINGLE-WIRE BUS CIRCUIT

Sense Amplifier Scan Capture Circuit with Reduced Sense Amplifier O...

INTEGRATED CIRCUIT COMPRISING A TEST CIRCUIT, RELATED METHOD AND CO...

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

BIT COUNTING CIRCUITS AND MEMORY DEVICES INCLUDING THE SAME

PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY

AT-SPEED TEST OF FUNCTIONAL MEMORY INTERFACE LOGIC IN DEVICES

AT-SPEED TRANSITION FAULT TESTING FOR A MULTI-PORT AND MULTI-CLOCK...

MEMORY REPAIR SYSTEM AND METHOD

BLOCK FAMILY ERROR AVOIDANCE BIN DESIGNS ADDRESSING ERROR CORRECTIO...

APPARATUSES, SYSTEMS, AND METHODS FOR MODULE LEVEL ERROR CORRECTION

VIRTUALIZED SCAN CHAIN TESTING IN A RANDOM ACCESS MEMORY (RAM) ARRAY

MEMORY DEVICE WITH IMPROVED SENSING STRUCTURE

Configurable Scan Chain Architecture for Multi-Port Memory

MEMORY SUB-SYSTEM THRESHOLD VOLTAGE MODIFICATION OPERATIONS

MEMORY MODULE WITH REDUCED ECC OVERHEAD AND MEMORY SYSTEM

SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY D...

PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY

CHANGING SCAN FREQUENCY OF A PROBABILISTIC DATA INTEGRITY SCAN BASE...

Memory device, memory test circuit and memory test method thereof h...

SINGLE "A" LATCH WITH AN ARRAY OF "B" LATCHES

MEMORY DEVICE ARCHITECTURE COUPLED TO A SYSTEM-ON-CHIP

Test System For Executing Built-In Self-Test In Deployment For Auto...

MEMORY DEVICE WITH ANALOG MEASUREMENT MODE FEATURES

THRESHOLD LOGIC GATES USING FLASH TRANSISTORS

SCAN SYNCHRONOUS-WRITE-THROUGH TESTING ARCHITECTURES FOR A MEMORY D...

METHOD AND CIRCUIT FOR ROW SCANNABLE LATCH ARRAY