Silicon on III-V

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CPC
Y10S148/149

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YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10USPC classification Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS Y10S148/00Metal treatment

Current Industry

Y10S148/149Silicon on III-V

Industries

Patents Grantslast 30 patents

Information Patent Grant
Method of making a lattice mismatched heterostructure optical waveg...
- Patent number 5,354,709
- Issue date Oct 11, 1994
- The United States of America as represented by the Secretary of the Air Force
- Joseph P. Lorenzo
- G02 - OPTICS
Information Patent Grant
Method for manufacturing a semiconductor substrate having a compoun...
- Patent number 5,244,830
- Issue date Sep 14, 1993
- Korea Electronics and Telecommunications Research Institute
- Sang-Won Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Lattice mismatched hetrostructure optical waveguide
- Patent number 5,163,118
- Issue date Nov 10, 1992
- The United States of America as represented by the Secretary of the Air Force
- Joseph P. Lorenzo
- G02 - OPTICS
Information Patent Grant
Method for forming a transistor having cubic boron nitride layer
- Patent number 5,081,053
- Issue date Jan 14, 1992
- General Motors Corporation
- Joseph P. Heremans
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of making unpinned oxide-compound semiconductor structures
- Patent number 4,987,095
- Issue date Jan 22, 1991
- International Business Machines Corp.
- John Batey
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming intermediate buffer films with low plastic deform...
- Patent number 4,935,385
- Issue date Jun 19, 1990
- Xerox Corporation
- David K. Biegelsen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
III-V Semiconductor growth initiation on silicon using TMG and TEG
- Patent number 4,910,167
- Issue date Mar 20, 1990
- Kopin Corporation
- Jhang W. Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for growing gallium arsenide on silicon substrate
- Patent number 4,897,367
- Issue date Jan 30, 1990
- Fujitsu Limited
- Kazuto Ogasawara
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterning method in the manufacture of miniaturized devices
- Patent number 4,897,361
- Issue date Jan 30, 1990
- American Telephone and Telegraph Company, AT&T Bell Laboratories
- Lloyd R. Harriott
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Ion implantation and annealing of compound semiconductor layers
- Patent number 4,863,877
- Issue date Sep 5, 1989
- Kopin Corporation
- John C. C. Fan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for heteroepitaxial growth using tensioning layer on rear su...
- Patent number 4,830,984
- Issue date May 16, 1989
- Texas Instruments Incorporated
- Andrew J. Purdes
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gallium arsenide superlattice crystal grown on silicon substrate an...
- Patent number 4,789,421
- Issue date Dec 6, 1988
- Daidotokushuko Kabushikikaisha
- Masayoshi Umeno
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Monolithic integration of silicon and gallium arsenide devices
- Patent number 4,774,205
- Issue date Sep 27, 1988
- Massachusetts Institute of Technology
- Hong K. Choi
- H01 - BASIC ELECTRIC ELEMENTS

Silicon on III-V

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method of making a lattice mismatched heterostructure optical waveg...

Method for manufacturing a semiconductor substrate having a compoun...

Lattice mismatched hetrostructure optical waveguide

Method for forming a transistor having cubic boron nitride layer

Method of making unpinned oxide-compound semiconductor structures

Method of forming intermediate buffer films with low plastic deform...

III-V Semiconductor growth initiation on silicon using TMG and TEG

Process for growing gallium arsenide on silicon substrate

Patterning method in the manufacture of miniaturized devices

Ion implantation and annealing of compound semiconductor layers

Method for heteroepitaxial growth using tensioning layer on rear su...

Gallium arsenide superlattice crystal grown on silicon substrate an...

Monolithic integration of silicon and gallium arsenide devices