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G06F2207/4802

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F2207/00Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled

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G06F2207/4802Special implementations

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Patents Grantslast 30 patents

Information Patent Grant
Method of operation for a configurable number theoretic transform (...
- Patent number 11,870,881
- Issue date Jan 9, 2024
- The Governing Council of the University of Toronto
- Alhassan Khedr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of operation for a configurable number theoretic transform (...
- Patent number 11,456,856
- Issue date Sep 27, 2022
- The Governing Council of the University of Toronto
- Alhassan Khedr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Analog multiplier-accumulators
- Patent number 11,315,009
- Issue date Apr 26, 2022
- Hewlett Packard Enterprise Development LP
- Brent Buchanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
2D and 3D sum-of-products array for neuromorphic computing system
- Patent number 10,957,392
- Issue date Mar 23, 2021
- Macronix International Co., Ltd.
- Feng-Min Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware node having a mixed-signal matrix vector unit
- Patent number 10,860,924
- Issue date Dec 8, 2020
- Microsoft Technology Licensing, LLC
- Douglas C. Burger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Information processing apparatus that controls a semiconductor devi...
- Patent number 10,839,044
- Issue date Nov 17, 2020
- Hitachi, Ltd.
- Takuya Okuyama
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of operation for a configurable number theoretic transform (...
- Patent number 10,715,309
- Issue date Jul 14, 2020
- The Governing Council of the University of Toronto
- Alhassan Khedr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplication operations in memory
- Patent number 10,713,011
- Issue date Jul 14, 2020
- Micron Technology, Inc.
- Sanjay Tiwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Real time cognitive monitoring of correlations between variables
- Patent number 10,670,642
- Issue date Jun 2, 2020
- International Business Machines Corporation
- Karl R. Erickson
- G01 - MEASURING TESTING
Information Patent Grant
Real time cognitive monitoring of correlations between variables
- Patent number 10,663,502
- Issue date May 26, 2020
- International Business Machines Corporation
- Karl R. Erickson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable number theoretic transform (NTT) butterfly circuit for...
- Patent number 10,644,877
- Issue date May 5, 2020
- The Governing Council of the University of Toronto
- Alhassan Khedr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Voltage sensing type of matrix multiplication method for neuromorph...
- Patent number 10,635,398
- Issue date Apr 28, 2020
- Macronix International Co., Ltd.
- Yu-Yu Lin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memristor-based dividers using memristors-as-drivers (MAD) gates
- Patent number 10,608,639
- Issue date Mar 31, 2020
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memristor-based multipliers using memristors-as-drivers (MAD) gates
- Patent number 10,558,431
- Issue date Feb 11, 2020
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memristor-based dividers using memristors-as-drivers (MAD) gates
- Patent number 10,447,271
- Issue date Oct 15, 2019
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplication operations in memory
- Patent number 10,409,554
- Issue date Sep 10, 2019
- Micron Technology, Inc.
- Sanjay Tiwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resistive memory arrays for performing multiply-accumulate operations
- Patent number 10,339,202
- Issue date Jul 2, 2019
- Hewlett Packard Enterprise Development LP
- Brent Buchanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Homomorphic processing unit (HPU) for accelerating secure computati...
- Patent number 10,298,385
- Issue date May 21, 2019
- The Governing Council of the University of Toronto
- Alhassan Khedr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiply-accumulate circuits
- Patent number 10,180,820
- Issue date Jan 15, 2019
- HEWLETT PACKARD ENTERPRlSE DEVELOPMENT LP
- Brent Buchanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Resistive memory arrays for performing multiply-accumulate operations
- Patent number 10,169,297
- Issue date Jan 1, 2019
- Hewlett Packard Enterprise Development LP
- Brent Buchanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiplication operations in memory
- Patent number 9,898,252
- Issue date Feb 20, 2018
- Micron Technology, Inc.
- Sanjay Tiwari
- G11 - INFORMATION STORAGE
Information Patent Grant
Double rounded combined floating-point multiply and add
- Patent number 9,778,909
- Issue date Oct 3, 2017
- Intel Corporation
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Double rounded combined floating-point multiply and add
- Patent number 9,477,441
- Issue date Oct 25, 2016
- Intel Corporation
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder including transistor having oxide semiconductor layer
- Patent number 8,638,123
- Issue date Jan 28, 2014
- Semiconductor Energy Laboratory Co., Ltd.
- Tatsuya Ohnuki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Magnetic device for performing a logic function
- Patent number 8,344,758
- Issue date Jan 1, 2013
- Commissariat a l'Energie Atomique et Aux Energies Alternatives
- Virgile Javerliac
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Variable fixed multipliers using memory blocks
- Patent number 6,943,579
- Issue date Sep 13, 2005
- Altera Corporation
- Asher Hazanchuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programmable logic device with soft multiplier
- Patent number 6,888,372
- Issue date May 3, 2005
- Altera Corporation
- Asher Hazanchuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low power adder for accumulation
- Patent number 5,691,931
- Issue date Nov 25, 1997
- Hitachi America, Ltd.
- Kenichi Nitta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural comprising means for calculating a norm or a distance
- Patent number 5,548,686
- Issue date Aug 20, 1996
- U.S. Philips Corporation
- Yannick DeVille
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Neural processor which can calculate a norm or a distance
- Patent number 5,537,513
- Issue date Jul 16, 1996
- U.S. Philips Corporation
- Yannick DeVille
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
A Method of Operation for a Configurable Number Theoretic Transform...
- Publication number 20240421970
- Publication date Dec 19, 2024
- The Governing Council of the University of Toronto
- Alhassan Khedr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Operation for a Configurable Number Theoretic Transform (...
- Publication number 20230086526
- Publication date Mar 23, 2023
- The Governing Council of the University of Toronto
- Alhassan Khedr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method of Operation for a Configurable Number Theoretic Transform (...
- Publication number 20210028921
- Publication date Jan 28, 2021
- The Governing Council of the University of Toronto
- Alhassan Khedr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMRISTOR-BASED DIVIDERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES
- Publication number 20200014388
- Publication date Jan 9, 2020
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLICATION OPERATIONS IN MEMORY
- Publication number 20200004502
- Publication date Jan 2, 2020
- Micron Technology, Inc.
- Sanjay Tiwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMRISTOR-BASED MULTIPLIERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES
- Publication number 20190250885
- Publication date Aug 15, 2019
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMRISTOR-BASED DIVIDERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES
- Publication number 20190245542
- Publication date Aug 8, 2019
- Board of Regents, The University of Texas System
- Earl Swartzlander
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Configurable Number Theoretic Transform (NTT) Butterfly Circuit For...
- Publication number 20190222412
- Publication date Jul 18, 2019
- The Governing Council of the University of Toronto
- Alhassan Khedr
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RESISTIVE MEMORY ARRAYS FOR PERFORMING MULTIPLY-ACCUMULATE OPERATIONS
- Publication number 20190108193
- Publication date Apr 11, 2019
- HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
- Brent Buchanan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLICATION OPERATIONS IN MEMORY
- Publication number 20180173499
- Publication date Jun 21, 2018
- Micron Technology, Inc.
- Sanjay Tiwari
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD
- Publication number 20170039033
- Publication date Feb 9, 2017
- Intel Corporation
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD
- Publication number 20160077802
- Publication date Mar 17, 2016
- Intel Corporation
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDER
- Publication number 20140191791
- Publication date Jul 10, 2014
- Semiconductor Energy Laboratory Co., Ltd.
- Tatsuya Ohnuki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD
- Publication number 20140006467
- Publication date Jan 2, 2014
- Sridhar Samudrala
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDER
- Publication number 20120297221
- Publication date Nov 22, 2012
- Semiconductor Energy Laboratory Co., Ltd.
- Tatsuya Ohnuki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAGNETIC DEVICE FOR PERFORMING A "LOGIC FUNCTION"
- Publication number 20110221470
- Publication date Sep 15, 2011
- Commissariat a l'energie atomique et aux energies alternatives
- Virgile Javerliac
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MAGNETIC DEVICE FOR PERFORMING A LOGIC FUNCTION
- Publication number 20110115522
- Publication date May 19, 2011
- Commissariat A L'Energie Atomique et Aux Energies Alternatives
- Virgile Javerliac
- G06 - COMPUTING CALCULATING COUNTING

Special implementations

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method of operation for a configurable number theoretic transform (...

Method of operation for a configurable number theoretic transform (...

Analog multiplier-accumulators

2D and 3D sum-of-products array for neuromorphic computing system

Hardware node having a mixed-signal matrix vector unit

Information processing apparatus that controls a semiconductor devi...

Method of operation for a configurable number theoretic transform (...

Multiplication operations in memory

Real time cognitive monitoring of correlations between variables

Real time cognitive monitoring of correlations between variables

Configurable number theoretic transform (NTT) butterfly circuit for...

Voltage sensing type of matrix multiplication method for neuromorph...

Memristor-based dividers using memristors-as-drivers (MAD) gates

Memristor-based multipliers using memristors-as-drivers (MAD) gates

Memristor-based dividers using memristors-as-drivers (MAD) gates

Multiplication operations in memory

Resistive memory arrays for performing multiply-accumulate operations

Homomorphic processing unit (HPU) for accelerating secure computati...

Multiply-accumulate circuits

Resistive memory arrays for performing multiply-accumulate operations

Multiplication operations in memory

Double rounded combined floating-point multiply and add

Double rounded combined floating-point multiply and add

Adder including transistor having oxide semiconductor layer

Magnetic device for performing a logic function

Variable fixed multipliers using memory blocks

Programmable logic device with soft multiplier

Low power adder for accumulation

Neural comprising means for calculating a norm or a distance

Neural processor which can calculate a norm or a distance

Patents Applicationslast 30 patents

A Method of Operation for a Configurable Number Theoretic Transform...

Method of Operation for a Configurable Number Theoretic Transform (...

Method of Operation for a Configurable Number Theoretic Transform (...

MEMRISTOR-BASED DIVIDERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES

MULTIPLICATION OPERATIONS IN MEMORY

MEMRISTOR-BASED MULTIPLIERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES

MEMRISTOR-BASED DIVIDERS USING MEMRISTORS-AS-DRIVERS (MAD) GATES

Configurable Number Theoretic Transform (NTT) Butterfly Circuit For...

RESISTIVE MEMORY ARRAYS FOR PERFORMING MULTIPLY-ACCUMULATE OPERATIONS

MULTIPLICATION OPERATIONS IN MEMORY

DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD

DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD

ADDER

DOUBLE ROUNDED COMBINED FLOATING-POINT MULTIPLY AND ADD

ADDER

MAGNETIC DEVICE FOR PERFORMING A "LOGIC FUNCTION"

MAGNETIC DEVICE FOR PERFORMING A LOGIC FUNCTION