Patent Grant
9898252
This application is a Non-Provisional of U.S. Provisional Application No. 62/045,259, filed Sep. 3, 2014, the contents of which are incorporated herein by reference.
The present disclosure relates generally to semiconductor memory apparatuses and methods, and more particularly, to apparatuses and methods related to performing multiplication operations in memory.
Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic systems. There are many different types of memory including volatile and non-volatile memory. Volatile memory can require power to maintain its data (e.g., host data, error data, etc.) and includes random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), and thyristor random access memory (TRAM), among others. Non-volatile memory can provide persistent data by retaining stored data when not powered and can include NAND flash memory, NOR flash memory, and resistance variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), and magnetoresistive random access memory (MRAM), such as spin torque transfer random access memory (STT RAM), among others.
Electronic systems often include a number of processing resources (e.g., one or more processors), which may retrieve and execute instructions and store the results of the executed instructions to a suitable location. A processor can comprise a number of functional units (e.g., herein referred to as functional unit circuitry (FUC)) such as arithmetic logic unit (ALU) circuitry, floating point unit (FPU) circuitry, and/or a combinatorial logic block, for example, which can execute instructions to perform logical operations such as AND, OR, NOT, NAND, NOR, and XOR logical operations on data (e.g., one or more operands).
A number of components in an electronic system may be involved in providing instructions to the functional unit circuitry for execution. The instructions may be generated, for instance, by a processing resource such as a controller and/or host processor. Data (e.g., the operands on which the instructions will be executed to perform the logical operations) may be stored in a memory array that is accessible by the FUC. The instructions and/or data may be retrieved from the memory array and sequenced and/or buffered before the FUC begins to execute instructions on the data. Furthermore, as different types of operations may be executed in one or multiple clock cycles through the FUC, intermediate results of the operations and/or data may also be sequenced and/or buffered.
In many instances, the processing resources (e.g., processor and/or associated FUC) may be external to the memory array, and data can be accessed (e.g., via a bus between the processing resources and the memory array to execute instructions). Data can be moved from the memory array to registers external to the memory array via a bus.
The present disclosure includes apparatuses and methods related to multiplication operations for memory. A multiplication operation can be performed on a first element and a second element. An element can be stored in a group of memory cells coupled to an access line and to a number of sense lines. For example, a first group of memory cells coupled to a first access line can store a first element. A second group of memory cells coupled to a second access line can store a second element. The multiplication operation can multiply the first element by the second element by performing a number of operations without transferring data via an input/output (I/O) line to determine a multiplication result.
As used herein, a first element and a second element can be numerical values that are multiplied by each other. That is, a first value (e.g., a first element, which can be referred to as an operand) can be multiplied by a second value (e.g., a second element) via a controller (e.g., a controller configured to control sensing circuitry). A multiplication operation can be used to determine a multiplication result from multiplying the first value by the second value.
In a number of examples, an element can represent an object and/or other construct, which may be represented by a bit-vector. As an example, a multiplication operation can be performed to multiply objects by multiplying the bit-vectors that represent the respective objects.
A number of embodiments of the present disclosure can provide a reduction of the number of computations and/or time involved in performing a number of multiplication operations (e.g., multiplication functions) relative to previous approaches. For instance, the number of computations and/or the time can be reduced due to an ability to perform various portions of the number of multiplication operations in parallel (e.g., simultaneously). Performing a number of multiplication operations as described herein can also reduce power consumption as compared to previous approaches. In accordance with a number of embodiments, a multiplication operation can be performed on elements (e.g., data in the form of bit-vectors stored in an array) without transferring data out of the memory array and/or sensing circuitry via a bus (e.g., data bus, address bus, control bus, etc.). A multiplication operation can involve performing a number of logical operations (e.g., AND operations, OR operations, SHIFT operations, INVERT operations, and Block_OR operations, etc.). However, embodiments are not limited to these examples.
In various previous approaches, elements (e.g., a first value and a second value) to be multiplied may be transferred from the array and sensing circuitry to a number of registers via a bus comprising input/output (I/O) lines. The number of registers can be used by a processing resource such as a processor, microprocessor, and/or compute engine, which may comprise ALU circuitry and/or other functional unit circuitry configured to perform the appropriate logical operations. However, often only a single multiplication function can be performed by the ALU circuitry, and transferring data to/from memory from/to registers via a bus can involve significant power consumption and time requirements. Even if the processing resource is located on a same chip as the memory array, significant power can be consumed in moving data out of the array to the compute circuitry (e.g., ALU), which can involve performing a sense line address access (e.g., firing of a column decode signal) in order to transfer data from sense lines onto I/O lines, moving the data to the array periphery, and providing the data to a register in association with performing a multiplication operation, for instance.
In the following detailed description of the present disclosure, reference is made to the accompanying drawings that form a part hereof, and in which is shown by way of illustration how one or more embodiments of the disclosure may be practiced. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice the embodiments of this disclosure, and it is to be understood that other embodiments may be utilized and that process, electrical, and/or structural changes may be made without departing from the scope of the present disclosure. As used herein, the designators “S,” “T,” “U,” “V,” “W,” etc., particularly with respect to reference numerals in the drawings, indicates that a number of the particular feature so designated can be included. As used herein, “a number of” a particular thing can refer to one or more of such things (e.g., a number of memory arrays can refer to one or more memory arrays).
The figures herein follow a numbering convention in which the first digit or digits correspond to the drawing figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures may be identified by the use of similar digits. For example, 204 may reference element “04” in
System 100 includes a host 110 coupled to memory device 160, which includes a memory array 130. Host 110 can be a host system such as a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, or a memory card reader, among various other types of hosts. Host 110 can include a system motherboard and/or backplane and can include a number of processing resources (e.g., one or more processors, microprocessors, or some other type of controlling circuitry). The system 100 can include separate integrated circuits or both the host 110 and the memory device 160 can be on the same integrated circuit. The system 100 can be, for instance, a server system and/or a high performance computing (HPC) system and/or a portion thereof. Although the example shown in
For clarity, the system 100 has been simplified to focus on features with particular relevance to the present disclosure. The memory array 130 can be a DRAM array, SRAM array, STT RAM array, PCRAM array, TRAM array, RRAM array, NAND flash array, and/or NOR flash array, for instance. The array 130 can comprise memory cells arranged in rows coupled by access lines (which may be referred to herein as word lines or select lines) and columns coupled by sense lines (which may be referred to herein as digit lines or data lines). Although a single array 130 is shown in
The memory device 160 includes address circuitry 142 to latch address signals provided over an I/O bus 156 (e.g., a data bus) through I/O circuitry 144. Address signals are received and decoded by a row decoder 146 and a column decoder 152 to access the memory array 130. Data can be read from memory array 130 by sensing voltage and/or current changes on the sense lines using sensing circuitry 150. The sensing circuitry 150 can read and latch a page (e.g., row) of data from the memory array 130. The I/O circuitry 144 can be used for bi-directional data communication with host 110 over the I/O bus 156. The write circuitry 148 is used to write data to the memory array 130.
Controller 140 decodes signals provided by control bus 154 from the host 110. These signals can include chip enable signals, write enable signals, and address latch signals that are used to control operations performed on the memory array 130, including data read, data write, and data erase operations. In various embodiments, the controller 140 is responsible for executing instructions from the host 110. The controller 140 can be a state machine, a sequencer, or some other type of controller.
An example of the sensing circuitry 150 is described further below in association with
In various previous approaches, data associated with a multiplication operation, for instance, would be read from memory via sensing circuitry and provided to an external ALU. The external ALU circuitry would perform the multiplication functions using the elements (which may be referred to as operands or inputs) and the result could be transferred back to the array via the local I/O lines. In contrast, in a number of embodiments of the present disclosure, sensing circuitry (e.g., 150) is configured to perform a multiplication operation on data stored in memory cells in memory array 130 and store the result back to the array 130 without enabling a local I/O line coupled to the sensing circuitry.
As such, in a number of embodiments, registers and/or an ALU external to array 130 and sensing circuitry 150 may not be needed to perform the multiplication function as the sensing circuitry 150 can be operated to perform the appropriate computations involved in performing the multiplication function using the address space of memory array 130. Additionally, the multiplication function can be performed without the use of an external processing resource.
Memory cells can be coupled to different data lines and/or word lines. For example, a first source/drain region of a transistor 202-1 can be coupled to data line 205-1 (D), a second source/drain region of transistor 202-1 can be coupled to capacitor 203-1, and a gate of a transistor 202-1 can be coupled to word line 204-Y. A first source/drain region of a transistor 202-2 can be coupled to data line 205-2 (D_), a second source/drain region of transistor 202-2 can be coupled to capacitor 203-2, and a gate of a transistor 202-2 can be coupled to word line 204-X. The cell plate, as shown in
The memory array 230 is coupled to sensing circuitry 250 in accordance with a number of embodiments of the present disclosure. In this example, the sensing circuitry 250 comprises a sense amplifier 206 and a compute component 231 corresponding to respective columns of memory cells (e.g., coupled to respective pairs of complementary data lines). The sense amplifier 206 can comprise a cross coupled latch, which can be referred to herein as a primary latch. The sense amplifier 206 can be configured, for example, as described with respect to
In the example illustrated in
In this example, data line D 205-1 can be coupled to a first source/drain region of transistors 216-1 and 239-1, as well as to a first source/drain region of load/pass transistor 218-1. Data line D_ 205-2 can be coupled to a first source/drain region of transistors 216-2 and 239-2, as well as to a first source/drain region of load/pass transistor 218-2.
The gates of load/pass transistor 218-1 and 218-2 can be commonly coupled to a LOAD control signal, or respectively coupled to a PASSD/PASSDB control signal, as discussed further below. A second source/drain region of load/pass transistor 218-1 can be directly coupled to the gates of transistors 216-1 and 239-2. A second source/drain region of load/pass transistor 218-2 can be directly coupled to the gates of transistors 216-2 and 239-1.
A second source/drain region of transistor 216-1 can be directly coupled to a first source/drain region of pull-down transistor 214-1. A second source/drain region of transistor 239-1 can be directly coupled to a first source/drain region of pull-down transistor 207-1. A second source/drain region of transistor 216-2 can be directly coupled to a first source/drain region of pull-down transistor 214-2. A second source/drain region of transistor 239-2 can be directly coupled to a first source/drain region of pull-down transistor 207-2. A second source/drain region of each of pull-down transistors 207-1, 207-2, 214-1, and 214-2 can be commonly coupled together to a reference voltage 291-1 (e.g., ground (GND)). A gate of pull-down transistor 207-1 can be coupled to an AND control signal line, a gate of pull-down transistor 214-1 can be coupled to an ANDinv control signal line 213-1, a gate of pull-down transistor 214-2 can be coupled to an ORinv control signal line 213-2, and a gate of pull-down transistor 207-2 can be coupled to an OR control signal line.
The gate of transistor 239-1 can be referred to as node S1, and the gate of transistor 239-2 can be referred to as node S2. The circuit shown in
The configuration of compute component 231 shown in
Inverting transistors can pull-down a respective data line in performing certain logical operations. For example, transistor 216-1 (having a gate coupled to S2 of the dynamic latch) in series with transistor 214-1 (having a gate coupled to an ANDinv control signal line 213-1) can be operated to pull-down data line 205-1 (D), and transistor 216-2 (having a gate coupled to S1 of the dynamic latch) in series with transistor 214-2 (having a gate coupled to an ORinv control signal line 213-2) can be operated to pull-down data line 205-2 (D_).
The latch 264 can be controllably enabled by coupling to an active negative control signal line 212-1 (ACCUMB) and an active positive control signal line 212-2 (ACCUM) rather than be configured to be continuously enabled by coupling to ground and VDD. In various embodiments, load/pass transistors 208-1 and 208-2 can each having a gate coupled to one of a LOAD control signal or a PASSD/PASSDB control signal.
According to some embodiments, the gates of load/pass transistors 218-1 and 218-2 can be commonly coupled to a LOAD control signal. In the configuration where the gates of load/pass transistors 218-1 and 218-2 are commonly coupled to the LOAD control signal, transistors 218-1 and 218-2 can be load transistors. Activating the LOAD control signal causes the load transistors to conduct, and thereby load complementary data onto nodes S1 and S2. The LOAD control signal can be elevated to a voltage greater than VDD to pass a full VDD level to S1/S2. However, the LOAD control signal need not be elevated to a voltage greater than VDD is optional, and functionality of the circuit shown in
According to some embodiments, the gate of load/pass transistor 218-1 can be coupled to a PASSD control signal, and the gate of load/pass transistor 218-2 can be coupled to a PASSDb control signal. In the configuration where the gates of transistors 218-1 and 218-2 are respectively coupled to one of the PASSD and PASSDb control signals, transistors 218-1 and 218-2 can be pass transistors. Pass transistors can be operated differently (e.g., at different times and/or under different voltage/current conditions) than load transistors. As such, the configuration of pass transistors can be different than the configuration of load transistors.
Load transistors are constructed to handle loading associated with coupling data lines to the local dynamic nodes S1 and S2, for example. Pass transistors are constructed to handle heavier loading associated with coupling data lines to an adjacent accumulator (e.g., through the shift circuitry 223, as shown in
In a number of embodiments, the compute component 231, including the latch 264, can comprise a number of transistors formed on pitch with the transistors of the corresponding memory cells of an array (e.g., array 230 shown in
The voltages or currents on the respective data lines D and D— can be provided to the respective latch inputs 217-1 and 217-2 of the cross coupled latch 264 (e.g., the input of the secondary latch). In this example, the latch input 217-1 is coupled to a first source/drain region of transistors 208-1 and 209-1 as well as to the gates of transistors 208-2 and 209-2. Similarly, the latch input 217-2 can be coupled to a first source/drain region of transistors 208-2 and 209-2 as well as to the gates of transistors 208-1 and 209-1.
In this example, a second source/drain region of transistor 209-1 and 209-2 is commonly coupled to a negative control signal line 291-1 (e.g., ground (GND) or ACCUMB control signal similar to control signal RnIF shown in
The enabled cross coupled latch 264 operates to amplify a differential voltage between latch input 217-1 (e.g., first common node) and latch input 217-2 (e.g., second common node) such that latch input 217-1 is driven to either the activated positive control signal voltage (e.g., VDD) or the activated negative control signal voltage (e.g., ground), and latch input 217-2 is driven to the other of the activated positive control signal voltage (e.g., VDD) or the activated negative control signal voltage (e.g., ground).
As shown in
In the example illustrated in
Although the shift circuitry 223 shown in
Embodiments of the present disclosure are not limited to the configuration of shift circuitry 223 shown in
Although not shown in
In a number of embodiments, a sense amplifier (e.g., 206) can comprise a number of transistors formed on pitch with the transistors of the corresponding compute component 231 and/or the memory cells of an array (e.g., 230 shown in
The voltages or currents on the respective data lines D and D— can be provided to the respective latch inputs 233-1 and 233-2 of the cross coupled latch 215 (e.g., the input of the secondary latch). In this example, the latch input 233-1 is coupled to a first source/drain region of transistors 227-1 and 229-1 as well as to the gates of transistors 227-2 and 229-2. Similarly, the latch input 233-2 can be coupled to a first source/drain region of transistors 227-2 and 229-2 as well as to the gates of transistors 227-1 and 229-1. The compute component 231, which may be referred to herein as an accumulator, can be coupled to latch inputs 233-1 and 233-2 of the cross coupled latch 215 as shown; however, embodiments are not limited to the example shown in
In this example, a second source/drain region of transistor 227-1 and 227-2 is commonly coupled to an active negative control signal 228 (RnIF). A second source/drain region of transistors 229-1 and 229-2 is commonly coupled to an active positive control signal 265 (ACT). The ACT signal 265 can be a supply voltage (e.g., VDD) and the RnIF signal can be a reference voltage (e.g., ground). Activating signals 228 and 265 enables the cross coupled latch 215.
The enabled cross coupled latch 215 operates to amplify a differential voltage between latch input 233-1 (e.g., first common node) and latch input 233-2 (e.g., second common node) such that latch input 233-1 is driven to one of the ACT signal voltage and the RnIF signal voltage (e.g., to one of VDD and ground), and latch input 233-2 is driven to the other of the ACT signal voltage and the RnIF signal voltage.
The sense amplifier 206 can also include circuitry configured to equilibrate the data lines D and D— (e.g., in association with preparing the sense amplifier for a sensing operation). In this example, the equilibration circuitry comprises a transistor 224 having a first source/drain region coupled to a first source/drain region of transistor 225-1 and data line D 205-1. A second source/drain region of transistor 224 can be coupled to a first source/drain region of transistor 225-2 and data line D_ 205-2. A gate of transistor 224 can be coupled to gates of transistors 225-1 and 225-2.
The second source drain regions of transistors 225-1 and 225-2 are coupled to an equilibration voltage 238 (e.g., VDD/2), which can be equal to VDD/2, where VDD is a supply voltage associated with the array. The gates of transistors 224, 225-1, and 225-2 can be coupled to control signal 225 (EQ). As such, activating EQ enables the transistors 224, 225-1, and 225-2, which effectively shorts data line D to data line D— such that the data lines D and D— are equilibrated to equilibration voltage VDD/2. According to a number of embodiments of the present disclosure, a number of logical operations can be performed using the sense amplifier 206 and compute component 231, and the result can be stored in the sense amplifier and/or compute component.
The sensing circuitry 250 can be operated in several modes to perform logical operations, including a second mode in which a result of the logical operation is initially stored in the sense amplifier 206, and a first mode in which a result of the logical operation is initially stored in the compute component 231. Operation of the sensing circuitry 250 in the second mode is described below with respect to
As described further below, the sense amplifier 206 can, in conjunction with the compute component 231, be operated to perform various logical operations using data from an array as input. In a number of embodiments, the result of a logical operation can be stored back to the array without transferring the data via a data line address access (e.g., without firing a column decode signal such that data is transferred to circuitry external from the array and sensing circuitry via local I/O lines). As such, a number of embodiments of the present disclosure can enable performing logical operations and compute functions associated therewith using less power than various previous approaches. Additionally, since a number of embodiments eliminate the need to transfer data across I/O lines in order to perform compute functions (e.g., between memory and discrete processor), a number of embodiments can enable an increased parallel processing capability as compared to previous approaches.
Each column of memory cells can be coupled to sensing circuitry (e.g., sensing circuitry 150 shown in
In a number of embodiments, the sensing circuitry (e.g., compute components 331 and sense amplifiers 306) is configured to perform a multiplication operation on elements stored in array 301. As an example, a first plurality of elements can be stored in a first group of memory cells coupled to a particular access line (e.g., 304-0) and to a number of sense lines (e.g., 305-0 to 305-S), and a second plurality of elements can be stored in a second group of memory cells coupled to a different access line (e.g., 304-1) and the respective number of sense lines (305-0 to 305-S). Each element of the first plurality of elements can be multiplied by a respective one of the second plurality of elements, and the result of the multiplication operation can be stored (e.g., as a bit-vector(s)) in a third group of memory cells coupled to a particular access line (e.g., 304-0 to 304-R) and to the number of sense lines (e.g., 305-0 to 305-S). The third group of memory cells can, for example, be coupled to an access line 304-R or to at least one of access lines 304-0 to 304-R. That is, the third group of memory cells can be a same group of memory cells as the first group of memory cells or the second group of memory cells (e.g., a result of a multiplication operation can be written over a currently stored element).
An example multiplication operation is described below in association with
The example shown in
As described further below, the bit vectors 433 (Dynamic Mask), 435 (Static Mask), 437 (Carry), 439 (Intermediate), 441 (Intermediate 2), and 447 (Dest) can be used in association with multiplying the first elements (e.g., the elements of the srca bit-vector 443) by the respective second elements (e.g., the elements of the srcb bit-vector 445). The bit-vectors 433, 435, 437, 439, 441, and 447 can be stored in respective groups of memory cells coupled to particular access lines, which may be referred to as temporary storage rows (e.g., rows storing data that may be updated during various phases of a multiplication operation). As an example, the bit-vectors 433, 435, 437, 439, 441, and 447 can have a same width as the srca and srcb bit-vectors 443 and 445, respectively, and can be stored in cells coupled the same sense lines as the srca and srcb bit-vectors (e.g., sense lines 305-0 to 305-31). For instance, the bit-vector 433 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-2 and to sense lines 305-0 to 305-31, the bit-vector 435 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-3 and to sense lines 305-0 to 305-31, the bit-vector 437 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-4 and to sense lines 305-0 to 305-31, the bit-vector 439 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-5 and to sense lines 305-0 to 305-31, the bit-vector 441 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-6 and to sense lines 305-0 to 305-31, and the bit-vector 447 can be a 32 bit wide bit-vector stored in a group of cells coupled to access line 304-R and to sense lines 305-0 to 305-31. The bit-vector 431 (Comp_Comp) represents the data stored in the sensing circuitry (e.g., compute components (e.g., 331) and/or sense amplifiers 306) corresponding to the sense lines having cells coupled thereto which store elements being multiplied (e.g., sense lines 305-0 to 305-31 in this example).
As an example, the first element of the srca bit-vector 443 (e.g., hexadecimal value “07”) can be stored (e.g., as an 8 bit wide bit-vector [00000111]) in memory cells 303-0 to 303-7, and the first element of the srcb bit-vector 445 (e.g., hexadecimal value “03”) can be stored (e.g., as an 8 bit wide bit-vector [00000011]) in memory cells coupled to access line 304-1 (e.g., ROW 1) and to sense lines 305-0 to 305-7. As an example, the most significant bits (MSBs) of the respective bit-vectors (e.g., [00000111] and [00000011]) can be stored in cells coupled to sense line 305-0, the next MSBs of the respective bit-vectors can be stored in cells coupled to sense line 305-1, . . . , and the least significant bits (LSBs) of the respective bit-vectors can be stored in cells coupled to sense line 305-8. As used herein, the left most bit of a bit-vector is considered the MSB; however, embodiments are not so limited.
In a number of examples, a multiplication operation includes performing a number of AND operations, OR operations, SHIFT operations, INVERT operations, and BlockOR operations. The multiplication operation includes performing the AND operations, OR operations, SHIFT operations, and INVERT operations without transferring data via an input/output (I/O) line to multiply a first element by a second element. The number of AND operations, OR operations, INVERT operations, and SHIFT operations can be performed using sensing circuitry on pitch with each of a number of columns of complementary sense lines.
The below pseudocode represents instructions executable to perform a number of multiplication operations in a memory in accordance with a number of embodiments of the present disclosure. The example pseudocode is referenced using reference numbers 1-8, which correspond to the reference numbers of the rows shown in the tables of
For purposes of discussion, the above pseudocode will be divided into a setup phase and a multiplication phase associated with performing a multiplication operation (e.g., multiplying the four elements of the srca bit-vector 443 by the corresponding four elements of the srcb bit-vector 445). The pseudocode referenced by reference numbers 1-7 can correspond to the setup phase. The setup phase can be performed simultaneously for a number of the multiplication operations. In this example, bit-vectors can be illustrated in bold to indicate a change in the bit-vector stored in a particular location (e.g., the bit-vector stored in Comp_Comp 431 can change from [0x0] to [0x80000000] from reference 451-3 to reference 451-4 and would be bolded to indicate the change).
In a number of embodiments, the setup phase can be performed simultaneously for all of the elements that will be multiplied. The results (e.g., the resulting stored bit-vectors) corresponding to a number of operations performed in the setup phase are shown in
Row 451-1 of the table shown in
Reference number 3 (e.g., “Obtain all Temp Rows”) of the above pseudocode is associated with initializing a number of groups of memory cells for use as temporary storage rows. That is, the number of groups of memory cells can be groups of cells coupled to respective access lines (e.g., rows) and can be used to store data (e.g., on a temporary basis) in association with performing the multiplication operation. For example, a first group of memory cells can be coupled to a particular access line (e.g., 304-2, illustrated as ROW 2) and can store a bit-vector referred to as a “Row_Dynamic_Mask” bit-vector 433. A second group of memory cells can be coupled to another access line (e.g., 304-3, illustrated as ROW 3) and can store a bit-vector referred to as a “Row_Static_Mask” bit-vector 435. A third group of memory cells can be coupled to another access line (e.g., 304-4, illustrated as ROW 4) and can store a bit-vector referred to as a “Row_Carry” bit-vector 437. A fourth group of memory cells can be coupled to another access line (e.g., 304-5, illustrated as ROW 5) and can store a bit-vector referred to as a “Row_Intermediate” bit-vector 439. A fifth group of memory cells can be coupled to another access line (e.g., 304-6, illustrated as ROW 6) and can store a bit-vector referred to as a “Row_Intermediate2” bit-vector 441. In a number of embodiments, the “Dest” bit-vector 447 can be stored in a group of memory cells coupled to another access line (e.g., 304-R, illustrated as ROW N), which can be considered a temporary storage row. Embodiments are not limited to a particular number of temporary storage rows and/or to storage of the corresponding bit-vectors on particular access lines. Also, although the groups of memory cells used to store bit-vectors 433, 435, 437, 439, 441, and 447 may be referred to as “rows,” the respective groups of memory cells may comprise fewer than all of the cells coupled to a particular access line. In a number of examples, the bit-vectors 433, 435, 437, 439, 441, and 447 stored in memory cells corresponding to the temporary storage rows are stored in memory cells coupled to the same sense lines as the element pairs that are being multiplied.
The Row_Dynamic_Mask bit-vector 433 can be used, for instance, to indicate a particular bit position (e.g., a LSB) within elements being multiplied. The particular bit position indicated by the Row_Dynamic_Mask 433 can be used to determine a contribution of the bit at the particular bit position within the element being multiplied (e.g., the contribution being based on whether the bit is a “1” or “0”). The Row_Static_Mask 433 can be used to provide a mask to perform the multiplication operation. As described further below, the Row_Carry bit-vector 437 can be used to store a carry value from a contribution of a bit at a particular bit position within an element in order to apply the carry value to a next-most-significant bit position, for instance. A carry value can include a value of a bit at a particular bit position within an element (e.g., a “1” at an LSB position such as in bit-vector [00000001]) that carries a value of a bit to an additional bit position (e.g., a position of the 1 in bit-vector [00000010]. When a data value of a bit-vector (e.g., bit-vector [00000001] is added to a data value of another bit-vector (e.g., bit-vector [00000001], the two 1s in the LSB position can provide a carry value of 1 when added together (e.g., bit-vector [00000001] added to bit-vector [00000001] results in a bit-vector of [00000011]). The Row_Intermediate bit-vector 439 and the Row_Intermediate2 bit-vector 441 can be used to store temporary data values while performing the multiplication operation. The Dest bit-vector 447 can be used to store a result of an iteration of operations during performance of the multiplication operation and a result of the multiplication operation once the iterations of operations are complete. Row 451-3 of
Reference number 4 (e.g., “Determine MSB and store in Comp_Comp, Row_Dynamic_Mask”) of the above pseudocode is associated with determining the MSB of the srca 443 and/or srcb 445 bit-vectors and storing, as a bit-vector, a bit pattern indicating the MSB of the bit-vectors 443 and/or 445 in particular groups of memory cells. As an example, the bit pattern indicating the MSB of the bit-vectors 443 and/or 445 can be stored (e.g., as a bit-vector) in the group of memory cells used to store the Row_Dynamic_Mask bit-vector 433 and can be stored in the group of compute components (e.g., 331-0 to 331-31) as Comp_Comp bit-vector 431. In a number of embodiments, the bit pattern indicating the MSB of the srca and srcb bit-vectors comprises a “1” bit in the MSB position and a “0” bit in the remaining bit positions. For instance, as shown in row 451-4 of the table of
The pseudocode referenced at reference number 5 (e.g., “Determine MSB by shifting right with fixed vector for each length into Comp_Comp”) is associated with determining a bit-vector that can indicate a MSB position corresponding to each of the respective elements represented by srca 443 and srcb 445. The bit-vector used to indicate the MSBs corresponding to the number of elements can be determined by performing a number of logical operations (e.g., a number of iterations of SHIFT operations and OR operations) on the bit-vector 431 stored in the compute components (e.g., 331-0 to 331-31 in
For example, a SHIFT operation can be performed on the bit-vector [10000000 00000000 00000000 00000000 (e.g., [0x80000000]) stored in the Comp_Comp 431 at reference number 451-4. The SHIFT operation can include shifting the “1” bit over eight compute components to result in the bit-vector [00000000 100000000 00000000 00000000] (e.g., [0x00800000]). The resulting bit-vector [0x00800000] stored in the Comp_Comp 431 after shifting can be ORed with the Row_Dynamic_Mask bit-vector 433 [0x80000000], resulting in a bit-vector [0x80800000]. The bit-vector [0x80800000] can be stored as the Row_Dynamic_Mask 433 bit-vector (replacing the previous bit-vector). An additional SHIFT operation can include shifting the bit-vector [0x80800000] stored in Comp_Comp 431 eight compute components to the right, resulting in bit-vector—0x00808000]. The bit-vector [0x00808000] can be ORed with the bit-vector [0x80800000] stored as the Row_Dynamic_Mask 433, resulting in bit-vector—0x80808000]. A final SHIFT and OR operation (including eight shifts to the right and an OR operation) can result in the bit-vector [0x80808080] stored as the Row_Dynamic_Mask 433. The results of the SHIFT operations and the OR operations can be stored in the group of memory cells used to store Row_Dynamic_Mask 433 and the compute components (e.g., 331-0 to 331-31 in
At reference 451-6 (e.g., “Invert Comp_Comp and store in Row_Static_Mask), an invert operation can be performed on the bit-vector stored in the Comp_Comp 431 (e.g., bit-vector [0x80808080] stored in compute components 331-0 to 331-31). The resulting bit-vector (e.g., referred to as the “Row_Static_Mask bit-vector” 435) of the invert operation (e.g., bit-vector [0x7f7f7f7f]) can be stored in a group of memory cells as the Row_Static_Mask bit-vector 435.
The pseudocode referenced at reference number 7 (e.g., “Find Vectors of LSBs”) includes finding LSBs for the vectors. At reference 451-7a (e.g., “Find LSB and store in Comp_Comp, Row_Intermediate), an LSB of the bit-vector (e.g., [0x00000001]) is determined by setting all of the Comp_Comp 431 to “1”s (e.g., compute components store bit-vector [0xffffffff]). A LEFT shift is performed on the Comp_Compe 431 so that the Comp_Comp 431 stores bit-vector [0xfffffffe]. An inverse operation is performed on the bits stored in the Comp_Comp 431, resulting in a bit-vector [0x00000001] that indicates an LSB of the bit-vector. The resulting bit-vector [0x00000001] is stored as the Row_Intermediate bit-vector 439.
At reference 451-7b (e.g., “Load Row_Dynamic_Mask in Comp_Comp and LEFT Shift 1”), the Row_Dynamic_Mask bit-vector 433 (e.g., bit-vector [0x80808080]) is shifted in the Comp_Comp 431 left one position, resulting in bit-vector [0x01010100], as shown at reference 451-7b. At reference 451-7c (e.g., “Perform OR operation with Row_Intermediate and store in Row_Dynamic Mask”), the bit-vector [0x01010100] stored in Comp_Comp 431 is ORed with the Row_Intermediate bit-vector 439 (e.g., bit-vector [0x00000001]). The resulting bit-vector of the OR operation (e.g., bit-vector [0x01010101]) is stored as the Row_Dynamic_Mask bit-vector 433. At reference 7.d (e.g., “Clear Row_Intermediate”), the Row_Intermediate bit-vector 439 is cleared, resulting in a Row_Intermediate bit-vector 439 of [0x00000000] (indicated by [0x0]).
A multiplication phase begins at reference 8.a and concludes at reference 8.q. The multiplication phase can further be divided into a number of iterations of operations. For example, at reference 8 (e.g., “For Given Vector Fixed Width:”), an operation can include a number of iterations of operations. For instance, reference 8 refers to a “For” loop that iterates through a number of logical operations for multiplying each bit-vector's elements by corresponding elements of another bit-vector. Each iteration of the number of iterations can begin at reference 8.a and can conclude at reference 8.q. An iteration of operations can be executed to determine a data value contribution corresponding to a particular bit position of elements being multiplied. For example, a first element (e.g., [0000 0111]) and a second element (e.g., [0000 0011]) that have a bit-vector width of eight can contribute to a multiplication operation. During a first iteration of operations, a data value contribution of the first element and the second element can be determined for the least-significant-bit (LSB) position of the first element (e.g., the bit in bold of bit-vector [0000 0111]) and the second element (e.g., the bit in bold of bit-vector [0000 0011]). During a second iteration of operations, a data value contribution of the first element and the second element can be determined for the next LSB position for the first element (e.g., [0000 0111]) and the second element (e.g., [0000 0011]). The number of iterations of operations can be based on a bit-vector length of an element being multiplied. For example, in this instance, the number of iterations can be associated with an element-length of eight. At the completion of reference 8.q, temporary rows can be released at the completion of the multiplication operation. In a number of examples, the results of the multiplication operation can be stored in the array 301. In a number of examples, each iteration of the “For” loop that begins at reference 8.a can be performed sequentially.
At reference 8.a. (e.g., “Load srcb in Comp_Comp”) of the above pseudocode, the srcb bit-vector 445 (e.g., bit-vector [0x03050203]) can be loaded into the appropriate compute components (e.g., compute components 331-0 to 331-31 in this example) For example, the 8 bits corresponding to the first element (e.g., [0x03] or binary [00000011]) can be loaded into compute components 331-0 to 331-7 (e.g., with the MSB being loaded into compute component 331-0 and each subsequent next-most-significant bit being loaded into the subsequent corresponding compute components 331-1 to 331-7 such that a “0” is stored in compute components 331-0 to 331-5 and a “1” is stored in compute components 331-6 and 331-7). Subsequent elements (e.g., the second ([0x05], third ([0x02]), and fourth ([0x03]) element) of the srcb bit-vector 445 can be loaded into subsequent corresponding compute components 331-8 to 331-31. As such, row 451-8.a of the table shown in
At reference 8.b (e.g., “Do Comp_Comp AND operation with Row_Dynamic_Mask”), an AND logical operation can be performed on the bit-vector 431 (e.g., bit-vector [0x03050203]) shown in row 451-8.a (e.g., previously latched in the compute components 331-0 to 331-31) and the Row_Dynamic_Mask bit-vector 433 (e.g., bit-vector [0x01010101], which can be stored in memory cells coupled to the access line 304-2 and to sense lines 331-0 to 331-31). As used herein, performing a logical operation on a first and second bit-vector can include performing, in parallel, the logical operation on each of the respective bits at particular bit positions of the bit-vectors in parallel. As an example, the result of a logical AND operation performed on a first bit-vector “a” and a second bit-vector “b” is a bit-vector whose MSB is the result of “ANDing” the MSB of bit-vector “a” and the MSB of bit-vector “b,” whose next MSB is the result of ANDing the next MSBs of bit-vectors “a” and “b, and whose LSB is the result of ANDing the LSB of bit-vector “a” and the LSB of bit-vector “b.” For instance, performing an AND operation on a bit-vector [1110] and on bit-vector [1000] would result in bit-vector (e.g., the MSB of the resultant bit-vector is “1” since “1” AND “1” is “1”, the next MSB is “0” since “1” AND “0” is “0”, the next MSB is “0” since “1” AND “0” is “0”, and the LSB is “0” since “0” AND “0” is “0”).
Since the value of the srcb bit-vector 445 was loaded into the compute components 331-0 to 331-31, the result of “ANDing” the bit-vector 431 with the bit-vector 433 is analogous to the result of performing an AND operation on the srcb bit-vector 445 and the Row_Dynamic_Mask bit-vector 433. As such, bit-vector [00000011 00000101 00000010 00000011] (e.g., [0x03050203]) is “ANDed” with bit-vector [00000001 00000001 00000001 00000001] (e.g., [0x01010101]), which results in bit-vector [00000001 00000001 00000000 00000001] (e.g., [0x01010001]). In a number of examples, the results of the AND logical operation can be retained in the compute components (e.g., 331-0 to 331-31) as bit-vector 431. For instance, row 451-8.b illustrates the Comp_Comp bit-vector 431 as being [0x01010001].
At reference 8.c (e.g., “Store Comp_Comp in Row_Intermediate 2”), the result of the AND operation performed at reference 8.b (e.g., bit-vector [0x01010001]) is stored in (e.g., written to) the memory cells storing the Row_Intermediate_2 bit-vector 441. As an example, the Row_Intermediate_2 bit-vector 441 can be stored in cells coupled to access line 304-6 and to sense lines 305-0 to 305-31. Row 451-8.c of the table shown in
At reference 8.d (e.g., “Duplicate bits for each vector by left shifting and OR with Row_Intermediate 2), bits of the Intermediate 2 bit-vector 441 (e.g., [0x01010001]) are duplicated. Duplicating bits refers to filling an element with a particular bit that is in a least-significant bit position. For example, a bit (e.g., “1”) of bit-vector [0000 0001] can be duplicated by adding the “1” bit in the least significant bit position to each position of the element, resulting in bit-vector [1111 1111]. Duplication is performed by performing a SHIFT operation (e.g., a left shift operation) and an OR operation with a bit-vector (e.g., Row_Intermediate 2 bit-vector 441 illustrated as [0x01010001] at Row 451-8.c in
Each subsequent left-shift operation and OR operation results in duplicating bits across the first element bit-vector until the resulting first element bit-vector is [1111 1111]. The bits of the second, third, and fourth element of bit-vector [0x01010001] stored as the Intermediate 2 bit-vector 441 (at Row 451-8.c in
At reference 8.e (e.g., “Load srca in Comp_Comp”), srca bit-vector 443 (e.g., bit-vector [0x0704080c]) is loaded into corresponding compute components (e.g., Comp_Comp 431, corresponding to compute components 331-0 to 331-31). For example, the bits of the first element of the srca bit-vector (e.g., first element bit-vector [0000 0111]) can be stored in corresponding compute components such that a first, second, third, fourth, and fifth compute component (e.g., compute components 331-0 through 331-4) store a “0”, and a sixth, seventh, and eight compute component (e.g., compute components 331-5 through 331-7) store a “1.” In this example, additional compute components (e.g., compute components 331-8 to 331-31) store the second, third, and fourth elements of the srca bit-vector 443.
At reference 8.f (e.g., “Do Comp_Comp left shift for current iteration”), a SHIFT operation is performed on the srca bit-vector stored in Comp_Comp 431 based on an iteration of the multiplication operation. For example, for a first iteration of the multiplication operation (e.g., illustrated by Rows 451-8.a to 451-8.q in
At reference 8.g (e.g., “Do Comp_Comp AND operation with Row_Intermediate 2 and store in Row_Intermediate 2), the srca bit-vector stored in Comp_Comp 431 (e.g., [0x0704080c]) is ANDed with the Intermediate 2 bit-vector 441 (e.g., [0xffff00ff]). For example, srca bit-vector [0x0704080c] is ANDed with bit-vector [0xffff00ff] to result in bit-vector [0x0704000c]. The resulting bit-vector [0x0704000c] is stored as the Row_Intermediate 2 bit-vector 441. That is, at row 451-8.g in
At 8.h (e.g., “Halfadd Row_Intermediate and Row_Intermediate 2 output dest and Row_Carry), a half-add operation is performed on the Row_Intermediate bit-vector 439 and the Row_Intermediate 2 bit-vector 441. A half-add operation includes performing an XOR operation and an AND operation.
An XOR operation on two bit-vectors can be performed by a number of NAND, OR, and AND operations. The XOR operation on the two bit-vectors can include performing an AND operation on a result of a NAND operation and a result of an OR operation. For example, an XOR operation can be performed on a first bit-vector (e.g., [0011]) and a second bit-vector (e.g., [0110]). The XOR operation includes a NAND operation that can be performed on the first and second bit-vector, resulting in a bit-vector [1101] (e.g., ANDing [0011] and [0110] to result in [0010], and inversing the [0010] bit-vector to result in an XOR result of [1101]). The XOR operation includes an OR operation that can be performed on the first and second bit-vector, resulting in bit-vector [0111] (e.g., ORing [0011] and [0110]). The XOR operation includes an AND operation that can be performed on the result of the NAND operation (e.g., NAND operation result [1101]) and the result of the OR operation (e.g., OR operation result [0111]). The result of the AND operation (e.g., ANDing [1101] and [0111]) is bit-vector [0101], which is the result of an XOR operation performed on the first bit-vector (e.g., [0011]) and the second bit-vector (e.g., [0110]).
The result of the XOR operation on the Row_Intermediate bit-vector 439 and the Row_Intermediate 2 bit-vector 441 is stored, as shown at row 451-8.h, as the Dest bit-vector 447 (e.g., in a group of memory cells such as memory cells coupled to access line 304-R and sense lines 305-0 to 305-31). The result of the AND operation (e.g., [0x00000000] ANDed with [0x0704000c]) is stored as the Row_Carry bit-vector 437 (e.g., stored in memory cells coupled to access line 304-4 and to sense lines 305-0 to 305-31). That is, at row 451-8.h, the Row_Carry bit-vector 437 remains [0x00000000] (indicated by [0x0]). In addition, the Row_Intermediate bit-vector 439 (e.g., [0x00000000]) is XORed with the Row_Intermediate 2 bit-vector 441 (e.g., [0x0704000c]) and is stored, as shown at row 451-8.h as the Dest bit-vector 447. In this example, there is no half-add operation to perform since there are “0”s stored as the Row_Intermediate bit-vector 439, and the result of the AND operation results in a Row_Carry bit-vector 437 of [0x00000000]. The bit-vector [0x0704000c] stored in Comp_Comp 431, at row 451-8.h, from the XOR operation (e.g., [0x0] XORed with [0x0704000c] resulting in [0x0704000c]) is stored as the Dest bit-vector 447. Examples of the half-add operation will be described further below in the description of
References 8.h to 8.l will be described further below in relation to the second iteration of operations in
At 8.m (e.g., “Load Dest in Comp_Comp), the Dest bit-vector 447 (e.g., [0x0704000c]) is loaded into the compute components (e.g., Comp_Comp 431 corresponding to compute components 331 in
At reference 8.b (e.g., “Do Comp_Comp AND operation with Row_Dynamic_Mask”), an AND logical operation can be performed on the bit-vector (e.g., bit-vector [0x03050203]) shown in row 453-8.a (e.g., previously latched in the compute components 331-0 to 331-31) and the Row_Dynamic_Mask bit-vector 433 (e.g., bit-vector 0x02020202, which can be stored in memory cells coupled to the access line 304-2 and to sense lines 331-0 to 331-31) As used herein performing a logical operation on a first and second bit-vector can include performing, in parallel, the logical operation on each of the respective bits at particular bit positions of the bit-vectors in parallel. As an example, the result of a logical AND operation performed on a first bit-vector “a” and a second bit-vector “b” is a bit-vector whose MSB is the result of “ANDing” the MSB of bit-vector “a” and the MSB of bit-vector “b,” whose next MSB is the result of ANDing the next MSBs of bit-vectors “a” and “b, and whose LSB is the result of ANDing the LSB of bit-vector “a” and the LSB of bit-vector “b.” For instance, performing an AND operation on a bit-vector [1110] and on bit-vector [1000] would result in bit-vector (e.g., the MSB of the resultant bit-vector is “1” since “1” AND “1” is “1”, the next MSB is “0” since “1” AND “0” is “0”, the next MSB is “0” since “1” AND “0” is “0”, and the LSB is “0” since “0” AND “0” is “0”).
Since the value of the srcb bit-vector 445 was loaded into the compute components 331-0 to 331-31, the result of “ANDing” the bit-vector 431 with the bit-vector 433 is analogous to the result of performing an AND operation on the srcb bit-vector 445 and the Row_Dynamic_Mask bit-vector 433. As such, bit-vector [00000011 00000101 00000010 00000011] (e.g., [0x03050203]) is “ANDed” with bit-vector [00000010 00000010 00000010 00000010] (e.g., [0x02020202]), which results in bit-vector [00000010 00000000 00000010 00000010] (e.g., [0x02000202]). In a number of examples, the results of the AND logical operation can be retained in the compute components (e.g., 331-0 to 331-31) as bit-vector 431. For instance, row 453-8.b illustrates the Comp_Comp bit-vector 431 as being [0x02000202].
At reference 8.c (e.g., “Store Comp_Comp in Row_Intermediate 2), the result of the AND operation performed at reference 8.b (e.g., bit-vector [0x02000202]) is stored in (e.g., written to) the memory cells storing the Row_Intermediate_2 bit-vector 441. As an example, the Row_Intermediate_2 bit-vector 441 can be stored in cells coupled to access line 304-6 and to sense lines 305-0 to 305-31. Row 451-8.c of the table shown in
At reference 8.d (e.g., reference “8.d Duplicate bits for each vector by left shifting and OR with Row_Intermediate 2), bits of the Row_Intermediate 2 bit-vector 441 are duplicated. Duplicating bits refers to filling an element with a particular bit in a least-significant bit position. For example, a bit (e.g., “1”) of bit-vector [0000 0001] can be duplicated by adding the “1” bit in the least significant bit position to each position of the element, resulting in bit-vector [1111 1111]. Duplication is performed by performing a SHIFT operation (e.g., a left shift operation) and an OR operation with a bit-vector (e.g., Row_Intermediate 2 bit-vector 441 illustrated as [0x02000202] at Row 453-8.c in
Each subsequent left-shift operation and OR operation results in duplicating bits across the first element bit-vector (e.g., [0000 0010]) until the resulting bit-vector is [1111 1110] is stored in the corresponding compute components (e.g., compute components 331-0 to 331-7). The bits of the second, third, and fourth element of bit-vector [0x02000202] of the Row_Intermediate bit-vector 441 [0x02000202] at reference 453-8.c are also duplicated. For example, the second element bit-vector [0000 0000] results in bit-vector [0000 0000] since there is no “1” bit to duplicate. The third element bit-vector [0000 0010] results in bit-vector [1111 1110]. The fourth element bit-vector [0000 0010] results in bit-vector [1111 1110]. Each element can be duplicated simultaneously using sensing circuitry such that a least-significant bit in the first, second, third, and fourth elements are left-shifted at the same time to perform the duplication in parallel. After duplication of the Row_Intermediate 2 bit-vector 441 (e.g., the Row_Intermediate 2 bit-vector [0x02000202]) at row 451-8.c), the Row_Intermediate 2 bit-vector 441 is [1111 1110, 0000 0000, 1111 1110, 1111 1110] or [0xfe00fefe], at row 451-8.d in
At 8.e (e.g., “Load srca in Comp_Comp”), srca bit-vector 443 (e.g., bit-vector [0x0704080c]) is loaded into corresponding compute components (e.g., compute components 331-0 to 331-31). For example, the bits of the first element of the srca bit-vector (e.g., first element bit-vector [0000 0111]) can be stored in corresponding compute components such that a first, second, third, fourth, and fifth compute component (e.g., compute components 331-0 through 331-4) store a “0”, and a sixth, seventh, and eight compute component (e.g., compute components 331-5 through 331-7) store a “1.” Additional compute components (e.g., corresponding compute components 331-8 through 331-31) store the corresponding second, third, and fourth elements of the bit-vector, in this example. That is, at row 451-8.e, the bit-vector [0x0704080c] is loaded into the Comp_Comp 431.
At reference 8.f (e.g., “Do Comp_Comp left shift for current iteration”), a SHIFT operation is performed on the bit-vector stored in the compute components based on an iteration of the multiplication operation. For example, during a second iteration of the multiplication operation (e.g., from row 453-8.a to row 453-8.q) the srca bit-vector is shifted one position. That is, during the second iteration the bits are shifted one (1) compute component to the left. During a third iteration the bits are shifted twice (2), etc. Therefore, at reference 8.f, the bits of the first element of the srca bit-vector (e.g., [0000 0111] or [0x07) are shifted one compute component to the left to result in a first element of the srca bit-vector of [0000 1110] or [0x0e]. The second element of the srca bit-vector (e.g., [0000 0100]) is shifted one compute component to the left to result in a second element of the srca bit-vector of [0000 1000], the third element of the srca bit-vector [0000 1000] is shifted left to result in a third element bit-vector of [0001 0000], and the fourth element of the srca bit-vector [0000 1100] is shifted left to result in a fourth element bit-vector of [0001 1000]. Therefore, the bits of srca bit-vector [0x0704080c] are shifted one compute component to the left to result in bit-vector [0x0e081018] stored, at row 453-8.f, in the Comp_Comp 431.
At reference 8.g (e.g., “Do Comp_Comp AND operation with Row_Intermediate 2 and store in Row_Intermediate 2”), the bit-vector [0x0e081018] stored in Comp_Comp 431 at row 453-8.f is ANDed with the bit-vector stored as the Row_Intermediate 2 bit-vector 441 (e.g., bit-vector [0xfe00fefe] at row 453-8.f). For example, bit-vector [0x0e081018] is ANDed with bit-vector [0xfe00fefe] to result in bit-vector [0x0e001018], which is stored as the Row_Intermediate 2 bit-vector 441 at row 451-8.g. At reference 8.h (e.g., “Halfadd Row_Intermediate and Row_Intermediate 2 output dest and Row_Carry”), a half-add operation is performed on the Row_Intermediate bit-vectors 439 (e.g., bit-vector [0x0704000c] at row 453-h of
At reference 8.i (e.g., “Load Row_Carry in Comp_Comp”), the bit-vector (e.g., bit-vector [0x06000008]) stored as the Row_Carry bit-vector 437 is loaded into the compute components (e.g., computer components 331-0 to 331-31), at row 453-8.i of
At reference 8.l (e.g., “For any true bits in Comp_Comp BlockOR), a loop to determine whether three are any carry-over bits continues while the bit-vector stored in the Comp_Comp 431 includes a “1” bit. A BlockOR operation (described below) is performed to determine if the bit-vector stored in the Comp_Comp 431 comprises any “1” bits. For example, the bit-vector [0x0c000010], stored in Comp_Comp 431 at row 453-8.l, includes at least one “1” bit which indicates to continue the loop. The loop starting at reference 8.l can include, at reference 8.l.i, storing the bit-vector (e.g., bit-vector [0x0c000010] stored in the Comp_Comp 431 at row 453-8.l) as the Row_Carry bit-vector 437.
In a number of embodiments, a “BlockOR” operation can be performed in association with determining if the memory cells coupled to one or more (e.g., any) particular sense line store a particular data value (e.g., a bit of “1” or a bit of “0”). The determination of whether any of the sense lines are coupled to cells storing a particular data value can include charging (e.g., precharging) a local I/O line (e.g., local I/O line 334 in
Performing a BlockOR operation (which may be referred to as an “AccumulatorBlockOr”), the column decode lines (e.g., column decode lines 310-0 to 310-W in
For instance, if the I/O line (e.g., I/O line 334) is precharged to a ground voltage and one or more of the selected compute components (e.g., 331-0 to 331-X) stores a logic 1 (e.g., 0V), then the SSA (e.g., SSA 312) can sense a pull up (e.g., increase) of the voltage on the I/O line (e.g., I/O line 334) to determine whether at least one of the accumulators stores a “1”. Alternatively, if the I/O line (e.g., I/O line 334) is precharged to Vcc and one or more of the selected compute components (e.g., CC 331-0 to 331-X) stores a logic 0 (e.g., 0V) to represent a stored logic “0”, then the SSA (e.g., SSA 312 can sense a pull down (e.g., decrease) of the voltage on the I/O line (e.g., I/O line 334) to determine whether at least one compute component stores a logic “0”. The determination of whether one or more compute components (e.g., CC 331-0 to 331-X) coupled to selected column decode lines (e.g., column decode lines 310-0 to 310-W) stores a particular data value (e.g., a data value of “1”) is effectively performing a logic “OR” operation. In this manner, voltages corresponding to data sensed by sense amps (e.g., SAs 306-0 to 306-U) and/or stored in compute components (e.g., compute components 331-0 to 331-X) can be transferred, in parallel, to the local I/O line (e.g., L I/O line 334) and sensed by the SSA (e.g., SSA 312) as part of a BlockOR operation. Embodiments of the present disclosure are not limited to particular precharge voltages of the local I/O line and/or to particular voltage values corresponding to logic “1” or logic “0”.
At reference 8.l.ii, the loop includes performing a half-add operation on the bit-vector (e.g., bit-vector [0x09041014]) stored as the Dest bit-vector 447 and the bit-vector (e.g., bit-vector [0x0c000010]) stored as the Row_Carry bit-vector 437. The half-add operation includes performing an XOR operation on bit-vector [0x09041014] (stored as the Dest bit-vector 447) and bit-vector [0x0c000010] (stored as the Row_Carry bit-vector 437, resulting in bit-vector [0x05041004]. The result of the XOR operation (e.g., [0x05041004]) is stored as the Dest bit-vector 447, at row 453-8.l.ii. The half-add operation also includes performing an AND operation on bit-vectors [0x09041014] and [0x0c000010], resulting in bit-vector [0x08000010]. At reference 8.l.iii (e.g., “Load Row_Carry in Comp_Comp”), the bit-vector (e.g., bit-vector [0x08000010]) stored in the compute components (e.g., compute components 331-0 to 331-31) is stored as the Row_Carry bit-vector 437.
At reference 8.l.iv (e.g., “Do Comp_Comp AND operation with Row_Static_Mask”), the bit-vector (e.g., bit-vector [0x08000010]) stored in Comp_Comp 431 is ANDed with the bit-vector (e.g., bit-vector [0x7f7f7f7f]) stored as the Row_Static_Mask bit-vector 435. The resulting bit-vector of the AND operation is bit-vector [0x08000010]. At reference 8.l.v (e.g., “Shift Comp_Comp Left”), the bits of the bit-vector (e.g., bit-vector [0x08000010]) stored in the Comp_Comp 431 are shifted by one compute component to the left, resulting in bit-vector [0x10000020]. At reference 8.l.vi (representing a second loop of references 8.l.i through 8.l.v), a half-add operation (e.g., an XOR operation and an AND operation, each stored in separate locations) is performed on the bit-vector stored in the compute components 431 (e.g., bit-vector [0x10000020]) and the Dest bit-vector 447 (e.g., bit-vector [0x05041004]). An XOR operation is performed on the bit-vector stored in the Comp_Comp 431 (e.g., [0x10000020]) and the Dest bit-vector 447 (e.g., [0x05041004]). The result of the XOR operation (e.g., [0x15041024]) is stored as the Dest bit-vector 447. An AND is performed on the bit-vector stored in the Comp_Comp 431 (e.g., [0x10000020]) and the Dest bit-vector 447 (e.g., [0x05041004]). The result of the AND operation (e.g., bit-vector [0x00000000]) is stored as the Row_Carry bit-vector 437, at row 453-8.l.vi. on bit-vectors [0x10000020] and [0x05041004]). The resulting [0x0] bit-vector remaining in the compute components 431 is ANDed with the Row_Static_Mask bit-vector 435, resulting in bit-vector [0x0]. The resulting [0x00000000] bit-vector (indicated by [0x0]) is left-shifted in the compute components 431 resulting in bit-vector [0x0]. A BlockOR operation is performed on the [0x0] bit-vector stored in the Comp_Comp 431 and results in a determination that there are no “1” bits in the bit-vector. The determination of no “1” bits ends the while loop.
At reference 8.m (e.g., “Load dest in Comp_Comp,” illustrated at 453-8.m in
At reference 8.b (e.g., “Do Comp_Comp AND operation with Row_Dynamic_Mask”), an AND logical operation can be performed on the bit-vector (e.g., bit-vector [0x03050203]) previously latched in the compute components (e.g., compute components 331-0 to 331-31) and the Row_Dynamic Mask bit-vector 433 (e.g., bit-vector [0x04040404]). For example, the first element of the srcb bit-vector (e.g., bit-vector [0000 0011] or [0x03]) is ANDed with the first element of the Row_Dynamic_Mask bit-vector 433 (e.g., bit-vector [0000 0100] or [0x04]), resulting in bit-vector [0000 0000]. The second element of the srcb bit-vector (e.g., [0000 0101] or [0x05]) and the Row-Dynamic_Mask bit-vector (e.g., [0000 0100]) are ANDed, the third element of the srcb bit-vector (e.g., [0000 0010] or [0x02]) and the Row_Dynamic_Mask bit-vector (e.g., [0000 0100]) are ANDed, and the fourth elements of the srcb bit-vector (e.g., [0000 0011] or [0x03]) and the Row_Dynamic_Mask bit-vector (e.g., [0000 0100]) are ANDed. The ANDing of the four elements of the srcb bit-vector with the four elements of the Row_Dynamic Mask bit-vector results in bit-vector [0000 0000, 0000 0100, 0000 0000, 0000 0000] or [0x00040000]. In a number of examples, the results of the AND logical operation can be retained in the compute components (e.g., compute components 331-0 to 331-31).
At reference 8.c (e.g., reference “Store Comp_Comp in Row_Intermediate 2”), the result of the AND operations at reference 8.b (e.g., bit-vector [0x00040000]) are stored as the Row_Intermediate 2 bit-vector 441, shown at row 453-8.c in
Each subsequent left-shift operation and OR operation results in duplicating bits across the second element bit-vector until the resulting second element bit-vector is [1111 1100] (or [0xfc]). The bits of the first, third, and fourth element of bit-vector [0x00040000] stored as the Row_Intermediate 2 bit-vector 441 at reference 8.c are also duplicated. However, the duplication of the first, third, and fourth elements results in the same [0x0] bit-vector for each since there is no “1” bit to duplicate. After duplication of the Row_Intermediate 2 bit-vector 441 (e.g., bit-vector [0x00040000]), the Row_Intermediate 2 bit-vector becomes [0000 0000, 1111 1100, 0000 0000, 0000 0000] or [0x00fc0000].
At reference 8.e (e.g., “Load srca in Comp_Comp”), srca bit-vector (e.g., bit-vector [0x0704080c]) is loaded into corresponding compute components (e.g., compute components 331-0 to 331-31 designated as Comp_Comp 431). For example, the eight (8) bits of the first element of the srca bit-vector (e.g., first element bit-vector [0000 0111]) can be stored in corresponding compute components, at row 455-8.e in
At reference 8.f (e.g., “Do Comp_Comp left shift for current iteration”), a SHIFT operation is performed on the srca bit-vector based on an iteration of the multiplication operation. For example, during a third iteration of the multiplication operation (e.g., illustrated by row 455-8.a to row 455-8.q) the srca bit-vector is shifted two (2) positions. Therefore, at reference 8.f, the srca bit-vector is shifted two positions to the left (e.g., shifted over two compute components) to result in bit-vector [0x1c102030], as shown at row 455-8.f.
At reference 8.g (e.g., “Do Comp_Comp AND operation with Row_Intermediate 2 and store in Row_Intermediate 2”), the shifted srca bit-vector (e.g., [0x1c102030], previously stored in Comp_Comp 431 at reference 455-8.f) is ANDed with the Row_Intermediate 2 bit-vector 441 (e.g., bit-vector [0x00fc0000]). For example, the shifted srca bit-vector [0x1c102030] is ANDed with bit-vector [0x00fc0000] to result in bit-vector [0x00100000]. The resulting bit-vector [0x00100000] is stored as the Row_Intermediate 2 bit-vector 441, as show at row 455-8.g.
At reference 8.h (e.g., “Halfadd Row_Intermediate and Row_Intermediate 2 output dest and Row_Carry”), a half-add operation is performed on the Row_Intermediate bit-vector 439 (e.g., [0x15041024]) and the Row_Intermediate 2 bit-vector 441 (e.g., [0x0x00100000]). A half-add operation includes performing an XOR operation and an AND operation. The XOR operation is performed on the bit-vector stored in the Comp_Comp 431 (e.g., [0x00100000] from row 455-8.g) and the Dest bit-vector 447 (e.g., [0x15041024]). The result of the XOR operation (e.g., [0x15141024]) is stored as the Dest bit-vector 447. An AND operation is performed on the bit-vector (e.g., [0x00100000]) (e.g., by loading the Row_Intermediate 2 bit-vector (e.g., bit-vector [0x00100000]) into the Comp_Comp 431) and the Dest bit-vector 447 (e.g., [0x15041024]). The result of the AND operation (e.g., bit-vector [0x00000000]) is stored as the Row_Carry bit-vector 437, at row 455-8.l.h.
At reference 8.i (e.g., “Load Row_Carry in Comp_Comp), the resulting bit-vector [0x0] from the half-add operation that is stored as the Row_Carry bit-vector 437 can be loaded, as shown at row 455-8.i, into the compute components (e.g., corresponding compute components 331-0 to 331-31). At reference 8.j (e.g., “Do Comp_Comp AND operation with Row_Static Mask”), the bit-vector [0x0] stored in Comp_Comp 431 is ANDed with a bit-vector (e.g., bit-vector [0x7f7f7f7f]) stored as the Row_Static_Mask bit-vector 435. At reference 8.k (e.g., “Shift Comp_Comp Left”), a SHIFT operation (e.g., a left-shift operation) is performed on bits in the bit-vector [0x0] stored in compute components (e.g., Comp_Comp 431 corresponding to compute components 331-0 to 331-31 in
At reference 8.l (e.g., “For any true bits in Comp_Comp BlockOR), a BlockOR operation (as described above in relation to rows 453-l.i to 453-8.lv) is performed on the bit-vector stored in Comp_Comp 431 (e.g., [0x0]). Since there are no “1”s in the [0x0] bit-vector stored in Comp_Comp 431, the BlockOR operation ends the while loop (e.g., loop continues while there is a “1” in the bit-vector), as shown in the Comp_Comp 431 at row 455-8.l.
At reference 8.m (e.g., “Load Dest in Comp_Comp”), the Dest bit-vector 447 is loaded into the Comp_Comp 431 (e.g., corresponding to compute components 331-0 to 331-31 in
As subsequent iterations in this example do not change the bit-vector [0x15141024] stored in the memory cells coupled to the Dest access line 447, the subsequent iterations will not be explained in detail here. Subsequent iterations include a Row_Dynamic_Mask bit-vector of [0x08080808] during a fourth iteration, a Row_Dynamic_Mask bit-vector of [0x10101010] during a fifth iteration, a Row_Dynamic_Mask bit-vector of [0x20202020] for a sixth iteration, a Row_Dynamic_Mask bit-vector of [0x40404040] for a seventh iteration, and a Row_Dynamic_Mask bit-vector of [0x80808080] for an eighth iteration. Since a product of the two bit-vectors (e.g., srca bit-vector 443 [0x0704080c] and srcb bit-vector 445 [0x03050203) was determined after three (3) iterations, the fourth through eighth iteration continues with the same value as the Dest bit-vector (e.g., [0x15141024]), as there is no further Carry values to add into the product. The number of iterations corresponds to the fixed width of the bit-vector being multiplied (i.e., a bit-width of 8 bits in this example for each element multiplied). The resultant bit-vector [0x15141024] is a product of bit-vectors [0x0704080c] and [0x03050203]. That is, a first element [0x07] of the first bit-vector [0x0704080c] multiplied by a first element [0x03] of the second bit-vector [0x03050203] results in a first product element of [0x15] (e.g., the first element of the result bit-vector [0x15141024], stored as the Dest bit-vector 447 at row 455-8.q). A second element [0x04] of the first bit-vector multiplied by a second element [0x05] of the second bit-vector results in a second product element of [0x14]. A third element [0x08] of the first bit-vector multiplied by a third element [0x02] of the second bit-vector results in a third product element of [0x10]. A fourth element [0x0c] of the first bit-vector multiplied by a fourth element [0x03] of the second bit-vector results in a fourth product element of [0x24].
In the example illustrated in
The first operation phase of a logical operation described below involves loading a first operand of the logical operation into the accumulator. The time references (e.g., t1, etc.) shown in
At time t1, the equilibration signal 526 is deactivated, and then a selected row is enabled (e.g., the row corresponding to a memory cell whose data value is to be sensed and used as a first input). Signal 504-0 represents the voltage signal applied to the selected row (e.g., Row Y 204-Y shown in
At time t3, the sense amplifier (e.g., 206 shown in
According to some embodiments, the primary latch of sense amplifier 206 can be coupled to the complementary data lines D and D— through respective pass transistors (not shown in
At time t4, the pass transistors (if present) can be enabled (e.g., via respective Passd and Passdb control signals 511 applied to control lines coupled to the respective gates of the pass transistors going high). At time t5, the accumulator positive control signal 512-1 (e.g., Accumb) and the accumulator positive control signal 512-2 (e.g., Accum) are activated via respective control lines 212-1 and 212-2 shown in
At time t6, the Passd control signal 511 (and the Passdb control signal) goes low thereby turning off the pass transistors (if present). However, since the accumulator control signals ACCUMB 512-1 and ACCUM 512-2 remain activated, an accumulated result is stored (e.g., latched) in the secondary latches (e.g., accumulator). At time t7, the row signal 504-0 is deactivated, and the array sense amps are disabled at time t8 (e.g., sense amplifier control signals 528 and 590 are deactivated).
At time t9, the data lines D and D— are equilibrated (e.g., equilibration signal 526 is activated), as illustrated by data line voltage signals 505-1 and 505-2 moving from their respective rail values to the equilibration voltage (VDD/2). The equilibration consumes little energy due to the law of conservation of energy. As described above in association with
As shown in the timing diagrams illustrated in
At time t3, the sense amplifier (e.g., 206 shown in
As shown in timing diagrams illustrated in
Since the accumulator was previously enabled, activating only Passd (511-1 as shown in
Similarly, in an example OR/NOR operation shown in the timing diagram illustrated in
At the conclusion of an intermediate operation phase such as that shown in
For example, performing a last operation phase of an R-input can include performing the operation phase shown in
A NAND operation can be implemented, for example, by storing the result of the R-1 iterations for an AND operation in the sense amplifier, then inverting the sense amplifier before conducting the last operation phase to store the result (described below). A NOR operation can be implemented, for example, by storing the result of the R-1 iterations for an OR operation in the sense amplifier, then inverting the sense amplifier before conducting the last operation phase to store the result (described below).
The last operation phase illustrated in the timing diagram of
As shown in timing diagram illustrated in
Activating the Passd control signal 511 (and Passdb signal) (e.g., in association with an AND or OR operation) transfers the accumulated output stored in the secondary latch of compute component 231 shown in
For an OR operation, if any of the memory cells sensed in the prior operation phases (e.g., the first operation phase of
The result of the R-input AND or OR logical operations can then be stored back to a memory cell of array 230 shown in
The timing diagram illustrated in
As shown in
Although the example of performing a last operation phase of an R-input was discussed above with respect to
The functionality of the sensing circuitry 250 of
Initially storing the result of a particular operation in the sense amplifier 206 (e.g., without having to perform an additional operation to move the result from the compute component 231 (e.g., accumulator) to the sense amplifier 206) is advantageous because, for instance, the result can be written to a row (of the array of memory cells) or back into the accumulator without performing a precharge cycle (e.g., on the complementary data lines 205-1 (D) and/or 205-2 (D_)).
An example of pseudo code associated with loading (e.g., copying) a first data value stored in a cell coupled to row 204-X into the accumulator can be summarized as follows:
Copy Row X into the Accumulator:
Deactivate EQ;
Open Row X;
Fire Sense Amps (after which Row X data resides in the sense amps);
Activate LOAD (sense amplifier data (Row X) is transferred to nodes S1 and S2 of the Accumulator and resides there dynamically);
Deactivate LOAD;
Close Row X;
Precharge;
In the pseudo code above, “Deactivate EQ” indicates that an equilibration signal (EQ signal shown in
After Row X is enabled, in the pseudo code above, “Fire Sense Amps” indicates that the sense amplifier 206 is enabled to set the primary latch and subsequently disabled. For example, as shown at t3 in
The four sets of possible sense amplifier and accumulator signals illustrated in
After firing the sense amps, in the pseudo code above, “Activate LOAD” indicates that the LOAD control signal goes high as shown at t4 in
After setting the secondary latch from the data values stored in the sense amplifier (and present on the data lines 205-1 (D) and 205-2 (D_) in
After storing the data value on the secondary latch, the selected row (e.g., ROW X) is disabled (e.g., deselected, closed such as by deactivating a select signal for a particular row) as indicated by “Close Row X” and indicated at to in
A subsequent operation phase associated with performing the AND or the OR operation on the first data value (now stored in the sense amplifier 206 and the secondary latch of the compute component 231 shown in
Deactivate EQ;
Open Row Y;
Fire Sense Amps (after which Row Y data resides in the sense amps);
Close Row Y;
The result of the logic operation, in the next operation, will be placed on the sense amp, which will overwrite any row that is active.
Even when Row Y is closed, the sense amplifier still contains the Row Y data value;
Activate AND;
This results in the sense amplifier being written to the value of the function (e.g., Row X AND Row Y);
If the accumulator contains a “0” (i.e., a voltage corresponding to a “0” on node S2 and a voltage corresponding to a “1” on node S1), the sense amplifier data is written to a “0”;
If the accumulator contains a “1” (i.e., a voltage corresponding to a “1” on node S2 and a voltage corresponding to a “0” on node S1), the sense amplifier data remains unchanged (Row Y data);
This operation leaves the data in the accumulator unchanged.
Deactivate AND;
Precharge;
In the pseudo code above, “Deactivate EQ” indicates that an equilibration signal corresponding to the sense amplifier 206 is disabled (e.g., such that the complementary data lines 205-1 (D) and 205-2 (D_) are no longer shorted to VDD/2), which is illustrated in
After Row Y is enabled, in the pseudo code above, “Fire Sense Amps” indicates that the sense amplifier 206 is enabled to amplify the differential signal between 205-1 (D) and 205-2 (D_), resulting in a voltage (e.g., VDD) corresponding to a logic 1 or a voltage (e.g., GND) corresponding to a logic 0 being on data line 205-1 (D) (and the voltage corresponding to the other logic state being on complementary data line 205-2 (D_)). As shown at t10 in
After the second data value sensed from the memory cell 202-1 coupled to Row Y is stored in the primary latch of sense amplifier 206, in the pseudo code above, “Close Row Y” indicates that the selected row (e.g., ROW Y) can be disabled if it is not desired to store the result of the AND logical operation back in the memory cell corresponding to Row Y. However,
With the first data value (e.g., Row X) stored in the dynamic latch of the accumulator 231 and the second data value (e.g., Row Y) stored in the sense amplifier 206, if the dynamic latch of the compute component 231 contains a “0” (i.e., a voltage corresponding to a “0” on node S2 and a voltage corresponding to a “1” on node S1), the sense amplifier data is written to a “0” (regardless of the data value previously stored in the sense amp) since the voltage corresponding to a “1” on node S1 causes transistor 209-1 to conduct thereby coupling the sense amplifier 206 to ground through transistor 209-1, pull-down transistor 207-1 and data line 205-1 (D). When either data value of an AND operation is “0,” the result is a “0.” Here, when the second data value (in the dynamic latch) is a “0,” the result of the AND operation is a “0” regardless of the state of the first data value, and so the configuration of the sensing circuitry causes the “0” result to be written and initially stored in the sense amplifier 206. This operation leaves the data value in the accumulator unchanged (e.g., from Row X).
If the secondary latch of the accumulator contains a “1” (e.g., from Row X), then the result of the AND operation depends on the data value stored in the sense amplifier 206 (e.g., from Row Y). The result of the AND operation should be a “1” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is also a “1,” but the result of the AND operation should be a “0” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is also a “0.” The sensing circuitry 250 is configured such that if the dynamic latch of the accumulator contains a “1” (i.e., a voltage corresponding to a “1” on node S2 and a voltage corresponding to a “0” on node S1), transistor 209-1 does not conduct, the sense amplifier is not coupled to ground (as described above), and the data value previously stored in the sense amplifier 206 remains unchanged (e.g., Row Y data value so the AND operation result is a “1” if the Row Y data value is a “1” and the AND operation result is a “0” if the Row Y data value is a “0”). This operation leaves the data value in the accumulator unchanged (e.g., from Row X).
After the result of the AND operation is initially stored in the sense amplifier 206, “Deactivate AND” in the pseudo code above indicates that the AND control signal goes low as shown at t12 in
Although the timing diagrams illustrated in
A subsequent operation phase can alternately be associated with performing the OR operation on the first data value (now stored in the sense amplifier 206 and the secondary latch of the compute component 231) and the second data value (stored in a memory cell 202-1 coupled to Row Y 204-Y). The operations to load the Row X data into the sense amplifier and accumulator that were previously described with respect to times t1-t7 shown in
Deactivate EQ;
Open Row Y;
Fire Sense Amps (after which Row Y data resides in the sense amps);
Close Row Y;
When Row Y is closed, the sense amplifier still contains the Row Y data value;
Activate OR;
This results in the sense amplifier being written to the value of the function (e.g., Row X OR Row Y), which may overwrite the data value from Row Y previously stored in the sense amplifier as follows:
If the accumulator contains a “0” (i.e., a voltage corresponding to a “0” on node S2 and a voltage corresponding to a “1” on node S1), the sense amplifier data remains unchanged (Row Y data);
If the accumulator contains a “1” (i.e., a voltage corresponding to a “1” on node S2 and a voltage corresponding to a “0” on node S1), the sense amplifier data is written to a “1”;
This operation leaves the data in the accumulator unchanged.
Deactivate OR;
Precharge;
The “Deactivate EQ” (shown at is in
With the first data value (e.g., Row X) stored in the secondary latch of the compute component 231 and the second data value (e.g., Row Y) stored in the sense amplifier 206, if the dynamic latch of the accumulator contains a “0” (i.e., a voltage corresponding to a “0” on node S2 and a voltage corresponding to a “1” on node S1), then the result of the OR operation depends on the data value stored in the sense amplifier 206 (e.g., from Row Y). The result of the OR operation should be a “1” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is a “1,” but the result of the OR operation should be a “0” if the data value stored in the sense amplifier 206 (e.g., from Row Y) is also a “0.” The sensing circuitry 250 is configured such that if the dynamic latch of the accumulator contains a “0,” with the voltage corresponding to a “0” on node S2, transistor 209-2 is off and does not conduct (and pull-down transistor 207-1 is also off since the AND control signal is not asserted) so the sense amplifier 206 is not coupled to ground (either side), and the data value previously stored in the sense amplifier 206 remains unchanged (e.g., Row Y data value such that the OR operation result is a “1” if the Row Y data value is a “1” and the OR operation result is a “0” if the Row Y data value is a “0”).
If the dynamic latch of the accumulator contains a “1” (i.e., a voltage corresponding to a “1” on node S2 and a voltage corresponding to a “0” on node S1), transistor 209-2 does conduct (as does pull-down transistor 207-2 since the OR control signal is asserted), and the sense amplifier 206 input coupled to data line 205-2 (D_) is coupled to ground since the voltage corresponding to a “1” on node S2 causes transistor 209-2 to conduct along with pull-down transistor 207-2 (which also conducts since the OR control signal is asserted). In this manner, a “1” is initially stored in the sense amplifier 206 as a result of the OR operation when the secondary latch of the accumulator contains a “1” regardless of the data value previously stored in the sense amp. This operation leaves the data in the accumulator unchanged.
After the result of the OR operation is initially stored in the sense amplifier 206, “Deactivate OR” in the pseudo code above indicates that the OR control signal goes low as shown at t12 in
The sensing circuitry 250 illustrated in
In a similar approach to that described above with respect to inverting the data values for the AND and OR operations described above, the sensing circuitry shown in
Copy Row X into the Accumulator;
Deactivate EQ;
Open Row X;
Fire Sense Amps (after which Row X data resides in the sense amps);
Activate LOAD (sense amplifier data (Row X) is transferred to nodes S1 and S2 of the Accumulator and resides there dynamically;
Deactivate LOAD;
Activate ANDinv and ORinv (which puts the complement data value on the data lines);
Deactivate ANDinv and ORinv;
Close Row X;
Precharge;
The “Deactivate EQ,” “Open Row X,” “Fire Sense Amps,” “Activate LOAD,” and “Deactivate LOAD” shown in the pseudo code above indicate the same functionality as the same operations in the pseudo code for the “Copy Row X into the Accumulator” initial operation phase described above prior to pseudo code for the AND operation and OR operation. However, rather than closing the Row X and Precharging after the Row X data is loaded into the sense amplifier 206 and copied into the dynamic latch, a complement version of the data value in the dynamic latch of the accumulator can be placed on the data line and thus transferred to the sense amplifier 206 by enabling (e.g., causing transistor to conduct) and disabling the invert transistors (e.g., ANDinv and ORinv). This results in the sense amplifier 206 being flipped from the true data value that was previously stored in the sense amplifier to a complement data value (e.g., inverted data value) stored in the sense amp. That is, a true or complement version of the data value in the accumulator can be transferred to the sense amplifier by activating and deactivating ANDinv and ORinv. This operation leaves the data in the accumulator unchanged.
Because the sensing circuitry 250 shown in
When performing logical operations in this manner, the sense amplifier 206 can be pre-seeded with a data value from the dynamic latch of the accumulator to reduce overall current utilized because the sense amps 206 are not at full rail voltages (e.g., supply voltage or ground/reference voltage) when accumulator function is copied to the sense amplifier 206. An operation sequence with a pre-seeded sense amplifier 206 either forces one of the data lines to the reference voltage (leaving the complementary data line at VDD/2, or leaves the complementary data lines unchanged. The sense amplifier 206 pulls the respective data lines to full rails when the sense amplifier 206 fires. Using this sequence of operations will overwrite data in an enabled row.
A SHIFT operation can be accomplished by multiplexing (“muxing”) two neighboring data line complementary pairs using a traditional DRAM isolation (ISO) scheme. According to embodiments of the present disclosure, the shift circuitry 223 can be used for shifting data values stored in memory cells coupled to a particular pair of complementary data lines to the sensing circuitry 250 (e.g., sense amplifier 206) corresponding to a different pair of complementary data lines (e.g., such as a sense amplifier 206 corresponding to a left or right adjacent pair of complementary data lines. As used herein, a sense amplifier 206 corresponds to the pair of complementary data lines to which the sense amplifier is coupled when isolation transistors 221-1 and 221-2 are conducting. The SHIFT operations (right or left) do not pre-copy the Row X data value into the accumulator. Operations to shift right Row X can be summarized as follows:
Deactivate Norm and Activate Shift;
Deactivate EQ;
Open Row X;
Fire Sense Amps (after which shifted Row X data resides in the sense amps);
Activate Norm and Deactivate Shift;
Close Row X;
Precharge;
In the pseudo code above, “Deactivate Norm and Activate Shift” indicates that a NORM control signal goes low causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to not conduct (e.g., isolate the sense amplifier from the corresponding pair of complementary data lines). The SHIFT control signal goes high causing isolation transistors 221-3 and 221-4 to conduct, thereby coupling the sense amplifier 206 to the left adjacent pair of complementary data lines (e.g., on the memory array side of non-conducting isolation transistors 221-1 and 221-2 for the left adjacent pair of complementary data lines).
After the shift circuitry 223 is configured, the “Deactivate EQ,” “Open Row X,” and “Fire Sense Amps” shown in the pseudo code above indicate the same functionality as the same operations in the pseudo code for the “Copy Row X into the Accumulator” initial operation phase described above prior to pseudo code for the AND operation and OR operation. After these operations, the Row X data value for the memory cell coupled to the left adjacent pair of complementary data lines is shifted right and stored in the sense amplifier 206.
In the pseudo code above, “Activate Norm and Deactivate Shift” indicates that a NORM control signal goes high causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to conduct (e.g., coupling the sense amplifier to the corresponding pair of complementary data lines), and the SHIFT control signal goes low causing isolation transistors 221-3 and 221-4 to not conduct and isolating the sense amplifier 206 from the left adjacent pair of complementary data lines (e.g., on the memory array side of non-conducting isolation transistors 221-1 and 221-2 for the left adjacent pair of complementary data lines). Since Row X is still active, the Row X data value that has been shifted right is transferred to Row X of the corresponding pair of complementary data lines through isolation transistors 221-1 and 221-2.
After the Row X data values are shifted right to the corresponding pair of complementary data lines, the selected row (e.g., ROW X) is disabled as indicated by “Close Row X” in the pseudo code above, which can be accomplished by the access transistor turning off to decouple the selected cell from the corresponding data line. Once the selected row is closed and the memory cell is isolated from the data lines, the data lines can be precharged as indicated by the “Precharge” in the pseudo code above. A precharge of the data lines can be accomplished by an equilibrate operation, as described above. Operations to shift left Row X can be summarized as follows:
Activate Norm and Deactivate Shift;
Deactivate EQ;
Open Row X;
Fire Sense Amps (after which Row X data resides in the sense amps);
Deactivate Norm and Activate Shift;
Sense amplifier data (shifted left Row X) is transferred to Row X
Close Row X;
Precharge;
In the pseudo code above, “Activate Norm and Deactivate Shift” indicates that a NORM control signal goes high causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to conduct, and the SHIFT control signal goes low causing isolation transistors 221-3 and 221-4 to not conduct. This configuration couples the sense amplifier 206 to a corresponding pair of complementary data lines and isolates the sense amplifier from the right adjacent pair of complementary data lines.
After the shift circuitry is configured, the “Deactivate EQ,” “Open Row X,” and “Fire Sense Amps” shown in the pseudo code above indicate the same functionality as the same operations in the pseudo code for the “Copy Row X into the Accumulator” initial operation phase described above prior to pseudo code for the AND operation and OR operation. After these operations, the Row X data value for the memory cell coupled to the pair of complementary data lines corresponding to the sense circuitry 250 is stored in the sense amplifier 206.
In the pseudo code above, “Deactivate Norm and Activate Shift” indicates that a NORM control signal goes low causing isolation transistors 221-1 and 221-2 of the shift circuitry 223 to not conduct (e.g., isolate the sense amplifier from the corresponding pair of complementary data lines), and the SHIFT control signal goes high causing isolation transistors 221-3 and 221-4 to conduct coupling the sense amplifier to the left adjacent pair of complementary data lines (e.g., on the memory array side of non-conducting isolation transistors 221-1 and 221-2 for the left adjacent pair of complementary data lines. Since Row X is still active, the Row X data value that has been shifted left is transferred to Row X of the left adjacent pair of complementary data lines.
After the Row X data values are shifted left to the left adjacent pair of complementary data lines, the selected row (e.g., ROW X) is disabled as indicated by “Close Row X,” which can be accomplished by the access transistor turning off to decouple the selected cell from the corresponding data line. Once the selected row is closed and the memory cell is isolated from the data lines, the data lines can be precharged as indicated by the “Precharge” in the pseudo code above. A precharge of the data lines can be accomplished by an equilibrate operation, as described above.
The sensing circuitry 750 illustrated in
Operation of logic selection transistors 752 and 754 are similar based on the state of the TT and FT selection signals and the data values on the respective complementary sense lines at the time the ISO signal is asserted. Logic selection transistors 762 and 764 also operate in a similar manner to control the swap transistors 742. That is, to OPEN (e.g., turn on) the swap transistors 742, either the TF control signal is activated (e.g., high) with data value on the true sense line being “1,” or the FF control signal is activated (e.g., high) with the data value on the complement sense line being “1.” If either the respective control signal or the data value on the corresponding sense line (e.g., sense line to which the gate of the particular logic selection transistor is coupled) is not high, then the swap transistors 742 will not be OPENed by a particular logic selection transistor.
The PASS* control signal is not necessarily complementary to the PASS control signal. For instance, it is possible for the PASS and PASS* control signals to both be activated or both be deactivated at the same time. However, activation of both the PASS and PASS* control signals at the same time shorts the pair of complementary sense lines together, which may be a disruptive configuration to be avoided. Logical operations results for the sensing circuitry illustrated in
The logic table illustrated in
Via selective control of the pass gates 793-1 and 793-2 and the swap transistors 742, each of the three columns of the first set of two rows of the upper portion of the logic table of
The columns of the lower portion of the logic table illustrated in
As such, the sensing circuitry shown in
According to various embodiments, general computing can be enabled in a memory array core of a processor-in-memory (PIM) device such as a DRAM one transistor per memory cell (e.g., 1T1C) configuration at 6F^2 or 4F^2 memory cell sizes, for example. A potential advantage of certain example apparatuses and methods described herein can be cumulative speed that can be achieved by an entire bank of data being computed in parallel without necessarily transferring data out of the memory array (e.g., DRAM) or firing a column decode. For example, data transfer time can be reduce and/or eliminated. For example, apparatuses of the present disclosure can perform ANDs or ORs simultaneously using data values in memory cells coupled to a data line (e.g., a column of 16K memory cells).
In previous approach sensing circuits where data is moved out for logical operation processing (e.g., using 32 or 64 bit registers), fewer operations can be performed in parallel compared to the apparatus of the present disclosure. In this manner, significantly higher throughput is effectively provided in contrast to conventional configurations involving a central processing unit (CPU) discrete from the memory such that data must be transferred therebetween. An apparatus and/or methods according to the present disclosure can also use less energy/area than configurations where the CPU is discrete from the memory. Furthermore, an apparatus and/or methods of the present disclosure can improve upon the smaller energy/area advantages since the in-memory-array logical operations save energy by eliminating certain data value transfers.
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|---|---|---|---|
| 20160062733 A1 | Mar 2016 | US |
| Number | Date | Country | |
|---|---|---|---|
| 62045259 | Sep 2014 | US |
