Supports for storage elements, Supports for storage elements

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G11C5/04Supports for storage elements, Supports for storage elements

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Layout for dual in-line memory to support 128-byte cache line proce...
- Patent number 12,211,577
- Issue date Jan 28, 2025
- Tachyum Ltd.
- Radoslav Danilak
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory buffer with data scrambling and error correction
- Patent number 12,205,669
- Issue date Jan 21, 2025
- RAMBUS INC.
- Christopher Haywood
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory system with threaded transaction support
- Patent number 12,197,731
- Issue date Jan 14, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load reduced memory module
- Patent number 12,200,860
- Issue date Jan 14, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer system, memory device formed on a wafer on wafer stack in...
- Patent number 12,189,954
- Issue date Jan 7, 2025
- WHALECHIP CO., LTD.
- Kun-Hua Tsai
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
DRAM retention test method for dynamic error correction
- Patent number 12,190,974
- Issue date Jan 7, 2025
- RAMBUS INC.
- Ely Tsern
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device with a three-dimensional stacked memory...
- Patent number 12,185,538
- Issue date Dec 31, 2024
- Kioxia Corporation
- Tomoo Hishida
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor package
- Patent number 12,170,265
- Issue date Dec 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chao-I Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Buffer configurations for communications between memory dies and a...
- Patent number 12,170,127
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Sujeet V. Ayyapureddi
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 12,154,649
- Issue date Nov 26, 2024
- Kioxia Corporation
- Masato Sugita
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-volatile memory module architecture to support memory error cor...
- Patent number 12,153,827
- Issue date Nov 26, 2024
- George Pax
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High capacity memory system using standard controller component
- Patent number 12,148,462
- Issue date Nov 19, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Training and operations with a double buffered memory topology
- Patent number 12,141,081
- Issue date Nov 12, 2024
- RAMBUS INC.
- Chi-Ming Yeung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Accessing error statistics from DRAM memories having integrated err...
- Patent number 12,141,030
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Siva Srinivas Kothamasu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for providing compression attached memory module...
- Patent number 12,142,341
- Issue date Nov 12, 2024
- Dell Products L.P.
- Arnold Thomas Schnell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device comprising programmable command-and-address and/or da...
- Patent number 12,142,348
- Issue date Nov 12, 2024
- RAMBUS INC.
- Ian Shaeffer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory module with local synchronization and method of operation
- Patent number 12,135,644
- Issue date Nov 5, 2024
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module with reduced read/write turnaround overhead
- Patent number 12,130,757
- Issue date Oct 29, 2024
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory module, memory system, and operation method of memory contro...
- Patent number 12,132,501
- Issue date Oct 29, 2024
- Samsung Electronics Co., Ltd.
- Wonjae Shin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modular memory devices
- Patent number 12,127,361
- Issue date Oct 22, 2024
- MONTAGE ELECTRONICS (SHANGHAI) CO
- Christopher Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
Double stub transmission line for suppression of harmonics
- Patent number 12,101,875
- Issue date Sep 24, 2024
- Hewlett Packard Enterprise Development LP
- David P. Kopp
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory circuit and cache circuit configuration
- Patent number 12,093,176
- Issue date Sep 17, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Hsien-Hsin Sean Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with modular design and memory system comprising the...
- Patent number 12,080,369
- Issue date Sep 3, 2024
- MONTAGE ELECTRONICS (SHANGHAI) CO
- Christopher Cox
- G11 - INFORMATION STORAGE
Information Patent Grant
High-throughput low-latency hybrid memory module
- Patent number 12,079,486
- Issue date Sep 3, 2024
- RAMBUS INC.
- Aws Shallal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command bus in memory
- Patent number 12,067,276
- Issue date Aug 20, 2024
- Frank F. Ross
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer circuit with data bit inversion
- Patent number 12,067,285
- Issue date Aug 20, 2024
- RAMBUS INC.
- Scott C. Best
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Module board and memory module including the same
- Patent number 12,063,736
- Issue date Aug 13, 2024
- Samsung Electronics Co., Ltd.
- Wonseop Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Compute-in-memory device and method
- Patent number 12,063,786
- Issue date Aug 13, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd
- Chieh Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory system and label component
- Patent number 12,058,843
- Issue date Aug 6, 2024
- Kioxia Corporation
- Yoshiaki Yoshihara
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor memory device
- Patent number 12,048,110
- Issue date Jul 23, 2024
- Kioxia Corporation
- Akihisa Fujimoto
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
On-Die Termination of Address and Command Signals
- Publication number 20250037746
- Publication date Jan 30, 2025
- Rambus Inc.
- Ian Shaeffer
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING
- Publication number 20250028660
- Publication date Jan 23, 2025
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE
- Publication number 20250021235
- Publication date Jan 16, 2025
- Rambus Inc.
- Aws Shallal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY
- Publication number 20240420793
- Publication date Dec 19, 2024
- Rambus Inc.
- Scott C. Best
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE CAPABLE OF REDUCING POWER CONSUMPTION AND SEMICONDUCT...
- Publication number 20240402920
- Publication date Dec 5, 2024
- SK HYNIX INC.
- Jung Hyun KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-DIE MEMORY DEVICE
- Publication number 20240404580
- Publication date Dec 5, 2024
- Rambus Inc.
- Scott C. Best
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS
- Publication number 20240394177
- Publication date Nov 28, 2024
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD FOR PROVIDING COMPRESSION ATTACHED MEMORY MODULE...
- Publication number 20240379133
- Publication date Nov 14, 2024
- Dell Products L.P.
- Arnold Thomas Schnell
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE MEMORY CARD CONNECTOR
- Publication number 20240371411
- Publication date Nov 7, 2024
- Amphenol Commercial Products (ChengDu) Co., LTD.
- Kui Yang
- G11 - INFORMATION STORAGE
Information Patent Application
COMPUTE-IN-MEMORY DEVICE AND METHOD
- Publication number 20240365556
- Publication date Oct 31, 2024
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Chieh Lee
- G11 - INFORMATION STORAGE
Information Patent Application
ADJUSTMENT OF PROGRAM VERIFY TARGETS CORRESPONDING TO A LAST PROGRA...
- Publication number 20240331780
- Publication date Oct 3, 2024
- Micron Technology, Inc.
- Bruce A. Liikanen
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE
- Publication number 20240334631
- Publication date Oct 3, 2024
- KIOXIA Corporation
- Akihisa FUJIMOTO
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES
- Publication number 20240331757
- Publication date Oct 3, 2024
- Micron Technology, Inc.
- Hari Giduturi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY MODULE REGISTER ACCESS
- Publication number 20240320080
- Publication date Sep 26, 2024
- Rambus Inc.
- Thomas J. Giovannini
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTE...
- Publication number 20240321842
- Publication date Sep 26, 2024
- Samsung Electronics Co., Ltd.
- Tong-Suk Kim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY MODULES INCLUDING A MIRRORING CIRCUIT AND METHODS OF OPERATI...
- Publication number 20240312491
- Publication date Sep 19, 2024
- Samsung Electronics Co., Ltd.
- GYUCHAE LEE
- G11 - INFORMATION STORAGE
Information Patent Application
LOAD REDUCED MEMORY MODULE
- Publication number 20240276639
- Publication date Aug 15, 2024
- Rambus Inc.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIGNAL TIMING ALIGNMENT BASED ON A COMMON DATA STROBE IN MEMORY DEV...
- Publication number 20240265961
- Publication date Aug 8, 2024
- III Holdings 2, LLC
- Michael C. Stephens
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE AND SYSTEM SUPPORTING PARALLEL AND SERIAL ACCESS MODES
- Publication number 20240257846
- Publication date Aug 1, 2024
- Rambus Inc.
- Scott C. Best
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFER...
- Publication number 20240258273
- Publication date Aug 1, 2024
- Micron Technology, Inc.
- Blaine J. Thurgood
- G11 - INFORMATION STORAGE
Information Patent Application
Optimize Information Requests to a Memory System
- Publication number 20240248641
- Publication date Jul 25, 2024
- Micron Technology, Inc.
- Trevor Conrad Meyerowitz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DUAL IN-LINE MEMORY MODULE RETAINER
- Publication number 20240242740
- Publication date Jul 18, 2024
- Intel Corporation
- Phil GENG
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY MODULE PROVIDING DISTINCT SIGNALING INTERFACES VIA AN OPEN-D...
- Publication number 20240232105
- Publication date Jul 11, 2024
- Netlist, Inc.
- Hyun Lee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Multi-Mode Memory Module with Data Handlers
- Publication number 20240221852
- Publication date Jul 4, 2024
- Netlist, Inc.
- Hyun Lee
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS WITH DATA-RATE-BASED VOLTAGE CONTROL MECHANISM AND METHOD...
- Publication number 20240221813
- Publication date Jul 4, 2024
- Lodestar Licensing Group LLC
- Gary L. Howe
- G11 - INFORMATION STORAGE
Information Patent Application
STACKED SEMICONDUCTOR DEVICE
- Publication number 20240203483
- Publication date Jun 20, 2024
- Rambus Inc.
- Frederick A. Ware
- G11 - INFORMATION STORAGE
Information Patent Application
Remote Memory Architectures Enabled by Monolithic In-Package Optica...
- Publication number 20240187110
- Publication date Jun 6, 2024
- Ayar Labs, Inc.
- Roy Edward Meade
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHODS FOR OPTIMIZING SEMICONDUCTOR DEVICE PLACEMENT ON A SUBSTRAT...
- Publication number 20240177743
- Publication date May 30, 2024
- Micron Technology, Inc.
- James S. Rehmeyer
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR PACKAGES WITH PASS-THROUGH CLOCK TRACES AND ASSOCIATE...
- Publication number 20240178193
- Publication date May 30, 2024
- Lodestar Licensing Group LLC
- Thomas H. Kinsley
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory System Having Combined High Density, Low Bandwidth and Low D...
- Publication number 20240161804
- Publication date May 16, 2024
- Apple Inc.
- Sukalpa Biswas
- G11 - INFORMATION STORAGE

Supports for storage elements, Supports for storage elements

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Layout for dual in-line memory to support 128-byte cache line proce...

Memory buffer with data scrambling and error correction

Memory system with threaded transaction support

Load reduced memory module

Computer system, memory device formed on a wafer on wafer stack in...

DRAM retention test method for dynamic error correction

Semiconductor memory device with a three-dimensional stacked memory...

Semiconductor package

Buffer configurations for communications between memory dies and a...

Semiconductor device

Non-volatile memory module architecture to support memory error cor...

High capacity memory system using standard controller component

Training and operations with a double buffered memory topology

Accessing error statistics from DRAM memories having integrated err...

System and method for providing compression attached memory module...

Memory device comprising programmable command-and-address and/or da...

Memory module with local synchronization and method of operation

Memory module with reduced read/write turnaround overhead

Memory module, memory system, and operation method of memory contro...

Modular memory devices

Double stub transmission line for suppression of harmonics

Memory circuit and cache circuit configuration

Memory device with modular design and memory system comprising the...

High-throughput low-latency hybrid memory module

Command bus in memory

Buffer circuit with data bit inversion

Module board and memory module including the same

Compute-in-memory device and method

Memory system and label component

Semiconductor memory device

Patents Applicationslast 30 patents

On-Die Termination of Address and Command Signals

MEMORY MODULE WITH TIMING-CONTROLLED DATA BUFFERING

HIGH-THROUGHPUT LOW-LATENCY HYBRID MEMORY MODULE

BUFFER CIRCUIT WITH ADAPTIVE REPAIR CAPABILITY

MEMORY MODULE CAPABLE OF REDUCING POWER CONSUMPTION AND SEMICONDUCT...

MULTI-DIE MEMORY DEVICE

MEMORY MODULE WITH DISTRIBUTED DATA BUFFERS

SYSTEM AND METHOD FOR PROVIDING COMPRESSION ATTACHED MEMORY MODULE...

CONFIGURABLE MEMORY CARD CONNECTOR

COMPUTE-IN-MEMORY DEVICE AND METHOD

ADJUSTMENT OF PROGRAM VERIFY TARGETS CORRESPONDING TO A LAST PROGRA...

SEMICONDUCTOR MEMORY DEVICE

INTRA-PACKAGE MEMORY DIE COMMUNICATION STRUCTURES

MEMORY MODULE REGISTER ACCESS

PACKAGE-ON-PACKAGE (POP) SEMICONDUCTOR PACKAGE AND ELECTRONIC SYSTE...

MEMORY MODULES INCLUDING A MIRRORING CIRCUIT AND METHODS OF OPERATI...

LOAD REDUCED MEMORY MODULE

SIGNAL TIMING ALIGNMENT BASED ON A COMMON DATA STROBE IN MEMORY DEV...

MEMORY MODULE AND SYSTEM SUPPORTING PARALLEL AND SERIAL ACCESS MODES

SEMICONDUCTOR DEVICE ASSEMBLIES INCLUDING MULTIPLE STACKS OF DIFFER...

Optimize Information Requests to a Memory System

DUAL IN-LINE MEMORY MODULE RETAINER

MEMORY MODULE PROVIDING DISTINCT SIGNALING INTERFACES VIA AN OPEN-D...

Multi-Mode Memory Module with Data Handlers

APPARATUS WITH DATA-RATE-BASED VOLTAGE CONTROL MECHANISM AND METHOD...

STACKED SEMICONDUCTOR DEVICE

Remote Memory Architectures Enabled by Monolithic In-Package Optica...

METHODS FOR OPTIMIZING SEMICONDUCTOR DEVICE PLACEMENT ON A SUBSTRAT...

SEMICONDUCTOR PACKAGES WITH PASS-THROUGH CLOCK TRACES AND ASSOCIATE...

Memory System Having Combined High Density, Low Bandwidth and Low D...