Timing analysis

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CPC
G06F17/5031

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F17/00Digital computing or data processing equipment or methods, specially adapted for specific functions

Current Industry

G06F17/5031Timing analysis

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Bandwidth test in networking System-on-Chip verification
- Patent number 10,664,566
- Issue date May 26, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Latency test in networking system-on-chip verification
- Patent number 10,657,217
- Issue date May 19, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying circuits based on timing reports for critical paths
- Patent number 10,650,113
- Issue date May 12, 2020
- International Business Machines Corporation
- Rina Kipnis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Glitch detection at clock domain crossing
- Patent number 10,635,767
- Issue date Apr 28, 2020
- Mentor Graphics Corporation
- Sulabh Kumar Khare
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flow control in networking system-on-chip verification
- Patent number 10,628,548
- Issue date Apr 21, 2020
- Mentor Graphics Corporation
- Suresh Krishnamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock network analysis using harmonic balance
- Patent number 10,620,659
- Issue date Apr 14, 2020
- International Business Machines Corporation
- Peter Feldmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing analysis for electronic design automation of parallel multi-...
- Patent number 10,614,182
- Issue date Apr 7, 2020
- Movellus Circuits, Inc.
- Jeffrey Fredenburg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor process and performance sensor
- Patent number 10,614,184
- Issue date Apr 7, 2020
- ATLAZO, INC.
- Shahin Solki
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing clock power consumption of a computer processor
- Patent number 10,614,183
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Erez Barak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selection of corners and/or margins using statistical static timing...
- Patent number 10,606,970
- Issue date Mar 31, 2020
- International Business Machines Corporation
- Eric A. Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit design analyzer
- Patent number 10,599,792
- Issue date Mar 24, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reducing clock power consumption of a computer processor
- Patent number 10,585,995
- Issue date Mar 10, 2020
- International Business Machines Corporation
- Erez Barak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Die resistance-capacitance extraction and validation
- Patent number 10,585,996
- Issue date Mar 10, 2020
- Seagate Technology LLC
- Nitin Kumar Chhabra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Flip flop of a digital electronic chip
- Patent number 10,585,143
- Issue date Mar 10, 2020
- STMicroelectronics International N.V.
- Pascal Urard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementation of user logic in a field progr...
- Patent number 10,579,758
- Issue date Mar 3, 2020
- Wipro Limited
- Kodavalla Vijay Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High-level synthesis (HLS) method and apparatus to specify pipeline...
- Patent number 10,579,762
- Issue date Mar 3, 2020
- LegUp Computing Inc.
- Jongsok Choi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Estimating timing convergence using assertion comparisons
- Patent number 10,572,613
- Issue date Feb 25, 2020
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Single simulation-based structure function mapping
- Patent number 10,571,514
- Issue date Feb 25, 2020
- Mentor Graphics Corporation
- Byron Blackmore
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Back-pressure in virtual machine interface
- Patent number 10,572,623
- Issue date Feb 25, 2020
- Mentor Graphics Corporation
- Ankit Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pessimism reduction in cross-talk noise determination used in integ...
- Patent number 10,565,336
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Jason D. Morsey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit simulation using a recording of a reference execution
- Patent number 10,565,337
- Issue date Feb 18, 2020
- OPTIMA DESIGN AUTOMATION LTD
- Jamil Raja Mazzawi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Targeted delay optimization through programmable clock delays
- Patent number 10,565,334
- Issue date Feb 18, 2020
- Xilinx, Inc.
- Ruibing Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Modifying a circuit design
- Patent number 10,568,203
- Issue date Feb 18, 2020
- International Business Machines Corporation
- Ofer Geva
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase algebra for virtual clock and mode extraction in hierarchical...
- Patent number 10,558,782
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory element graph-based placement in integrated circuit design
- Patent number 10,558,775
- Issue date Feb 11, 2020
- International Business Machines Corporation
- Myung-Chul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Glitch-aware phase algebra for clock analysis
- Patent number 10,552,559
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hybrid out of context hierarchical design flow for hierarchical tim...
- Patent number 10,552,561
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Nitin Srimal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Conditional phase algebra for clock analysis
- Patent number 10,552,558
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Gabor Drasny
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Leverage cycle stealing within optimization flows
- Patent number 10,552,562
- Issue date Feb 4, 2020
- International Business Machines Corporation
- Nathaniel D. Hieter
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hard error simulation and usage thereof
- Patent number 10,546,086
- Issue date Jan 28, 2020
- OPTIMA DESIGN AUTOMATION LTD
- Jamil R. Mazzawi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SUPERCONDUCTING CIRCUIT WITH VIRTUAL TIMING ELEMENTS AND RELATED ME...
- Publication number 20210064718
- Publication date Mar 4, 2021
- Microsoft Technology Licensing, LLC
- Janet L. Schneider
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FEEDBACK-AWARE SLACK STEALING ACROSS TRANSPARENT LATCHES EMPOWERING...
- Publication number 20210011980
- Publication date Jan 14, 2021
- International Business Machines Corporation
- Chaitanya Ravindra Peddawad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL CLOCK TREE CONSTRUCTION BASED ON CONSTRAINTS
- Publication number 20200401179
- Publication date Dec 24, 2020
- Samsung Electronics Co., Ltd.
- Sridhar SUBRAMANIAM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EMBEDDED FPGA TIMING SIGN-OFF
- Publication number 20200311219
- Publication date Oct 1, 2020
- Achronix Semiconductor Corporation
- Namit Varma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHARACTERIZATION OF SPATIAL CORRELATION IN INTEGRATED CIRCUIT DEVEL...
- Publication number 20200257769
- Publication date Aug 13, 2020
- International Business Machines Corporation
- Ning Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VERIFICATION APPARATUS AND METHOD FOR VERIFYING OPERATION OF INTEGR...
- Publication number 20200257332
- Publication date Aug 13, 2020
- Toshiba Memory Corporation
- Kazunao SAWADA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD OF OPERATING TIMING ANALYSIS CONSIDERING MULTI...
- Publication number 20200242206
- Publication date Jul 30, 2020
- Samsung Electronics Co., Ltd.
- MOON SU KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIABLE ACCURACY INCREMENTAL TIMING ANALYSIS
- Publication number 20200242205
- Publication date Jul 30, 2020
- International Business Machines Corporation
- Jeffrey Hemmett
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PREDICTIVE ON-CHIP VOLTAGE SIMULATION TO DETECT NEAR-FUTURE UNDER V...
- Publication number 20200201407
- Publication date Jun 25, 2020
- International Business Machines Corporation
- Thomas Strach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for determining IC voltage and method for finding relation b...
- Publication number 20200151295
- Publication date May 14, 2020
- REALTEK SEMICONDUCTOR CORPORATION
- YING-CHIEH CHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TESTING SYSTEM AND TESTING METHOD
- Publication number 20200151299
- Publication date May 14, 2020
- Global Unichip (Nanjing) Ltd.
- Shih-Hsin Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR GENERATING AGING MODEL AND MANUFACTURING SEMICONDUCTOR C...
- Publication number 20200151294
- Publication date May 14, 2020
- Samsung Electronics Co., Ltd.
- Moon Su KIM
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ARCHITECTURE FOR ORDERED WRITE OF DATA COLLECTED IN PARALLEL
- Publication number 20200134115
- Publication date Apr 30, 2020
- International Business Machines Corporation
- Maurya Prabhat Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT FIN LAYOUT METHOD, SYSTEM, AND STRUCTURE
- Publication number 20200134122
- Publication date Apr 30, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- Po-Hsiang HUANG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPERPOSITION OF CANONICAL TIMING VALUE REPRESENTATIONS IN STATISTI...
- Publication number 20200134114
- Publication date Apr 30, 2020
- International Business Machines Corporation
- Eric Foreman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPLICATION INTERFACE GOVERNANCE PLATFORM TO HARMONIZE, VALIDATE, A...
- Publication number 20200133744
- Publication date Apr 30, 2020
- Stoplight, Inc.
- Marc MacLeod
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CAPACITANCE EXTRACTION FOR FLOATING METAL IN INTEGRATED CIRCUIT
- Publication number 20200134129
- Publication date Apr 30, 2020
- International Business Machines Corporation
- David J. Widiger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT DESIGN WITH OPTIMIZED TIMING CONSTRAINT CONFIGUR...
- Publication number 20200104452
- Publication date Apr 2, 2020
- International Business Machines Corporation
- OFER GEVA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METASTABILITY INSERTION USING THE X-STATE
- Publication number 20200097626
- Publication date Mar 26, 2020
- ADVANCED MICRO DEVICES, INC.
- Shalini Sodagam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Elmore Delay Time (EDT)-Based Resistance Model
- Publication number 20200089830
- Publication date Mar 19, 2020
- Synopsys, Inc.
- Ralph Benhart IVERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BOUNDARY ASSERTION-BASED POWER RECOVERY IN INTEGRATED CIRCUIT DESIGN
- Publication number 20200089828
- Publication date Mar 19, 2020
- International Business Machines Corporation
- Alexander J. Suess
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING PHOTONIC EMISSION TO DEVELOP ELECTROMAGNETIC EMISSION MODELS
- Publication number 20200082518
- Publication date Mar 12, 2020
- International Business Machines Corporation
- Andrea Bahgat Shehata
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT TESTING AND MANUFACTURE USING MULTIPLE TIMING LIBRARIES
- Publication number 20200074030
- Publication date Mar 5, 2020
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Ravi Babu PITTU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CO-WOUND RESISTOR
- Publication number 20200051718
- Publication date Feb 13, 2020
- QUALCOMM Incorporated
- Haitao CHENG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR OPTIMIZING CIRCUIT PERFORMANCE VIA CONFIGURABLE CLOCK S...
- Publication number 20200042033
- Publication date Feb 6, 2020
- Altera Corporation
- Mark Bourgeault
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PESSIMISM IN STATIC TIMING ANALYSIS
- Publication number 20200026812
- Publication date Jan 23, 2020
- Synopsys, Inc.
- Chunyang Feng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REFLECTION-CANCELING PACKAGE TRACE DESIGN
- Publication number 20200020673
- Publication date Jan 16, 2020
- CREDO TECHNOLOGY GROUP LIMITED
- Xike LIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR MANUFACTURING INTEGRATED CIRCUIT WITH AID OF PATTERN BAS...
- Publication number 20200019663
- Publication date Jan 16, 2020
- Taiwan Semiconductor Manufacturing company Ltd.
- RAVI BABU PITTU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CIRCUIT MODULE FOR MODELLING A DIGITAL CIRCUIT AND SIMULATION DEVIC...
- Publication number 20200012757
- Publication date Jan 9, 2020
- Seuk SON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR ADAPTIVE VOLTAGE SCALING TO ELIMINATE DELA...
- Publication number 20190384868
- Publication date Dec 19, 2019
- Realtek Semiconductor Corp.
- Mei-Li Yu
- G06 - COMPUTING CALCULATING COUNTING

Timing analysis

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Bandwidth test in networking System-on-Chip verification

Latency test in networking system-on-chip verification

Modifying circuits based on timing reports for critical paths

Glitch detection at clock domain crossing

Flow control in networking system-on-chip verification

Clock network analysis using harmonic balance

Timing analysis for electronic design automation of parallel multi-...

Semiconductor process and performance sensor

Reducing clock power consumption of a computer processor

Selection of corners and/or margins using statistical static timing...

Circuit design analyzer

Reducing clock power consumption of a computer processor

Die resistance-capacitance extraction and validation

Flip flop of a digital electronic chip

Method and system for implementation of user logic in a field progr...

High-level synthesis (HLS) method and apparatus to specify pipeline...

Estimating timing convergence using assertion comparisons

Single simulation-based structure function mapping

Back-pressure in virtual machine interface

Pessimism reduction in cross-talk noise determination used in integ...

Circuit simulation using a recording of a reference execution

Targeted delay optimization through programmable clock delays

Modifying a circuit design

Phase algebra for virtual clock and mode extraction in hierarchical...

Memory element graph-based placement in integrated circuit design

Glitch-aware phase algebra for clock analysis

Hybrid out of context hierarchical design flow for hierarchical tim...

Conditional phase algebra for clock analysis

Leverage cycle stealing within optimization flows

Hard error simulation and usage thereof

Patents Applicationslast 30 patents

SUPERCONDUCTING CIRCUIT WITH VIRTUAL TIMING ELEMENTS AND RELATED ME...

FEEDBACK-AWARE SLACK STEALING ACROSS TRANSPARENT LATCHES EMPOWERING...

HIERARCHICAL CLOCK TREE CONSTRUCTION BASED ON CONSTRAINTS

EMBEDDED FPGA TIMING SIGN-OFF

CHARACTERIZATION OF SPATIAL CORRELATION IN INTEGRATED CIRCUIT DEVEL...

VERIFICATION APPARATUS AND METHOD FOR VERIFYING OPERATION OF INTEGR...

APPARATUS AND METHOD OF OPERATING TIMING ANALYSIS CONSIDERING MULTI...

VARIABLE ACCURACY INCREMENTAL TIMING ANALYSIS

PREDICTIVE ON-CHIP VOLTAGE SIMULATION TO DETECT NEAR-FUTURE UNDER V...

Method for determining IC voltage and method for finding relation b...

TESTING SYSTEM AND TESTING METHOD

METHOD FOR GENERATING AGING MODEL AND MANUFACTURING SEMICONDUCTOR C...

ARCHITECTURE FOR ORDERED WRITE OF DATA COLLECTED IN PARALLEL

INTEGRATED CIRCUIT FIN LAYOUT METHOD, SYSTEM, AND STRUCTURE

SUPERPOSITION OF CANONICAL TIMING VALUE REPRESENTATIONS IN STATISTI...

APPLICATION INTERFACE GOVERNANCE PLATFORM TO HARMONIZE, VALIDATE, A...

CAPACITANCE EXTRACTION FOR FLOATING METAL IN INTEGRATED CIRCUIT

INTEGRATED CIRCUIT DESIGN WITH OPTIMIZED TIMING CONSTRAINT CONFIGUR...

METASTABILITY INSERTION USING THE X-STATE

Elmore Delay Time (EDT)-Based Resistance Model

BOUNDARY ASSERTION-BASED POWER RECOVERY IN INTEGRATED CIRCUIT DESIGN

USING PHOTONIC EMISSION TO DEVELOP ELECTROMAGNETIC EMISSION MODELS

CIRCUIT TESTING AND MANUFACTURE USING MULTIPLE TIMING LIBRARIES

CO-WOUND RESISTOR

METHODS FOR OPTIMIZING CIRCUIT PERFORMANCE VIA CONFIGURABLE CLOCK S...

PESSIMISM IN STATIC TIMING ANALYSIS

REFLECTION-CANCELING PACKAGE TRACE DESIGN

METHOD FOR MANUFACTURING INTEGRATED CIRCUIT WITH AID OF PATTERN BAS...

CIRCUIT MODULE FOR MODELLING A DIGITAL CIRCUIT AND SIMULATION DEVIC...

METHOD AND APPARATUS FOR ADAPTIVE VOLTAGE SCALING TO ELIMINATE DELA...