Timing circuits

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CPC
G11C11/4076

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Parent Industries

GPHYSICS G11Information storage G11CSTATIC STORES G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements Storage elements therefor

Current Industry

G11C11/4076Timing circuits

Industries

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Patents Grantslast 30 patents

Information Patent Grant
Method and system for refresh of memory devices
- Patent number 12,322,432
- Issue date Jun 3, 2025
- Taiwan Semiconductor Manufacturing Co., Ltd
- Hiroki Noguchi
- G11 - INFORMATION STORAGE
Information Patent Grant
Word line delay interlock circuit for write operation
- Patent number 12,315,552
- Issue date May 27, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd
- Atul Katoch
- G11 - INFORMATION STORAGE
Information Patent Grant
Read clock start and stop for synchronous memories
- Patent number 12,315,551
- Issue date May 27, 2025
- Advanced Micro Devices, Inc.
- Aaron John Nygren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable row hammer mitigation
- Patent number 12,315,553
- Issue date May 27, 2025
- Micron Technology, Inc.
- Edmund J. Gieske
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory controller operable in data loop-back mode
- Patent number 12,314,113
- Issue date May 27, 2025
- RAMBUS INC.
- Frederick A. Ware
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory activation timing management
- Patent number 12,307,128
- Issue date May 20, 2025
- Micron Technology, Inc.
- Angelo Visconti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo-static random access memory
- Patent number 12,308,066
- Issue date May 20, 2025
- Winbond Electronics Corp.
- Hitoshi Ikeda
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for determining an interface connection status
- Patent number 12,308,080
- Issue date May 20, 2025
- Micron Technology, Inc.
- Melissa I. Uribe
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal skew in source-synchronous system
- Patent number 12,300,303
- Issue date May 13, 2025
- RAMBUS INC.
- Shahram Nikoukary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for signal transmission, circuit and memory
- Patent number 12,300,348
- Issue date May 13, 2025
- CHANGXIN MEMORY TECHNOLOGIES, INC.
- Kiho Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device and memory system
- Patent number 12,300,353
- Issue date May 13, 2025
- Samsung Electronics Co., Ltd.
- Seung-Jun Shin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Bank-level self-refresh
- Patent number 12,300,300
- Issue date May 13, 2025
- Micron Technology, Inc.
- John Christopher Sancon
- G11 - INFORMATION STORAGE
Information Patent Grant
Convertible memory device
- Patent number 12,293,782
- Issue date May 6, 2025
- SK Hynix Inc.
- Gyeong Cheol Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit module with reliable margin configuration
- Patent number 12,293,785
- Issue date May 6, 2025
- M31 Technology Corporation
- Li-Wei Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient and low power reference voltage mixing
- Patent number 12,288,581
- Issue date Apr 29, 2025
- Advanced Micro Devices, Inc.
- Aaron D Willey
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase correction circuit, and clock buffer and semiconductor appara...
- Patent number 12,289,110
- Issue date Apr 29, 2025
- SK hynix Inc.
- Ji Hyo Kang
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-static random-access memory and reading method thereof
- Patent number 12,283,309
- Issue date Apr 22, 2025
- Winbond Electronics Corp.
- Junichi Sasaki
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus with data-rate-based voltage control mechanism and method...
- Patent number 12,277,963
- Issue date Apr 15, 2025
- Gary L. Howe
- G11 - INFORMATION STORAGE
Information Patent Grant
Reading from a mode register having different read and write timing
- Patent number RE50373
- Issue date Apr 8, 2025
- Sony Group Corporation
- Christopher E. Cox
Information Patent Grant
Method of generating a multi-level signal using selective equalizat...
- Patent number 12,272,396
- Issue date Apr 8, 2025
- Samsung Electronics Co., Ltd.
- Junyoung Park
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write operation assist circuit
- Patent number 12,266,399
- Issue date Apr 1, 2025
- Spreadtrum Communications (Shanghai) Co., Ltd.
- Yiqi She
- G11 - INFORMATION STORAGE
Information Patent Grant
Input data pre-alignment circuit capable of performing a first-in f...
- Patent number 12,266,396
- Issue date Apr 1, 2025
- Fujian Jinhua Integrated Circuit Co., Ltd.
- Minho Park
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus including parallel pipelines and methods of manufacturing...
- Patent number 12,265,485
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Kallol Mazumder
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for enhanced memory context restore
- Patent number 12,265,467
- Issue date Apr 1, 2025
- Advanced Micro Devices, Inc.
- Anwar Parvez Kashem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power supply circuit, memory, testing device, memory system, and el...
- Patent number 12,254,917
- Issue date Mar 18, 2025
- Yangtze Memory Technologies Co., Ltd.
- Yu Wang
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus with non-linear delay variations for scheduling memory re...
- Patent number 12,249,364
- Issue date Mar 11, 2025
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G11 - INFORMATION STORAGE
Information Patent Grant
Automated voltage demarcation (VDM) adjustment for memory device
- Patent number 12,243,577
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- Yi-Min Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Read clock start and stop for synchronous memories
- Patent number 12,243,578
- Issue date Mar 4, 2025
- Advanced Micro Devices, Inc.
- Aaron John Nygren
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Semiconductor device having duty-cycle corrector
- Patent number 12,244,316
- Issue date Mar 4, 2025
- Micron Technology, Inc.
- Yasuo Satoh
- G11 - INFORMATION STORAGE
Information Patent Grant
Management of dynamic read voltage sequences in a memory subsystem
- Patent number 12,237,003
- Issue date Feb 25, 2025
- Micron Technology, Inc.
- Yu-Chung Lien
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
APPARATUSES, SYSTEMS, AND METHODS FOR ODT PULSE WIDTH DURATION DETE...
- Publication number 20250182816
- Publication date Jun 5, 2025
- Micron Technology, Inc.
- Yukimi Morimoto
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORYS, OPERATION METHODS THEREOF AND MEMORY SYSTEMS
- Publication number 20250182815
- Publication date Jun 5, 2025
- Yangtze Memory Technologies Co., Ltd.
- Ling DING
- G11 - INFORMATION STORAGE
Information Patent Application
COMMAND TIMING CONTROL CIRCUIT AND MEMORY
- Publication number 20250182812
- Publication date Jun 5, 2025
- CXMT Corporation
- Wenxue DU
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CIRCUIT AND METHOD OF OPERATING SAME
- Publication number 20250182818
- Publication date Jun 5, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Atul KATOCH
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS WITH NON-LINEAR REFRESH MECHANISM AND METHODS FOR OPERATI...
- Publication number 20250182810
- Publication date Jun 5, 2025
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G11 - INFORMATION STORAGE
Information Patent Application
OFFSET CALIBRATION METHOD AND APPARATUS FOR HIGH BANDWIDTH MEMORY 3...
- Publication number 20250182811
- Publication date Jun 5, 2025
- SKYECHIP SDN BHD
- Tze Jian CHOW
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE AND SYSTEM, AND DECODING CIRCUIT
- Publication number 20250174267
- Publication date May 29, 2025
- Yangtze Memory Technologies Co., Ltd.
- Xuesong SHEN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES AND OPERATING METHODS THEREOF, MEMORY SYSTEMS, AND S...
- Publication number 20250174268
- Publication date May 29, 2025
- Yangtze Memory Technologies Co., Ltd.
- Chuyan Hu
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE, OPERATION METHOD, AND MEMORY SYSTEM
- Publication number 20250166691
- Publication date May 22, 2025
- Yangtze Memory Technologies Co., Ltd.
- Yong FU
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGEMENT OF DYNAMIC READ VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM
- Publication number 20250166696
- Publication date May 22, 2025
- Micron Technology, Inc.
- Yu-Chung Lien
- G11 - INFORMATION STORAGE
Information Patent Application
GAIN-CELL RANDOM ACCESS MEMORY WITH ENHANCED RETENTION
- Publication number 20250166695
- Publication date May 22, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Wei Ting HSIEH
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE CAPABLE OF ADJUSTING CLOCK SIGNAL BASED ON OPERATING...
- Publication number 20250166690
- Publication date May 22, 2025
- Lodestar Licensing Group LLC
- Randon K. Richards
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE PERFORMING LOOPBACK OPERATION
- Publication number 20250157526
- Publication date May 15, 2025
- Micron Technology, Inc.
- Yuichiro Sato
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICES HAVING EFFICIENT SERIALIZERS THEREIN F...
- Publication number 20250157513
- Publication date May 15, 2025
- Samsung Electronics Co., Ltd.
- Sanguk Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION
- Publication number 20250157503
- Publication date May 15, 2025
- Rambus Inc.
- James E. Harris
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICES RELATED TO THE GENERATION OF A COMMAND
- Publication number 20250157522
- Publication date May 15, 2025
- SK HYNIX INC.
- Jung Taek YOU
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME
- Publication number 20250157523
- Publication date May 15, 2025
- Samsung Electronics Co., Ltd.
- Kiheung Kim
- G11 - INFORMATION STORAGE
Information Patent Application
DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICE, MEMORY BANK OF DRAM DEV...
- Publication number 20250157525
- Publication date May 15, 2025
- WINBOND ELECTRONICS CORP.
- Ki-Myung Kyung
- G11 - INFORMATION STORAGE
Information Patent Application
AUTOMATED VOLTAGE DEMARCATION (VDM) ADJUSTMENT FOR MEMORY DEVICE
- Publication number 20250149079
- Publication date May 8, 2025
- Micron Technology, Inc.
- Yi-Min Lin
- G11 - INFORMATION STORAGE
Information Patent Application
IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IN-MEMORY COMPUTING METHOD
- Publication number 20250149083
- Publication date May 8, 2025
- Macronix International Co., Ltd.
- Yu-Yu LIN
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR REDUCED POWER COMMAND SHIFTER
- Publication number 20250140304
- Publication date May 1, 2025
- Micron Technology, Inc.
- Yukimi Morimoto
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE PERFORMING REPLICA ROUTING
- Publication number 20250140303
- Publication date May 1, 2025
- Micron Technology, Inc.
- Honoka Enomoto
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUSES AND METHODS FOR INPUT RECEIVER CIRCUITS AND RECEIVER MA...
- Publication number 20250140305
- Publication date May 1, 2025
- Lodestar Licensing Group LLC
- Dean D. Gans
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAYOUT FOR DUAL IN-LINE MEMORY TO SUPPORT 128-BYTE CACHE LINE PROCE...
- Publication number 20250131947
- Publication date Apr 24, 2025
- TACHYUM LTD.
- Radoslav DANILAK
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY SYSTEM AND RECEIVER
- Publication number 20250124967
- Publication date Apr 17, 2025
- NANYA TECHNOLOGY CORPORATION
- Wu-Der YANG
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING COMPLEMENTARY DELA...
- Publication number 20250124968
- Publication date Apr 17, 2025
- SK HYNIX INC.
- Jae KWON
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROL UNIT OF MEMORY AND METHOD OF CONTROLLING MEMORY
- Publication number 20250124972
- Publication date Apr 17, 2025
- NANYA TECHNOLOGY CORPORATION
- Wu-Der Yang
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES CONFIGURED WITH PULSE ADJUSTMENT AND METHODS FOR OPE...
- Publication number 20250124966
- Publication date Apr 17, 2025
- Taiwan Semiconductor Manufacturing Company, Ltd.
- Hidehiro Fujiwara
- G11 - INFORMATION STORAGE
Information Patent Application
CONTROL UNIT OF MEMORY AND METHOD OF CONTROLLING MEMORY
- Publication number 20250124973
- Publication date Apr 17, 2025
- NANYA TECHNOLOGY CORPORATION
- Wu-Der Yang
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS INCLUDING CLOCK INPUT BUFFER
- Publication number 20250118356
- Publication date Apr 10, 2025
- Micron Technology, Inc.
- Yasuhiro Takai
- G11 - INFORMATION STORAGE

Timing circuits

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Method and system for refresh of memory devices

Word line delay interlock circuit for write operation

Read clock start and stop for synchronous memories

Selectable row hammer mitigation

Memory controller operable in data loop-back mode

Memory activation timing management

Pseudo-static random access memory

Techniques for determining an interface connection status

Signal skew in source-synchronous system

Method for signal transmission, circuit and memory

Memory device and memory system

Bank-level self-refresh

Convertible memory device

Circuit module with reliable margin configuration

Efficient and low power reference voltage mixing

Phase correction circuit, and clock buffer and semiconductor appara...

Pseudo-static random-access memory and reading method thereof

Apparatus with data-rate-based voltage control mechanism and method...

Reading from a mode register having different read and write timing

Method of generating a multi-level signal using selective equalizat...

Write operation assist circuit

Input data pre-alignment circuit capable of performing a first-in f...

Apparatus including parallel pipelines and methods of manufacturing...

Methods for enhanced memory context restore

Power supply circuit, memory, testing device, memory system, and el...

Apparatus with non-linear delay variations for scheduling memory re...

Automated voltage demarcation (VDM) adjustment for memory device

Read clock start and stop for synchronous memories

Semiconductor device having duty-cycle corrector

Management of dynamic read voltage sequences in a memory subsystem

Patents Applicationslast 30 patents

APPARATUSES, SYSTEMS, AND METHODS FOR ODT PULSE WIDTH DURATION DETE...

MEMORYS, OPERATION METHODS THEREOF AND MEMORY SYSTEMS

COMMAND TIMING CONTROL CIRCUIT AND MEMORY

MEMORY CIRCUIT AND METHOD OF OPERATING SAME

APPARATUS WITH NON-LINEAR REFRESH MECHANISM AND METHODS FOR OPERATI...

OFFSET CALIBRATION METHOD AND APPARATUS FOR HIGH BANDWIDTH MEMORY 3...

MEMORY DEVICE AND SYSTEM, AND DECODING CIRCUIT

MEMORY DEVICES AND OPERATING METHODS THEREOF, MEMORY SYSTEMS, AND S...

MEMORY DEVICE, OPERATION METHOD, AND MEMORY SYSTEM

MANAGEMENT OF DYNAMIC READ VOLTAGE SEQUENCES IN A MEMORY SUBSYSTEM

GAIN-CELL RANDOM ACCESS MEMORY WITH ENHANCED RETENTION

MEMORY DEVICE CAPABLE OF ADJUSTING CLOCK SIGNAL BASED ON OPERATING...

SEMICONDUCTOR DEVICE PERFORMING LOOPBACK OPERATION

SEMICONDUCTOR MEMORY DEVICES HAVING EFFICIENT SERIALIZERS THEREIN F...

MEMORY WITH DEFERRED FRACTIONAL ROW ACTIVATION

SEMICONDUCTOR DEVICES RELATED TO THE GENERATION OF A COMMAND

SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME

DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICE, MEMORY BANK OF DRAM DEV...

AUTOMATED VOLTAGE DEMARCATION (VDM) ADJUSTMENT FOR MEMORY DEVICE

IN-MEMORY COMPUTING (IMC) MEMORY DEVICE AND IN-MEMORY COMPUTING METHOD

APPARATUSES AND METHODS FOR REDUCED POWER COMMAND SHIFTER

SEMICONDUCTOR DEVICE PERFORMING REPLICA ROUTING

APPARATUSES AND METHODS FOR INPUT RECEIVER CIRCUITS AND RECEIVER MA...

LAYOUT FOR DUAL IN-LINE MEMORY TO SUPPORT 128-BYTE CACHE LINE PROCE...

MEMORY SYSTEM AND RECEIVER

SEMICONDUCTOR DEVICE AND MEMORY DEVICE INCLUDING COMPLEMENTARY DELA...

CONTROL UNIT OF MEMORY AND METHOD OF CONTROLLING MEMORY

MEMORY DEVICES CONFIGURED WITH PULSE ADJUSTMENT AND METHODS FOR OPE...

CONTROL UNIT OF MEMORY AND METHOD OF CONTROLLING MEMORY

APPARATUS INCLUDING CLOCK INPUT BUFFER