Digital stores characterised by the use of particular electric or magnetic storage elements Storage elements therefor

GPHYSICS G11Information storage G11CSTATIC STORES

G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements Storage elements therefor

G11C11/005comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells G11C11/02using magnetic elements G11C11/04using rod-type storage elements G11C11/06using single-aperture storage elements G11C11/06007using a single aperture or single magnetic closed circuit G11C11/06014using one such element pro bit G11C11/06021with destructive read-out G11C11/06028Matrixes G11C11/06035"bit"- organised, e.g. 2 1/2D, 3D or a similar organisation G11C11/06042"word"-organised, e.g. 2D organisation or linear selection G11C11/0605with non-destructive read-out G11C11/06057Matrixes G11C11/06064"bit"-organised (2 1/2D, 3D or similar organisation) G11C11/06071"word"-organised (2D organisation or linear selection) G11C11/06078using two or more such elements pro bit G11C11/06085Multi-aperture structures or multi-magnetic closed circuits, each aperture storing a "bit", realised by rods, plates, grids, waffle-irons,( G11C11/06092Multi-aperture structures or multi-magnetic closed circuits using two or more apertures per bit G11C11/061using element with single aperture or magnetic loop for storage, one element per bit, and for destructive read-out G11C11/063bit organised, such as 2 1/2D, 3D organisation G11C11/065word organised, such as 2D organisation, or linear selection G11C11/067using elements with single aperture or magnetic loop for storage, one element per bit, and for non-destructive read-out G11C11/08using multi-aperture storage elements G11C11/10using multi-axial storage elements G11C11/12using tensors using twistors G11C11/14using thin-film elements G11C11/15using multiple magnetic layers G11C11/155with cylindrical configuration G11C11/16using elements in which the storage effect is based on magnetic spin effect G11C11/161details concerning the memory cell structure G11C11/165Auxiliary circuits G11C11/1653Address circuits or decoders G11C11/1655Bit-line or column circuits G11C11/1657Word-line or row circuits G11C11/1659Cell access G11C11/1673Reading or sensing circuits or methods G11C11/1675Writing or programming circuits or methods G11C11/1677Verifying circuits or methods G11C11/1693Timing circuits or methods G11C11/1695Protection circuits or methods G11C11/1697Power supply circuits G11C11/18using Hall-effect devices G11C11/19using non-linear reactive devices in resonant circuits G11C11/20using parametrons G11C11/21using electric elements G11C11/22using ferroelectric elements G11C11/221using ferroelectric capacitors G11C11/223using MOS with ferroelectric gate insulating film G11C11/225Auxiliary circuits G11C11/2253Address circuits or decoders G11C11/2255Bit-line or column circuits G11C11/2257Word-line or row circuits G11C11/2259Cell access G11C11/2273Reading or sensing circuits or methods G11C11/2275Writing or programming circuits or methods G11C11/2277Verifying circuits or methods G11C11/2293Timing circuits or methods G11C11/2295Protection circuits or methods G11C11/2297Power supply circuits G11C11/23using electrostatic storage on a common layer G11C11/24using capacitors G11C11/26using discharge tubes G11C11/265counting tubes G11C11/28using gas-filled tubes G11C11/30using vacuum tubes G11C11/34using semiconductor devices G11C11/35with charge storage in a depletion layer G11C11/36using diodes, e.g. as threshold elements G11C11/38using tunnel diodes G11C11/39using thyristors or the avalanche or negative resistance type G11C11/40using transistors G11C11/401forming cells needing refreshing or charge regeneration G11C11/402with charge regeneration individual to each memory cell G11C11/4023using field effect transistors G11C11/4026using bipolar transistors G11C11/403with charge regeneration common to a multiplicity of memory cells G11C11/404with one charge-transfer gate G11C11/4045using a plurality of serially connected access transistors, each having a storage capacitor G11C11/405with three charge-transfer gates G11C11/406Management or control of the refreshing or charge-regeneration cycles G11C11/40603Arbitration, priority and concurrent access to memory cells for read/write or refresh operations G11C11/40607Refresh operations in memory devices with an internal cache or data buffer G11C11/40611External triggering or timing of internal or partially internal refresh operations G11C11/40615Internal triggering or timing of refresh G11C11/40618Refresh operations over multiple banks or interleaving G11C11/40622Partial refresh of memory arrays G11C11/40626Temperature related aspects of refresh operations G11C11/4063Auxiliary circuits G11C11/4067for memory cells of the bipolar type G11C11/407for memory cells of the field-effect type G11C11/4072Circuits or initialisation, powering up or down, clearing memory or presetting G11C11/4074Power supply or voltage generation circuits G11C11/4076Timing circuits G11C11/4078Safety or protection circuits G11C11/408Address circuits G11C11/4082Address Buffers; level conversion circuits G11C11/4085Word line control circuits G11C11/4087Address decoders G11C11/409Read-write (R-W) circuits G11C11/4091Sense or sense/refresh amplifiers, or associated sense circuitry G11C11/4093Input/output (I/O) data interface arrangements G11C11/4094Bit-line management or control circuits G11C11/4096Input/output (I/O) data management or control circuits G11C11/4097Bit-line organisation G11C11/4099Dummy cell treatment Reference voltage generators G11C11/41forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration G11C11/411using bipolar transistors only G11C11/4113with at least one cell access to base or collector of at least one of said transistors G11C11/4116with at least one cell access via separately connected emittors of said transistors or via multiple emittors G11C11/412using field-effect transistors only G11C11/4125Cells incorporating circuit means for protection against loss of information G11C11/413Auxiliary circuits G11C11/414for memory cells of the bipolar type G11C11/415Address circuits G11C11/416Read-write circuits G11C11/417for memory cells of the field-effect type G11C11/418Address circuits G11C11/419Read-write circuits G11C11/42using opto-electronic devices G11C11/44using super-conductive elements G11C11/46using thermoplastic elements G11C11/48using displaceable coupling elements G11C11/50using actuation of electric contacts to store the information G11C11/52using electromagnetic relays G11C11/54using elements simulating biological cells G11C11/56using storage elements with more than two stable states represented by steps G11C11/5607using magnetic storage elements G11C11/5614using conductive bridging RAM [CBRAM] or programming metallization cells [PMC] G11C11/5621using charge storage in a floating gate G11C11/5628Programming or writing circuits; Data input circuits G11C11/5635Erasing circuits G11C11/5642Sensing or reading circuits; Data output circuits G11C11/565using capacitive charge storage elements G11C11/5657using ferroelectric storage elements G11C11/5664using organic memory material storage elements G11C11/5671using charge trapping in an insulator G11C11/5678using amorphous/crystalline phase transition storage elements G11C11/5685using storage elements comprising metal oxide memory material G11C11/5692read-only digital stores using storage elements with more than two stable states