using a bus scheme (

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GPHYSICS G06Computing G06FELECTRICAL DIGITAL DATA PROCESSING G06F12/00Accessing, addressing or allocating within memory systems or architectures

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G06F12/0831using a bus scheme (

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Patents Grantslast 30 patents

Information Patent Grant
Cache size change
- Patent number 12,271,314
- Issue date Apr 8, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for managing data bias in a graphics processin...
- Patent number 12,260,470
- Issue date Mar 25, 2025
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Eviction operations based on eviction message types of different pr...
- Patent number 12,248,401
- Issue date Mar 11, 2025
- SiFive, Inc.
- Michael Klinglesmith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory interface having multiple snoop processors
- Patent number 12,235,767
- Issue date Feb 25, 2025
- Imagination Technologies Limited
- Martin John Robinson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore, multibank, fully concurrent coherence controller
- Patent number 12,223,165
- Issue date Feb 11, 2025
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Shared memory for intelligent network interface cards
- Patent number 12,204,471
- Issue date Jan 21, 2025
- Intel Corporation
- Francesc Guim Bernat
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 12,197,357
- Issue date Jan 14, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hardware coherence signaling protocol
- Patent number 12,197,331
- Issue date Jan 14, 2025
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic extension and de-allocation of cache coherence snoop filter...
- Patent number 12,189,533
- Issue date Jan 7, 2025
- Microsoft Technology Licensing, LLC
- Eric Francis Robinson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High performance interconnect
- Patent number 12,189,550
- Issue date Jan 7, 2025
- Intel Corporation
- Robert J. Safranek
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual network pre-arbitration for deadlock avoidance and enhanced...
- Patent number 12,182,398
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Matthew David Pierson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multicore shared cache operation engine
- Patent number 12,159,030
- Issue date Dec 3, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Global coherence operations
- Patent number 12,141,601
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Configurable cache for coherent system
- Patent number 12,141,435
- Issue date Nov 12, 2024
- Texas Instruments Incorporated
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Machine learning sparse computation mechanism
- Patent number 12,141,891
- Issue date Nov 12, 2024
- Intel Corporation
- Eriko Nurvitadhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache coherence shared state suppression
- Patent number 12,135,646
- Issue date Nov 5, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses, methods, and systems for dynamic bypassing of last lev...
- Patent number 12,130,739
- Issue date Oct 29, 2024
- Intel Corporation
- Ayan Mandal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatuses and methods for a processor architecture
- Patent number 12,130,740
- Issue date Oct 29, 2024
- Intel Corporation
- Jason W. Brandt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing system with direct invalidation in a hierarchical cache s...
- Patent number 12,086,065
- Issue date Sep 10, 2024
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Weilin Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive credit-based replenishment threshold used for transaction...
- Patent number 12,079,471
- Issue date Sep 3, 2024
- Texas Instruments Incorporated
- Daniel Brad Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tag update bus for updated coherence state
- Patent number 12,056,051
- Issue date Aug 6, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache management operations using streaming engine
- Patent number 12,050,914
- Issue date Jul 30, 2024
- Texas Instruments Incorporated
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pseudo-random way selection
- Patent number 12,045,644
- Issue date Jul 23, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-level cache security
- Patent number 12,038,840
- Issue date Jul 16, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipeline arbitration
- Patent number 12,014,206
- Issue date Jun 18, 2024
- Texas Instruments Incorporated
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable system on a chip
- Patent number 12,007,895
- Issue date Jun 11, 2024
- Apple Inc.
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computing system with write-back and invalidation in a hierarchical...
- Patent number 11,971,821
- Issue date Apr 30, 2024
- SHANGHAI ZHAOXIN SEMICONDUCTOR CO., LTD.
- Weilin Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache systems for main and speculative threads of processors
- Patent number 11,954,493
- Issue date Apr 9, 2024
- Micron Technology, Inc.
- Steven Jeffrey Wallach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scalable cache coherency protocol
- Patent number 11,947,457
- Issue date Apr 2, 2024
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Handling memory requests
- Patent number 11,941,430
- Issue date Mar 26, 2024
- Imagination Technologies Limited
- Mark Landers
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MACHINE LEARNING SPARSE COMPUTATION MECHANISM
- Publication number 20250117873
- Publication date Apr 10, 2025
- Intel Corporation
- Eriko Nurvitadhi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTITIONED HOME SNOOP FILTER
- Publication number 20250110879
- Publication date Apr 3, 2025
- Intel Corporation
- Kiran Kumar Akella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SNOOP FILTER SCALABILITY
- Publication number 20250110880
- Publication date Apr 3, 2025
- NUMASCALE AS
- Thibaut PALFER-SOLLIER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Controller Reservation of Retry Queue
- Publication number 20250103520
- Publication date Mar 27, 2025
- Apple Inc.
- Ilya Granovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fast Synchronization Mechanism for Heterogeneous Computing
- Publication number 20250103498
- Publication date Mar 27, 2025
- MEDIATEK INC.
- Hsing-Chuang Liu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTICORE SHARED CACHE OPERATION ENGINE
- Publication number 20250094044
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai Chirca
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REAL-TIME SNOOP STATUS
- Publication number 20250077430
- Publication date Mar 6, 2025
- International Business Machines Corporation
- Scot RIDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE CACHE FOR COHERENT SYSTEM
- Publication number 20250060873
- Publication date Feb 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECTORY-LESS SNOOP OFFLOAD OF A HIGHER LEVEL CACHE MANAGEMENT AGE...
- Publication number 20250053514
- Publication date Feb 13, 2025
- International Business Machines Corporation
- Scot RIDER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OPPORTUNISTIC CLEANING OF COHERENCE DIRECTORIES TO REDUCE CACHE-COH...
- Publication number 20250053513
- Publication date Feb 13, 2025
- Samsung Electronics Co., Ltd.
- Samantika Subramaniam Sury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR INTERFERENCE AVOIDANCE IN MEMOR...
- Publication number 20250028647
- Publication date Jan 23, 2025
- Samsung Electronics Co., Ltd.
- Patrick Anthony LA FRATTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
GLOBAL COHERENCE OPERATIONS
- Publication number 20250028551
- Publication date Jan 23, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE COHERENCE SHARED STATE SUPPRESSION
- Publication number 20250013569
- Publication date Jan 9, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC EXTENSION AND DE-ALLOCATION OF CACHE COHERENCE SNOOP FILTER...
- Publication number 20240427703
- Publication date Dec 26, 2024
- Microsoft Technology Licensing, LLC
- Eric Francis ROBINSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable System on a Chip
- Publication number 20240411695
- Publication date Dec 12, 2024
- Apple Inc.
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, DEVICE AND STORAGE MEDIUM FOR REQUEST PROCESSING UNDER MIXE...
- Publication number 20240385964
- Publication date Nov 21, 2024
- HEXIN Technologies (Suzhou) Co., Ltd.
- Yangfan LIU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE
- Publication number 20240385840
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Joseph Raymond Michael Zbiciak
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable System on a Chip
- Publication number 20240370371
- Publication date Nov 7, 2024
- Apple Inc.
- Per H. Hammarlund
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PSEUDO-RANDOM WAY SELECTION
- Publication number 20240345868
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAG UPDATE BUS FOR UPDATED COHERENCE STATE
- Publication number 20240345956
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS, METHODS, AND APPARATUS FOR COMPUTATIONAL DEVICE COMMUNICAT...
- Publication number 20240338315
- Publication date Oct 10, 2024
- Samsung Electronics Co., Ltd.
- Changho CHOI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LEVEL CACHE SECURITY
- Publication number 20240320154
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PIPELINE ARBITRATION
- Publication number 20240281278
- Publication date Aug 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok CHACHAD
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Scalable Cache Coherency Protocol
- Publication number 20240273024
- Publication date Aug 15, 2024
- Apple Inc.
- James Vash
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE SYSTEMS FOR MAIN AND SPECULATIVE THREADS OF PROCESSORS
- Publication number 20240264840
- Publication date Aug 8, 2024
- Micron Technology, Inc.
- Steven Jeffrey Wallach
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SNOOP FILTER FOR LARGE CACHE USING HASH TECHNIQUE WITH OPTIMAL REFR...
- Publication number 20240202124
- Publication date Jun 20, 2024
- Intel Corporation
- Israel Diamand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS
- Publication number 20240184446
- Publication date Jun 6, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Kai CHIRCA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
AN EFFICIENT AND SCALABLE ARCHITECTURE AND METHOD FOR ISOGENY-BASED...
- Publication number 20240184699
- Publication date Jun 6, 2024
- PQSecure Technologies, LLC
- Rami El Khatib
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSIN...
- Publication number 20240177264
- Publication date May 30, 2024
- Intel Corporation
- Joydeep Ray
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONTROLLER WITH CACHING AND NON-CACHING MODES
- Publication number 20240152385
- Publication date May 9, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Abhijeet Ashok Chachad
- G06 - COMPUTING CALCULATING COUNTING

using a bus scheme (

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Cache size change

Apparatus and method for managing data bias in a graphics processin...

Eviction operations based on eviction message types of different pr...

Memory interface having multiple snoop processors

Multicore, multibank, fully concurrent coherence controller

Shared memory for intelligent network interface cards

High performance interconnect

Hardware coherence signaling protocol

Dynamic extension and de-allocation of cache coherence snoop filter...

High performance interconnect

Virtual network pre-arbitration for deadlock avoidance and enhanced...

Multicore shared cache operation engine

Global coherence operations

Configurable cache for coherent system

Machine learning sparse computation mechanism

Cache coherence shared state suppression

Apparatuses, methods, and systems for dynamic bypassing of last lev...

Apparatuses and methods for a processor architecture

Computing system with direct invalidation in a hierarchical cache s...

Adaptive credit-based replenishment threshold used for transaction...

Tag update bus for updated coherence state

Cache management operations using streaming engine

Pseudo-random way selection

Multi-level cache security

Pipeline arbitration

Scalable system on a chip

Computing system with write-back and invalidation in a hierarchical...

Cache systems for main and speculative threads of processors

Scalable cache coherency protocol

Handling memory requests

Patents Applicationslast 30 patents

MACHINE LEARNING SPARSE COMPUTATION MECHANISM

PARTITIONED HOME SNOOP FILTER

SNOOP FILTER SCALABILITY

Memory Controller Reservation of Retry Queue

Fast Synchronization Mechanism for Heterogeneous Computing

MULTICORE SHARED CACHE OPERATION ENGINE

REAL-TIME SNOOP STATUS

CONFIGURABLE CACHE FOR COHERENT SYSTEM

DIRECTORY-LESS SNOOP OFFLOAD OF A HIGHER LEVEL CACHE MANAGEMENT AGE...

OPPORTUNISTIC CLEANING OF COHERENCE DIRECTORIES TO REDUCE CACHE-COH...

SYSTEMS, METHODS, AND APPARATUS FOR INTERFERENCE AVOIDANCE IN MEMOR...

GLOBAL COHERENCE OPERATIONS

CACHE COHERENCE SHARED STATE SUPPRESSION

DYNAMIC EXTENSION AND DE-ALLOCATION OF CACHE COHERENCE SNOOP FILTER...

Scalable System on a Chip

METHOD, DEVICE AND STORAGE MEDIUM FOR REQUEST PROCESSING UNDER MIXE...

CACHE MANAGEMENT OPERATIONS USING STREAMING ENGINE

Scalable System on a Chip

PSEUDO-RANDOM WAY SELECTION

TAG UPDATE BUS FOR UPDATED COHERENCE STATE

SYSTEMS, METHODS, AND APPARATUS FOR COMPUTATIONAL DEVICE COMMUNICAT...

MULTI-LEVEL CACHE SECURITY

PIPELINE ARBITRATION

Scalable Cache Coherency Protocol

CACHE SYSTEMS FOR MAIN AND SPECULATIVE THREADS OF PROCESSORS

SNOOP FILTER FOR LARGE CACHE USING HASH TECHNIQUE WITH OPTIMAL REFR...

MULTI-PROCESSOR BRIDGE WITH CACHE ALLOCATE AWARENESS

AN EFFICIENT AND SCALABLE ARCHITECTURE AND METHOD FOR ISOGENY-BASED...

APPARATUS AND METHOD FOR MANAGING DATA BIAS IN A GRAPHICS PROCESSIN...

CONTROLLER WITH CACHING AND NON-CACHING MODES