using a chain of bistable devices

Industry

CPC
H03K5/15033

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Parent Industries

HELECTRICITY H03Electronic circuits H03KPULSE TECHNIQUE H03K5/00Manipulating pulses not covered by one of the other main groups in this subclass

Current Industry

H03K5/15033using a chain of bistable devices

Industries

Patents Grantslast 30 patents

Information Patent Grant
Low-power inter-die communication using delay lines
- Patent number 11,695,400
- Issue date Jul 4, 2023
- QUALCOMM Incorporated
- Sameer Wadhwa
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clocking circuit and method for time-interleaved analog-to-digital...
- Patent number 10,790,845
- Issue date Sep 29, 2020
- The Boeing Company
- Alfio Zanchi
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Asynchronous clock signal generator and semiconductor device for co...
- Patent number 10,566,961
- Issue date Feb 18, 2020
- SK Hynix Inc.
- Seonggyu Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Folded divider architecture
- Patent number 10,418,982
- Issue date Sep 17, 2019
- STMicroelectronics Asia Pacific PTE Ltd.
- Beng-Heng Goh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Asynchronous clock signal generator and semiconductor device for co...
- Patent number 10,250,243
- Issue date Apr 2, 2019
- SK Hynix Inc.
- Seonggyu Lee
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Folded divider architecture
- Patent number 10,079,593
- Issue date Sep 18, 2018
- STMicroelectronics Asia Pacific PTE Ltd.
- Beng-Heng Goh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Folded divider architecture
- Patent number 9,847,778
- Issue date Dec 19, 2017
- STMicroelectronics Asia Pacific PTE Ltd.
- Beng-Heng Goh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock transmission circuit and semiconductor integrated circuit
- Patent number 9,748,938
- Issue date Aug 29, 2017
- SOCIONEXT INC.
- Shigeaki Kawai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock selection system and method
- Patent number 9,209,792
- Issue date Dec 8, 2015
- NVIDIA Corporation
- Gary A. Browning
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Dynamic divider having interlocking circuit
- Patent number 9,088,285
- Issue date Jul 21, 2015
- QUALCOMM Incorporated
- Jeremy Mark Goldblatt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Receiving apparatus and receiving method
- Patent number 8,693,604
- Issue date Apr 8, 2014
- Fujitsu Limited
- Michio Hibi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Phase-error reduction circuitry for an IQ generator
- Patent number 8,174,301
- Issue date May 8, 2012
- Fujitsu Semiconductor Limited
- Robert Braun
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Semiconductor device for synchronous communication between stacked LSI
- Patent number 7,994,822
- Issue date Aug 9, 2011
- Hitachi, Ltd.
- Kazuo Otsuga
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Timing control circuit and semiconductor storage device
- Patent number 7,973,582
- Issue date Jul 5, 2011
- Elpida Memory, Inc.
- Akira Ide
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Integrated circuit devices generating a plurality of drowsy clock s...
- Patent number 7,567,109
- Issue date Jul 28, 2009
- Samsung Electronics Co., Ltd.
- Uk-Song Kang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pulse generator using latch and control signal generator having the...
- Patent number 7,394,303
- Issue date Jul 1, 2008
- Samsung Electronics Co., Ltd.
- Do-Kyung Kim
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Multi-phase edge rate control for SCSI LVD
- Patent number 6,661,271
- Issue date Dec 9, 2003
- LSI Logic Corporation
- Brian E. Burdick
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and method for producing a plurality of output signals wi...
- Patent number 6,253,066
- Issue date Jun 26, 2001
- Motorola, Inc.
- Jeffrey B. Wilhite
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and method for producing a plurality of output signals wi...
- Patent number 5,930,689
- Issue date Jul 27, 1999
- Motorola, Inc.
- Jeffrey B. Wilhite
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Timing generator circuit including adjustable tapped delay line wit...
- Patent number 5,159,205
- Issue date Oct 27, 1992
- Burr-Brown Corporation
- James L. Gorecki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Option/sequence selection circuit with sequence selection first
- Patent number 5,003,201
- Issue date Mar 26, 1991
- Goldstar Semiconductor Co., Ltd.
- Jong K. Bai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Clock generator which generates a non-overlap clock having fixed pu...
- Patent number 4,877,974
- Issue date Oct 31, 1989
- Mitsubishi Denki Kabushiki Kaisha
- Hiroyuki Kawai
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Wide range multiple time mark generator
- Patent number 4,323,851
- Issue date Apr 6, 1982
- The United States of America as represented by the Secretary of the Air Force
- Walter M. Shedd
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Sequential logical electronic circuit controlling the discharge of...
- Patent number 4,300,059
- Issue date Nov 10, 1981
- Ramon G. Chavez
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FET load gate compensator
- Patent number 3,996,481
- Issue date Dec 7, 1976
- International Business Machines Corporation
- William M. Chu
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Grant
3914698
- Patent number 3,914,698
- Issue date Oct 21, 1975
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
3760580
- Patent number 3,760,580
- Issue date Sep 25, 1973
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
3660691
- Patent number 3,660,691
- Issue date May 2, 1972
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
3634886
- Patent number 3,634,886
- Issue date Jan 11, 1972
- G01 - MEASURING TESTING
Information Patent Grant
3575593
- Patent number 3,575,593
- Issue date Apr 20, 1971
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR GENERATING CIRCUIT CLOCK SIGNAL
- Publication number 20240305284
- Publication date Sep 12, 2024
- Beijing Youzhuju Network Technology Co., Ltd.
- Junyan GUO
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
LOW-POWER INTER-DIE COMMUNICATION USING DELAY LINES
- Publication number 20240056067
- Publication date Feb 15, 2024
- QUALCOMM Incorporated
- Sameer WADHWA
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ASYNCHRONOUS CLOCK SIGNAL GENERATOR AND SEMICONDUCTOR DEVICE FOR CO...
- Publication number 20190181846
- Publication date Jun 13, 2019
- SK HYNIX INC.
- Seonggyu LEE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FOLDED DIVIDER ARCHITECTURE
- Publication number 20180367129
- Publication date Dec 20, 2018
- STMicroelectronics Asia Pacific Pte. Ltd.
- Beng-Heng Goh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ASYNCHRONOUS CLOCK SIGNAL GENERATOR AND SEMICONDUCTOR DEVICE FOR CO...
- Publication number 20180175843
- Publication date Jun 21, 2018
- SK HYNIX INC.
- Seonggyu LEE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FOLDED DIVIDER ARCHITECTURE
- Publication number 20180083606
- Publication date Mar 22, 2018
- STMicroelectronics Asia Pacific Pte. Ltd.
- Beng-Heng Goh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FOLDED DIVIDER ARCHITECTURE
- Publication number 20170346470
- Publication date Nov 30, 2017
- STMicroelectronics Asia Pacific Pte. Ltd.
- Beng-Heng Goh
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
CLOCK TRANSMISSION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT
- Publication number 20160261256
- Publication date Sep 8, 2016
- SOCIONEXT INC.
- Shigeaki KAWAI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC DIVIDER HAVING INTERLOCKING CIRCUIT
- Publication number 20140376683
- Publication date Dec 25, 2014
- Jeremy Mark Goldblatt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR DEVICE
- Publication number 20100182046
- Publication date Jul 22, 2010
- Hitachi, Ltd.
- Kazuo Otsuga
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Receiving apparatus and receiving method
- Publication number 20090141846
- Publication date Jun 4, 2009
- FUJITSU LIMITED
- Michio Hibi
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
PHASE-ERROR REDUCTION CIRCUITRY FOR AN IQ GENERATOR
- Publication number 20090135968
- Publication date May 28, 2009
- FUJITSU LIMITED
- Robert BRAUN
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE
- Publication number 20090066390
- Publication date Mar 12, 2009
- Elpida Memory, Inc.
- Akira IDE
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Integrated circuit devices generating a plurality of drowsy clock s...
- Publication number 20070200609
- Publication date Aug 30, 2007
- SAMSUNG ELECTRONICS CO., LTD.
- Uk-Song Kang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PULSE GENERATOR USING LATCH AND CONTROL SIGNAL GENERATOR HAVING THE...
- Publication number 20070096791
- Publication date May 3, 2007
- Do-Kyung Kim
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Application
MULTI-PHASE EDGE RATE CONTROL FOR SCSI LVD
- Publication number 20030222689
- Publication date Dec 4, 2003
- LSI Logic Corporation
- Brian E. Burdick
- H03 - BASIC ELECTRONIC CIRCUITRY

using a chain of bistable devices

Industry

Parent Industries

Current Industry

Patents Grantslast 30 patents

Low-power inter-die communication using delay lines

Clocking circuit and method for time-interleaved analog-to-digital...

Asynchronous clock signal generator and semiconductor device for co...

Folded divider architecture

Asynchronous clock signal generator and semiconductor device for co...

Folded divider architecture

Folded divider architecture

Clock transmission circuit and semiconductor integrated circuit

Clock selection system and method

Dynamic divider having interlocking circuit

Receiving apparatus and receiving method

Phase-error reduction circuitry for an IQ generator

Semiconductor device for synchronous communication between stacked LSI

Timing control circuit and semiconductor storage device

Integrated circuit devices generating a plurality of drowsy clock s...

Pulse generator using latch and control signal generator having the...

Multi-phase edge rate control for SCSI LVD

Apparatus and method for producing a plurality of output signals wi...

Apparatus and method for producing a plurality of output signals wi...

Timing generator circuit including adjustable tapped delay line wit...

Option/sequence selection circuit with sequence selection first

Clock generator which generates a non-overlap clock having fixed pu...

Wide range multiple time mark generator

Sequential logical electronic circuit controlling the discharge of...

FET load gate compensator

3914698

3760580

3660691

3634886

3575593

Patents Applicationslast 30 patents

APPARATUS AND METHOD FOR GENERATING CIRCUIT CLOCK SIGNAL

LOW-POWER INTER-DIE COMMUNICATION USING DELAY LINES

ASYNCHRONOUS CLOCK SIGNAL GENERATOR AND SEMICONDUCTOR DEVICE FOR CO...

FOLDED DIVIDER ARCHITECTURE

ASYNCHRONOUS CLOCK SIGNAL GENERATOR AND SEMICONDUCTOR DEVICE FOR CO...

FOLDED DIVIDER ARCHITECTURE

FOLDED DIVIDER ARCHITECTURE

CLOCK TRANSMISSION CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT

DYNAMIC DIVIDER HAVING INTERLOCKING CIRCUIT

SEMICONDUCTOR DEVICE

Receiving apparatus and receiving method

PHASE-ERROR REDUCTION CIRCUITRY FOR AN IQ GENERATOR

TIMING CONTROL CIRCUIT AND SEMICONDUCTOR STORAGE DEVICE

Integrated circuit devices generating a plurality of drowsy clock s...

PULSE GENERATOR USING LATCH AND CONTROL SIGNAL GENERATOR HAVING THE...

MULTI-PHASE EDGE RATE CONTROL FOR SCSI LVD